EPM9320RC208-15N vs EPM9320RC208-15 Comparison
Detailed side-by-side comparison of EPM9320RC208-15N by Intel and EPM9320RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-15N | EPM9320RC208-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | 320 |
| Flip-Flops | 484 | — |
| Configurable I/O Lines | 128 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Clock Frequency | 117.6 MHz | 117.6 MHz |
| Supply Voltage | 5.0 V | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| Configuration Technology | CMOS EEPROM (non-volatile) | EEPROM-based (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (ISP via JTAG) |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (Power QFP) |
| Terminal Pitch | 0.5 mm | — |
| Operating Temperature Range | 0C to +70C (commercial) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 9000 |
| Pin-to-Pin Propagation Delay | — | 15 ns (speed grade -15) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Package Type | — | 208-BFQFP Exposed Pad |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Logic Array Blocks | — | [DATA_NEEDED: LAB count] |
| Lifecycle Status | — | Obsolete (PDN0706, 2007) |