EPM9480RC208-15N vs EPM9320RC208-15N Comparison
Detailed side-by-side comparison of EPM9480RC208-15N by Altera and EPM9320RC208-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9480RC208-15N | EPM9320RC208-15N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 10,000 | 6,000 |
| Macro Cells | 480 | 320 |
| Maximum Frequency | 117.6 MHz | — |
| Propagation Delay | 15 ns (speed grade -15) | — |
| Supply Voltage | 5.0 V | 5.0 V |
| Package | 208-pin RQFP | 208-pin RQFP (PowerQuad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | — |
| RoHS Status | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level | MSL 3 (168 Hours) | — |
| Manufacturer Standard Lead Time | 1-7 Days | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| Flip-Flops | — | 484 |
| Configurable I/O Lines | — | 128 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Clock Frequency | — | 117.6 MHz |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Configuration Technology | — | CMOS EEPROM (non-volatile) |
| Terminal Pitch | — | 0.5 mm |
| Operating Temperature Range | — | 0C to +70C (commercial) |
| Packaging | — | Tray |