EPM9560RC208-10N vs EPM9560RC208-20N Comparison

Detailed side-by-side comparison of EPM9560RC208-10N by Intel and EPM9560RC208-20N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM9560RC208-10N EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N ⚠ Last Time Buy

Specification Comparison

Parameter EPM9560RC208-10N EPM9560RC208-20N
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $175.00 $0.00
Family MAX 9000 β€”
Device EPM9560 β€”
Macro Cells 560 β€”
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 16 β€”
User I/O Pins 153 149
Pin-to-Pin Delay (tPD1) 10 ns β€”
Supply Voltage (VCCINT) 5.0 V β€”
I/O Bank Voltage (VCCIO) 5.0 V β€”
Package 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (PowerQuad Flat Pack)
Mounting Type Surface Mount Surface Mount
Process Technology CMOS EEPROM β€”
Programmability In-system via IEEE 1149.1 JTAG β€”
Operating Temperature [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature range]
RoHS Status [DATA_NEEDED: RoHS status] Lead-free (N suffix)
Device Family β€” MAX 9000 (EPM9560)
Macrocells β€” 560
Propagation Delay (tPD) β€” 20 ns
Supply Voltage β€” 5.0 V
Configuration Technology β€” EEPROM (non-volatile)
In-System Programmability β€” Yes, via IEEE Std. 1149.1 JTAG
JTAG Interface β€” IEEE Std. 1149.1
Logic Architecture β€” Multiple Array MatriX (MAX), third-generation CMOS EEPROM
Flip-Flops β€” 772 (per EPM9560 series data)
Speed Grade β€” -20 (20 ns)
MSL Level β€” [DATA_NEEDED: MSL level]

Datasheets & Resources

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