EPM9560RC208-12 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-12 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-12 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | — |
| Flip-Flops | 772 | — |
| Usable Gates | 12000 | 12,000 gates |
| User I/O Lines | 153 | — |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Clock Frequency | 125 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| Package | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (Power Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | — |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| Logic Array Blocks | 20 | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | -12 (12 ns) | -15 (15 ns pin-to-pin) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Supply Voltage | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |