EPM9560RC208-15C vs EPM9560RC208-12 Comparison
Detailed side-by-side comparison of EPM9560RC208-15C by Altera and EPM9560RC208-12 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-15C | EPM9560RC208-12 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD (EPLD) | EEPROM-based CPLD |
| Usable Gates | 12,000 | 12000 |
| Macrocells | 560 | 560 |
| User I/O Pins | 149 | — |
| Propagation Delay (tPD) | 15 ns | 12 ns |
| Maximum Counter Frequency | 117.6 MHz | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| I/O Voltage Compatibility | 3.3 V or 5 V | 3.3 V or 5 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Package | 208-pin RQFP | 208-pin RQFP (S-PQFP-G208) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | 0C to +70C (commercial) | — |
| Speed Grade | -15 (15 ns) | -12 (12 ns) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Architecture | Multiple Array MatriX (MAX) third generation | — |
| Flip-Flops | — | 772 |
| User I/O Lines | — | 153 |
| Maximum Clock Frequency | — | 125 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| Terminal Pitch | — | 0.50 mm |
| Operating Temperature | — | 0C to +70C (commercial) |
| Logic Array Blocks | — | 20 |