MCIMX31CVMN4C vs MCIMX31LCVMN4C Comparison

Detailed side-by-side comparison of MCIMX31CVMN4C by NXP Semiconductors and MCIMX31LCVMN4C by NXP Semiconductors. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

NXP Semiconductors
MCIMX31CVMN4C MCIMX31CVMN4C - i.MX31 ARM1136 400MHz MPU, MAPBGA-473 | NXP

MCIMX31CVMN4C - i.MX31 ARM1136 400MHz MPU, MAPBGA-473 | NXP

MCIMX31CVMN4C ✗ End of Life
NXP Semiconductors
MCIMX31LCVMN4C MCIMX31LCVMN4C - i.MX31L ARM1136 400MHz MPU, MAPBGA-457 | NXP

MCIMX31LCVMN4C - i.MX31L ARM1136 400MHz MPU, MAPBGA-457 | NXP

MCIMX31LCVMN4C ⚠ Last Time Buy

Specification Comparison

Parameter MCIMX31CVMN4C MCIMX31LCVMN4C
Brand NXP Semiconductors NXP Semiconductors
Category Microcontrollers Microcontrollers
Lifecycle Status End of Life Last Time Buy
Stock Status In Stock In Stock
Unit Price (USD) $17.40 $10.50
Core Architecture ARM1136JF-S (ARMv6, 32-bit) ARM1136JF-S
Maximum Core Clock 400 MHz —
Core Count 1 1
Bit Width 32-bit —
Package 473-LFBGA / MAPBGA-473, 19 x 19 mm —
Product Family i.MX31 (Multimedia Applications Processor) —
Variant MCIMX31C (with on-chip graphics engine) —
Jazelle Technology Yes (Java bytecode acceleration) —
Memory Controller DDR / DDR2 SDRAM, NAND flash —
Display Interface Integrated LCD controller —
Image Sensor Interface CSI (Camera Sensor Interface) —
Connectivity Multiple serial interfaces (UART, SPI, I2C, USB) —
Operating Temperature -40C to +85C (industrial) —
Mounting Type Surface Mount (BGA) Surface Mount
RoHS Status [DATA_NEEDED: RoHS compliance] Compliant
ITAR / Trade Restriction Subject to US ITC order (BGA-packaged i.MX31 family) —
Data Bus Width — 16-bit
Maximum Clock Frequency — 400 MHz
Operating Temperature Range — -40C to +85C
Package Type — MAPBGA-457
Package Dimensions — 14 x 14 mm
Ball Pitch — 0.5 mm
Pin Count — 457
Family — i.MX31L
Variant Suffix — N4C (industrial/auto temp grade)
Process Node — [DATA_NEEDED: process node]
L1 Cache — [DATA_NEEDED: L1 instruction/data cache]
L2 Cache — [DATA_NEEDED: L2 cache]
Integrated LCD Controller — Yes
USB Interface — USB 2.0 with on-chip PHY
Image Processing Unit (IPU) — Yes
AEC-Q100 Grade — Grade 3

Datasheets & Resources

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