MPC8533EVTAQGA vs MPC8536EAVTAQG Comparison
Detailed side-by-side comparison of MPC8533EVTAQGA by NXP Semiconductors and MPC8536EAVTAQG by NXP Semiconductors. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
NXP Semiconductors
MPC8533EVTAQGA - PowerQUICC III 1GHz SoC, 783-FCBGA | NXP
MPC8533EVTAQGA ✓ ActiveNXP Semiconductors
MPC8536EAVTAQG - PowerQUICC III 1GHz e500 MPU | NXP/Freescale
MPC8536EAVTAQG NrndSpecification Comparison
| Parameter | MPC8533EVTAQGA | MPC8536EAVTAQG |
|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors |
| Category | Microcontrollers | Microcontrollers |
| Lifecycle Status | Active | NRND |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $38.50 | $218.75 |
| Family | PowerQUICC III | — |
| Core Architecture | PowerPC e500v2 | — |
| Core Count | 1 | — |
| Data Bus Width | 32-bit | 32 bit |
| Maximum Core Frequency | 1.0 GHz | — |
| L1 Cache | 32 KB I-cache + 32 KB D-cache | — |
| L2 Cache | 256 KB (per core, on-chip) | — |
| Memory Controller | DDR1/DDR2 with ECC | — |
| Ethernet | 3x 10/100/1000 Mb/s MAC (1 GbE) | — |
| PCI Express | 2x PCIe interfaces | — |
| PCI | 1x PCI 32-bit/66 MHz | — |
| USB | USB 2.0 (host/device) | — |
| Security Engine | SEC 2.0 (IPSec/SSL/SRTP) | — |
| Operating Temperature | 0C to +90C (commercial) | [DATA_NEEDED: operating temperature range] |
| Package | 783-FCPBGA (29x29 mm) | 783-FCPBGA (29x29 mm) |
| Silicon Revision | Rev 2.1 | — |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS compliance] |
| Processor Series | — | MPC85xx (PowerQUICC III) |
| Core | — | PowerPC e500, 32-bit |
| Maximum Clock Frequency | — | 1.0 GHz |
| Number of Cores | — | 1 |
| Encryption Support | — | Yes ('E' suffix indicates encryption-enabled silicon) |
| Supply Voltage | — | [DATA_NEEDED: core/IO supply voltage] |
| Integrated Peripherals | — | QUICC Engine, DDR controller, Gigabit Ethernet, PCI Express |
| Instruction Set Architecture | — | Power Architecture (Book-E) |
| On-chip Cache | — | [DATA_NEEDED: L1/L2 cache configuration] |
| MSL Level | — | [DATA_NEEDED: MSL rating] |