RTAX250S-1LG624V vs RTAX250S-CG624E Comparison

Detailed side-by-side comparison of RTAX250S-1LG624V by Microchip Technology and RTAX250S-CG624E by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Microchip Technology
RTAX250S-1LG624V RTAX250S-1LG624V - 250K-Gate Rad-Tolerant FPGA 1.5V | Microchip

RTAX250S-1LG624V - 250K-Gate Rad-Tolerant FPGA 1.5V | Microchip

RTAX250S-1LG624V ✓ Active
Microchip Technology
RTAX250S-CG624E RTAX250S-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip

RTAX250S-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip

RTAX250S-CG624E ✓ Active

Specification Comparison

Parameter RTAX250S-1LG624V RTAX250S-CG624E
Brand Microchip Technology Microchip Technology
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $0.00
Family RTAX-S Radiation-Tolerant FPGA RTAX-S radiation-tolerant FPGA
Equivalent Gate Count 250000 gates —
Configurable Logic Blocks (CLBs) 2816 —
Logic Cells 4224 —
I/Os 248 —
Core Supply Voltage 1.5 V nominal 1.5 V
Speed Grade -1 —
Package CGA624 (LG624), 624-column ceramic column grid array —
Package Suffix V (leaded column finish) —
Operating Temperature -55C to +125C -55C to +125C
Technology CMOS, antifuse programmable —
Radiation Tolerance Radiation-tolerant (RTAX-S family, SEU-tolerant) [DATA_NEEDED: TID and SEU LET figures] —
Configuration Live at power-up, single chip, no boot PROM —
Mounting Type Surface Mount Surface Mount
MSL Level [DATA_NEEDED: MSL level] —
RoHS Status [DATA_NEEDED: RoHS status - ceramic space-grade package typically exempt] —
Lifecycle Status Active —
System Gates — 250000 gates
Logic Cells (CLBs) — 2816
Maximum Toggle Frequency — 649 MHz
Process Technology — 0.15 um CMOS
Logic Family — CMOS
CLB Combinatorial Delay (max) — 0.930 ns
Package Type — CCGA-624 (ceramic column grid array, 624 pins)
Programming Technology — Antifuse (one-time programmable)
SEU Hardening — SEU-hardened registers, no external TMR required
SEU Immunity — Immune to single-event upsets to specified LET threshold; SEU rate < 10-10 errors/bit-day
Power-Up Behavior — Live at power-up (true single-chip)
Target Application — Space-flight systems

Datasheets & Resources

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