RTAX250SL-LG624V vs RTAX250S-CG624E Comparison
Detailed side-by-side comparison of RTAX250SL-LG624V by Microchip Technology and RTAX250S-CG624E by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
RTAX250SL-LG624V - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-LG624V ✓ ActiveMicrochip Technology
RTAX250S-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250S-CG624E ✓ ActiveSpecification Comparison
| Parameter | RTAX250SL-LG624V | RTAX250S-CG624E |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,620.00 | $0.00 |
| Equivalent System Gates | 250000 gates | — |
| Configurable Logic Blocks (CLBs) | 2816 | — |
| Logic Cells | 4224 | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V |
| User I/O | 248 | — |
| Package | 624-pin LGA (LG624) | — |
| Family | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs | RTAX-S radiation-tolerant FPGA |
| Program Technology | Anti-fuse, one-time programmable | — |
| Configuration | Live at power-up, single chip | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | — |
| Clocking | Segmentable clocks, chip-wide highway routing | — |
| Radiation Tolerance | Radiation-tolerant, SEU-mitigated (SL variant) | — |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS Status] | — |
| Operating Temperature | [DATA_NEEDED: Operating Temperature] | -55C to +125C |
| System Gates | — | 250000 gates |
| Logic Cells (CLBs) | — | 2816 |
| Maximum Toggle Frequency | — | 649 MHz |
| Logic Family | — | CMOS |
| CLB Combinatorial Delay (max) | — | 0.930 ns |
| Package Type | — | CCGA-624 (ceramic column grid array, 624 pins) |
| Programming Technology | — | Antifuse (one-time programmable) |
| SEU Hardening | — | SEU-hardened registers, no external TMR required |
| SEU Immunity | — | Immune to single-event upsets to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| Power-Up Behavior | — | Live at power-up (true single-chip) |
| Target Application | — | Space-flight systems |