STM32F411VEH6TR vs STM32F411VET6TR Comparison
Detailed side-by-side comparison of STM32F411VEH6TR by STMicroelectronics and STM32F411VET6TR by STMicroelectronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
STMicroelectronics
STM32F411VEH6TR - ARM Cortex-M4 100MHz 512KB MCU | STMicroelectronics
STM32F411VEH6TR ✓ ActiveSTMicroelectronics
STM32F411VET6TR - 100MHz Cortex-M4 MCU 512KB Flash | STMicroelectronics
STM32F411VET6TR ✓ ActiveSpecification Comparison
| Parameter | STM32F411VEH6TR | STM32F411VET6TR |
|---|---|---|
| Brand | STMicroelectronics | STMicroelectronics |
| Category | Microcontrollers | Microcontrollers |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.95 | $5.42 |
| Core | ARM Cortex-M4 with FPU | — |
| Maximum Clock Frequency | 100 MHz | 100 MHz |
| Performance | 125 DMIPS / 273 CoreMark | 125 DMIPS / 273 CoreMark |
| Program Memory (Flash) | 512 KB | 512 KB |
| SRAM | 128 KB | 128 KB |
| Supply Voltage (VDD) | 1.7 V to 3.6 V | 1.7 V to 3.6 V |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C (grade 6) |
| ADC | 1 x 12-bit, 2.4 MSPS, up to 16 channels | 3x 12-bit, 2.4 MSPS |
| Timers | 11 (including 32-bit and motor-control timers) | — |
| Communication Interfaces | 13 (USART, SPI, I2C, I2S, SDIO, USB OTG FS) | — |
| USB | USB 2.0 Full-Speed OTG with on-chip PHY | USB 2.0 OTG Full-Speed with on-chip PHY |
| Package | UFBGA-100 (7x7 mm) | 100-LQFP (14x14 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Backup SRAM | 4 KB with battery domain | — |
| RTC | Yes, with calendar and alarm | — |
| RoHS Status | Compliant | Compliant |
| MSL Level | 3 | — |
| Core Architecture | — | ARM Cortex-M4 with FPU and DSP |
| GPIO Count | — | 81 |
| DAC | — | 2x 12-bit |
| CAN | — | 1x CAN 2.0B |
| SDMMC | — | Yes |
| External Memory Bus | — | Yes (SRAM/NOR/NAND) |
| DMA | — | 2x 7-channel controllers |
| ART Accelerator | — | 8 KB instruction cache |