XC6SLX45-2CSG484I vs XC6SLX45-2CSG484C Comparison

Detailed side-by-side comparison of XC6SLX45-2CSG484I by AMD and XC6SLX45-2CSG484C by AMD. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

AMD
XC6SLX45-2CSG484C XC6SLX45-2CSG484C - Spartan-6 LX FPGA, 43,661 Logic Cells | AMD

XC6SLX45-2CSG484C - Spartan-6 LX FPGA, 43,661 Logic Cells | AMD

XC6SLX45-2CSG484C ⚠ Last Time Buy

Specification Comparison

Parameter XC6SLX45-2CSG484I XC6SLX45-2CSG484C
Brand AMD AMD
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Last Time Buy
Device Type Spartan-6 LX field-programmable gate array (FPGA) —
Logic Cells 43,661 logic cells —
Adaptive Logic Modules 6,822 ALMs —
Embedded Memory 2.04 Mbit —
Process Technology 45 nm CMOS 45 nm CMOS, 9-metal copper low-k
Core Operating Voltage 1.2 V —
Internal Frequency 500 MHz —
Speed Grade -2 -2
Package 484-pin CSBGA 484-ball CSBGA (CSPBGA, 19 x 19 mm, 0.8 mm pitch)
Package Dimensions 15 mm x 15 mm —
Package Pitch 0.80 mm —
Ball Count 484 balls —
Operating Temperature 0°C to 85°C —
Mounting Type Surface mount Surface Mount (BGA, requires microvia PCB)
Lead-Free Status Lead free —
Device Series Spartan-6 LX —
Product Type Programmable logic device —
Number of I/O Pins [DATA_NEEDED: number of user I/O pins] —
Block RAM Capacity [DATA_NEEDED: block RAM capacity in bits] —
DSP Slice Count [DATA_NEEDED: DSP slice count] —
Configuration Interface [DATA_NEEDED: supported configuration interface types] —
Family — Spartan-6 LX
Device Logic Cells — 43,661
CLBs / LABs — 3,411
Slices — 6,822
Distributed RAM (Kb) — [DATA_NEEDED: distributed RAM Kb]
Block RAM (bits) — 2,138,112 (~261 Kib)
DSP48A1 Slices — 58
User I/O Count — 320
Maximum User I/O (per datasheet) — [DATA_NEEDED: max user I/O value]
Operating Temperature (Commercial) — 0 C to +85 C
Core Supply Voltage (VCCINT) — 1.2 V (range 1.14 V to 1.26 V)
Auxiliary Supply Voltage (VCCAUX) — 3.3 V
IO Supply Voltage (VCCO) — 1.2 V to 3.3 V (per bank)
Internal Frequency (max) — 500 MHz
MSL Level — 3 (per JEDEC J-STD-020)
RoHS / Lead-free — Compliant / Pb-free (lead-free)
Configuration Modes — JTAG, Slave Serial, SPI, BPI
Transceivers — None (LX variant; LXT variant required for GTP)

Datasheets & Resources

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