Takt & Timing

Si5368

Si5368 - Sub-1ps Jitter Clock Multiplier | Skyworks

The Skyworks Solutions Si5368 is a jitter-attenuating precision clock multiplier delivering sub 1 ps rms jitter performance, accepting four clock inputs from 2 kHz to 710 MHz and generating five synchronous outputs from 2 kHz to 945 MHz with select frequencies to 1.4 GHz, housed in a 100-pin TQFP package. A precision clock multiplier/jitter attenuator is a timing IC that takes a noisy or offset-frequency reference clock and synthesizes a new, ultra-clean output clock at virtually any required frequency. Within the system hierarchy, it sits under clock generation and distribution ICs, part of the broader clock and timing category of semiconductors that also includes oscillators, buffers, and frequency translators. Unlike simple PLL multipliers, jitter cleaners use a two-stage architecture with an internal VCXO-style loop to strip reference noise. Key features include any-frequency synthesis from 2 kHz to 945 MHz (select outputs to 1.4 GHz), support for LVPECL, LVDS, CML, and CMOS signal formats on five independent outputs, and holdover and freerun operating modes for reference loss conditions. Four selectable input clocks enable automatic reference switchover in redundant-timing systems. Technically, the Si5368 is built on Silicon Laboratories' third-generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL that eliminates the need for an external VCXO and loop filter components. This integration reduces board area, BOM cost, and loop-filter tuning effort compared to discrete PLL plus VCXO designs. Typical applications include line-card and optical-transport clock recovery and cleanup for SONET/SDH rates, 10G/40G/100G Ethernet and OTN retiming subsystems, and test-and-measurement instrumentation requiring sub-picosecond clock purity. When designing with the Si5368, follow the manufacturer datasheet recommendations for power-supply filtering of the analog PLL supplies and use a clean reference; jitter attenuation degrades if the loop bandwidth is misconfigured relative to input jitter. This page synthesizes distributor availability, drop-in family alternatives, comparison data, and practical design notes not found in the manufacturer datasheet alone.

Si5369

Si5369 - Any-Frequency Jitter Attenuating Clock | Skyworks

The Skyworks Solutions (formerly Silicon Labs) Si5369 is an any-frequency precision clock multiplier and jitter attenuator that generates any frequency from 2 kHz to 945 MHz and select frequencies up to 1.4 GHz from an input frequency of 2 kHz to 710 MHz, housed in a 100-pin TQFP package with jitter generation as low as 300 fs rms. A jitter attenuating clock multiplier (also called a jitter cleaner or precision clock IC) is a phase-locked-loop-based timing device that takes a noisy or frequency-mismatched reference clock and produces one or more ultra-clean output clocks. Within the timing hierarchy, it sits above simple clock oscillators and below full network synchronization modules, combining a digital PLL, integrated VCO, and programmable loop filter in a single clock management IC. Key features include ultra-low jitter generation of 300 fs rms (12 kHz-20 MHz bandwidth on B/D grades), an integrated loop filter with selectable loop bandwidth, and any-frequency synthesis via Silicon Labs' dsPLL architecture that eliminates external VCXO selection. The selectable loop bandwidth allows designers to trade jitter transfer versus jitter tolerance for SONET/SDH, OTN, or Ethernet compliance. Technically, the Si5369 uses a third-generation dsPLL (digitally synthesized PLL) with an integrated low-noise VCO and an on-chip loop filter configurable from tens of Hz to several kHz, removing the need for external loop-filter component design. Frequency plans are computed in-circuit, so a single stock part supports thousands of output/input frequency combinations, reducing BOM proliferation. Typical applications include line-card and transport synchronization in SONET/SDH and OTN equipment, jitter cleaning for 10G/40G Ethernet PHYs, low-jitter clocking for high-speed ADC/DAC converters, and reference distribution in wireless base stations and test instrumentation. A key design consideration is that loop bandwidth selection directly governs jitter transfer: tight bandwidths attenuate input jitter best but increase lock time, so choose the bandwidth setting per the applicable jitter tolerance mask. This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet alone.