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EPM5128LC-1 - 128-Macrocell MAX 5000 CPLD | Altera | 5V 68-Pin PLCC
EPM5128LC-1

EPM5128LC-1 - 128-Macrocell MAX 5000 CPLD | Altera | 5V 68-Pin PLCC

The Altera EPM5128LC-1 is a 128-macrocell, UV-erasable/OTP CMOS Complex Programmable Logic Device (CPLD) from the legacy MAX 5000 family, housed in a 68-terminal J-lead ceramic chip carrier (windowed/erasable package) and rated for commercial 5V operation. Built on a 5 µm double-metal EPROM process, the device combines high logic density with predictable, deterministic 30 ns pin-to-pin delay, enabling straightforward replacement of discrete SSI/MSI glue logic. It provides 7 dedicated inputs and 52 bidirectional I/O pins for up to 60 inputs and 52 outputs, with 128 macrocells distributed across the MAX classic Logic Array Block (LAB) fabric. A Complex Programmable Logic Device (CPLD) is a non-volatile, electrically programmable logic IC that integrates multiple PAL/GAL-like macrocell arrays onto a single die with a global interconnect matrix. Within the broader hierarchy, the EPM5128LC-1 sits as: CPLD -> programmable logic device -> logic IC -> semiconductor IC. CPLDs are favored over discrete TTL/CMOS glue logic because they offer deterministic timing, lower board area, lower power, and field re-programmability, while remaining far simpler to use than FPGA & CPLD-class SRAM-based FPGAs. Key features include 128 macrocells, 52 user I/O pins, 7 dedicated input pins, an internal tpd of 30 ns, and an industry-standard 4-pin JTAG (IEEE 1149.1) interface for in-system boundary-scan testing and ISP. The device is offered in the LC package suffix - a windowed ceramic J-lead PLCC that supports UV erasure and re-programming, which makes the LC variant especially valuable for prototyping, design iteration, and low-volume engineering builds. Typical applications include address decoding for 8/16-bit microprocessor and microcontroller systems, bus-interface glue logic between legacy peripherals, board-level control sequencers, and retrocomputing or industrial controller logic. The wide 5V operating range and CMOS input thresholds make the EPM5128LC-1 compatible with TTL and CMOS logic families used in 1980s-1990s designs. When designing with this device, verify JTAG chain order against other boundary-scan devices and note that Altera legacy MAX 5000 software support requires MAX+PLUS II or Quartus in legacy compatibility mode.

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EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera
EPM5128LC2

EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera

The Altera EPM5128LC2 is a high-density, high-speed CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, providing 128 macrocells organized into 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). It operates from a single 5 V supply and offers a pin-to-pin propagation delay of 45 ns, making it suitable for replacing multiple TTL/74-series glue-logic packages with a single in-system programmable device. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines the integration density of an FPGA with the deterministic timing and instant-on behavior of classic PAL/GAL architectures. Within the broader semiconductor hierarchy, CPLDs sit alongside FPGAs under the programmable-logic umbrella, but unlike SRAM-based FPGAs they retain their configuration in on-chip EPROM/EEPROM cells and require no external boot memory. The MAX 5000 series specifically targets TTL-compatible, 5 V-only glue-logic consolidation and bus-interface replacement in industrial control, telecommunications, and legacy computer designs. Key features of the EPM5128LC2 include 128 macrocells, 8 LABs linked by a global PIA, 1 dedicated global clock input plus shared input/clock pins, JTAG/IEEE 1149.1 boundary-scan support, and an extended operating temperature grade. The device is offered in a Pin-Grid-Array (PGA) ceramic package suitable for socketed or through-hole industrial assemblies, with the 'LC2' suffix indicating the lower-power CMOS process and the commercial speed/power grade. Architecturally, the MAX 5000 device uses an EPROM-based configuration cell so the programmed logic is retained without power, enabling true instant-on behavior at power-up - a defining advantage over SRAM FPGAs in deterministic boot applications. Each macrocell contains a programmable AND/OR array with a flip-flop, and the deterministic PIA routing provides predictable, fixed propagation delays that simplify static timing closure in control and interface designs. Typical applications include TTL/74-series glue-logic consolidation in industrial controllers, address decoding and bus interfacing in legacy x86 and embedded CPU designs, state-machine and sequencer replacement in telecommunications line cards, and I/O expansion for microprocessor-based systems. The 5 V supply, ceramic packaging, and -40 C to +85 C extended commercial operating range also suit it to harsh-environment industrial equipment. When designing with the EPM5128LC2, engineers should note that the MAX 5000 family has been classified as mature/EOL by Altera (now part of Intel), so long-term production planning and last-time-buy windows must be confirmed with the manufacturer before committing to new designs. Use the Altera MAX+PLUS II or Altera Quartus legacy support tools for design entry, fitting, and programming of this older device. This page synthesizes distributor pricing, same-brand drop-in alternatives from the MAX 5000 family, and practical design notes that go beyond what the manufacturer datasheet alone provides.

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EPM5130GI - 128-Macrocell MAX 5000 UV PLD | Altera
EPM5130GI

EPM5130GI - 128-Macrocell MAX 5000 UV PLD | Altera

The Altera EPM5130GI is a UV-erasable, high-density CMOS Programmable Logic Device (PLD) from the classic MAX 5000 family, delivering 128 macrocells organized into 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). It supports one global external clock, provides 19 dedicated inputs, 68 total inputs, and 48 bidirectional I/O lines, with a propagation delay (tPD) of 55 ns and a maximum clock frequency of 33.3 MHz, all housed in a ceramic Pin Grid Array (PGA) windowed package suitable for prototype and low-volume engineering work. What is a Programmable Logic Device (PLD)? A PLD is a general-purpose digital integrated circuit whose internal logic function is defined by the end user rather than the device vendor. PLDs sit in the broader taxonomy of logic semiconductors, beneath programmable logic and above fixed-function gate arrays, and historically bridge the gap between discrete 7400-series SSI/MSI TTL packages and modern FPGAs. The MAX 5000 family is a second-generation multi-level AND-OR architecture that consolidated dozens of SSI/MSI functions into one programmable part, an early step toward the high-density CPLDs and FPGAs that dominate today's logic design landscape. Key features of the EPM5130GI include a 100% generic, JTAG-free architecture with 100% interconnect coverage between LABs and macrocells, individual macrocell register control, programmable output polarity, and a 5 V CMOS core compatible with TTL input levels. Programmable output slew-rate control, 100% testable with a high fault coverage, and a ceramic-windowed PGA package suitable for erasure by ultraviolet light round out the silicon feature set. The MAX 5000 architecture separates logic from I/O using a Programmable Interconnect Array (PIA) that is fixed in delay regardless of routing, simplifying timing analysis. Each macrocell contains a programmable AND/OR/Register structure with a D flip-flop and a tri-state output buffer, allowing every output to be configured as combinatorial or registered. The PIA delays are predictable, which historically allowed the MAX 5000 family to replace large amounts of SSI/MSI logic with a single, fully deterministic device. Typical applications for the EPM5130GI include legacy industrial control glue logic, bus-interface address decoding, state-machine implementation, and replacement of large SSI/MSI TTL boards. The 55 ns tPD makes the device suitable for microprocessorial peripheral decoding, peripheral-interface state machines, and older control systems where the surrounding logic is still 5 V TTL. When designing with this part, note that the 'GI' suffix denotes a ceramic PGA windowed (UV-erasable) package intended for prototype and engineering use; production users normally move to the plastic-windowless or one-time-programmable variants after design freeze. Power sequencing should respect standard 5 V CMOS rails, and unused I/O pins must be left floating per MAX 5000 family guidelines. This page synthesizes distributor pricing, drop-in alternatives, and engineering notes not found in the original Altera datasheet alone, so that designers maintaining legacy systems can quickly evaluate the EPM5130GI against modern and same-family substitutes.

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EPM5130GM883B - Military CPLD, MAX 5000, 100-pin CPGA | Altera
EPM5130GM883B

EPM5130GM883B - Military CPLD, MAX 5000, 100-pin CPGA | Altera

The Altera EPM5130GM883B is a high-density, high-speed CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, screened to MIL-STD-883B specifications and housed in a 100-terminal Ceramic Pin Grid Array (CPGA) package designated S-CPGA-P100. The /883B suffix indicates Class B MIL-STD-883 screening, which qualifies the device for aerospace, defense, and other high-reliability programs requiring extended temperature operation and traceability. The MAX 5000 architecture combines multiple Logic Array Blocks (LABs) and a programmable interconnect array, providing non-volatile, instant-on logic with deterministic timing suitable for replacing multiple SSI/MSI glue-logic devices. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple PLDs and FPGAs in the programmable logic hierarchy. CPLDs use EEPROM or flash-based configuration cells and a continuous, predictable routing fabric with predictable pin-to-pin delays. Compared to discrete 74-series logic, a CPLD reduces board area, simplifies BOM, and adds design flexibility, while offering faster, more deterministic timing than an FPGA. The EPM5130GM883B is one of the highest-density members of the legacy MAX 5000 family, with up to 5,000 usable gates, making it appropriate for state machines, address decoding, bus arbitration, and peripheral control in legacy military systems. Key features include up to 5,000 usable gates, 128 macrocells, up to 60 user I/O pins, propagation delays on the order of 15 ns, and a 5 V tolerant core designed for TTL-compatible logic levels. The non-volatile EEPROM configuration means the device powers up fully operational without external boot memory, which is critical for safety-critical systems where determinism at power-on is mandatory. Programmable security bits protect the user's design against reverse engineering. The EPM5130GM883B utilizes Altera's MAX architecture with multiple Logic Array Blocks (LABs), each containing 16 macrocells. Each macrocell contains a programmable AND/OR array, a flip-flop, and configurable I/O architecture. The hierarchical interconnect network (PIA) provides predictable routing delays regardless of fan-out, which is a defining advantage over FPGA-based solutions. Typical applications include military avionics, aerospace flight-control subsystems, missile guidance electronics, radar signal processing front-ends, and legacy defense retrofit programs where long-term product lifecycle and MIL-STD-883B traceability are required. The 5 V tolerance and instant-on behavior suit it for retrofits into older 5 V digital designs. A key design consideration when using this part is that the MAX 5000 family is mature/legacy. Engineers should validate long-term availability, second-source the design where possible, and consider newer MAX II/MAX V CPLDs in 3.3 V designs unless MIL-STD-883 screening is mandatory. This page synthesizes distributor pricing, MIL-STD-883B screening details, application context, and design notes that are not aggregated in a single datasheet source. Information reflects the Altera MAX 5000 datasheet family and distributor inventory snapshots as of 2026-09-12.

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EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000
EPM5130JC-1

EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000

The Altera (now Intel) EPM5130JC-1 is a high-density UV-erasable CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, featuring 2,500 usable gates organized as 128 macrocells in 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), housed in an 84-pin PLCC package. The device operates from a single 5 V supply with 128 macrocells, supports a maximum clock frequency of 62.5 MHz, and delivers a pin-to-pin propagation delay of 40 ns at commercial-grade timing. A Complex Programmable Logic Device (CPLD) is a non-volatile, flash- or EPROM-backed programmable logic IC that combines the integration density of an FPGA with the deterministic timing, instant-on behavior, and simple programming model of a classic PLD. Within the broader programmable-logic taxonomy, the MAX 5000 sits between classic 7400-series SSI/MSI glue logic and modern SRAM-based FPGAs; it functions as a glue-logic replacement, bus-interface bridge, or state-machine engine in industrial, telecom, and military systems where deterministic 5 ns-class pin-to-pin delays and zero-config startup are mandatory. Key features include 19 dedicated inputs, a shared input/clock architecture, 80 I/O pins in the 84-pin PLCC package, and one global clock pin with user-configurable polarity. The architecture uses 100% CMOS EEPROM cells (for MAX 5000AE variants) or EPROM (for the EPM5130 JC-1, which is UV-erasable through a quartz window). Logic is implemented using sum-of-products expressions evaluated by the AND-OR array, with each macrocell containing a programmable flip-flop, select-mux, and feedback path. Typical applications include industrial-control state machines, bus-interface glue logic (8086/68000 glue), address decoding, DRAM controller glue, and legacy 7400-series logic consolidation. The device's 5 V tolerance and deterministic timing also make it suitable for replacing multiple discrete TTL/CMOS packages in designs where PCB real estate is at a premium. This page synthesizes distributor stock, drop-in same-package alternatives from the MAX 5000 family, and design notes that complement the manufacturer datasheet.

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EPM5130JI - 128-Macrocell MAX 5000 EPLD, 33.3 MHz | Altera
EPM5130JI

EPM5130JI - 128-Macrocell MAX 5000 EPLD, 33.3 MHz | Altera

The Altera EPM5130JI is a CMOS UV-erasable programmable logic device (EPLD) from the MAX 5000 family, featuring 128 macrocells organized into 8 Logic Array Blocks (LABs) interconnected through a Programmable Interconnect Array (PIA), and housed in a ceramic-windowed J-lead package for in-system erasure with ultraviolet light. An EPLD (Erasable Programmable Logic Device) is a non-volatile, reprogrammable digital logic IC that predates modern flash-based CPLDs and FPGAs. The MAX 5000 family sits in the historical Altera (now Intel) product lineage as a high-density, high-speed CMOS EPLD family built around a sum-of-products macrocell architecture with a unified interconnect matrix. This places the EPM5130JI in the hierarchy: macrocell -> LAB -> EPLD -> programmable logic device -> digital IC -> semiconductor. Key features include a maximum clock frequency of 33.3 MHz, a propagation delay of 55 ns (tPD), 1 dedicated external clock input with shared input/clock pin capability, and a 100% factory-tested logic macrocell count of 128. The device is built on a 0.75-micron CMOS EPROM process and is packaged in a ceramic J-leaded chip carrier (JLCC) with a quartz erasure window - a hallmark of the MAX 5000 family. The EPM5130 architecture uses a Programmable Interconnect Array to route signals between LABs, providing fast, predictable timing for state-machine and glue-logic designs. The 128 macrocells each contain a programmable AND/OR array and a configurable flip-flop, supporting registered, combinatorial, and buried logic. Power consumption is roughly 250 mW at typical CMOS supply levels, and inputs are TTL-compatible. Typical applications include legacy telecom interface glue logic, industrial control state machines, prototyping platforms for ASIC replacement, and educational laboratory courses on programmable logic. The UV window allows engineers to erase and re-program the device dozens of times, making it attractive for design iteration. When designing with the EPM5130JI, note that the ceramic JLCC package requires a through-hole socket or careful hand-soldering and that UV erasure takes 20-30 minutes of exposure to 12,000 uW/cm² UV light. The device operates from a single 5V supply and is a commercial-temperature-grade part. This page synthesizes legacy distributor stock data, J-lead package information, and cross-family replacement guidance not consolidated in the original Altera datasheet, helping engineers evaluate the part for both new designs and legacy repair scenarios.

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EPM5130LC - 128-Macrocell MAX 5000 UV-Erasable CPLD | Altera
EPM5130LC

EPM5130LC - 128-Macrocell MAX 5000 UV-Erasable CPLD | Altera

The Altera EPM5130LC is a 128-macrocell, UV-erasable/OTP Complex Programmable Logic Device (CPLD) from Altera's MAX 5000 family, fabricated in CMOS technology and housed in a J-Lead Ceramic Chip Carrier (JLCC) package. It delivers a pin-to-pin propagation delay of 55 ns, supports a maximum internal clock frequency of 50 MHz, and provides 8 Logic Array Blocks interconnected by a Programmable Interconnect Array (PIA). The device integrates 19 dedicated inputs and 48 bidirectional I/O lines, totaling 68 inputs, and is supplied across a 4.5 V to 5.5 V VCC range with TTL-compatible I/O. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that uses EPROM, EEPROM, or flash memory cells to store configuration. The MAX 5000 family predates the MAX 7000/3000 series and belongs to Altera's classic UV-erasable/OTP taxonomy, sitting at the base of the programmable logic hierarchy: CPLD -> PLD (Programmable Logic Device) -> programmable logic IC -> semiconductor. These parts retain their configuration when powered off and are widely used in glue-logic and bus-interface designs. Key features include 128 macrocells, 48 user I/O, 8 LABs, 1 global clock input, 68 total inputs (dedicated + I/O), and a 55 ns tPD. The chip is built on a 0.7 um CMOS EPROM process and supports in-system programming via Altera's A+PLUS or MAX+PLUS II toolchains. Typical applications include bus-interface and address decoding for legacy microprocessors, glue-logic replacement for 74LS/74F TTL gates, asynchronous state-machine controllers, and industrial control boards where UV-erasable parts are preferred for security reasons. Compared to SRAM-based FPGAs, the EPM5130LC is non-volatile and boots in microseconds. When designing with this device, ensure the VCC rail stays within 4.5 V to 5.5 V and account for the 55 ns propagation delay in worst-case timing analysis. Provide proper decoupling on VCC/GND pairs and respect the 48-I/O and 68-input budgets when allocating pins. This page synthesizes distributor pricing, drop-in MAX-family alternatives, and practical design notes not found in the original Altera datasheet, providing engineering value beyond raw parameter repetition.

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EPM5130QC-1 - MAX 5000 5130 Logic Cells UV-Erasable PLD | Altera
EPM5130QC-1

EPM5130QC-1 - MAX 5000 5130 Logic Cells UV-Erasable PLD | Altera

The Altera (Intel) EPM5130QC-1 is a UV-Erasable / OTP Complex Programmable Logic Device (CPLD) from the legacy MAX 5000 family, supplied in a 100-pin PQFP package with a 0.635 mm terminal pitch. Built on a CMOS process, the device integrates 5130 equivalent logic cells (macrocell class) intended for high-density glue-logic and state-machine replacement in digital systems. The "-1" speed grade and "QC" package code indicate a commercial-temperature grade PLD housed in a windowed ceramic PQFP suitable for prototype development and UV erasure reprogramming. A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on semiconductor that combines multiple PAL/GAL-style AND/OR arrays on a single die with on-chip programmable interconnect, EEPROM or EPROM storage, and a fixed number of macrocells. In the broader taxonomy, the CPLD sits between simple SPLDs (PAL/GAL) and FPGAs: it offers predictable timing, deterministic propagation delay, and pin-locking capability while providing significantly higher logic density than discrete 22V10/26V12-era PLDs. CPLDs are typically used as address decoders, bus interface bridges, peripheral glue, and state machines that need to boot in microseconds without external configuration memory. Key feature highlights of the EPM5130QC-1 include its 5130 usable gates (marketing name), 128 macrocells, EPROM-based UV-erasable non-volatile configuration, and a -1 speed grade aimed at general-purpose commercial logic integration. The device operates from a single 5 V supply, supports JTAG-style boundary-scan testing (per MAX 5000 family features), and offers output macrocells with programmable polarity, register/ combinatorial modes, and tri-state control. Compared with later MAX 7000/MAX II families, the MAX 5000 retains the older EPROM cell, requiring a quartz window package for erasure. Architecturally, the MAX 5000 family uses an EPROM-based AND array feeding a fixed OR array per macrocell, with each macrocell containing a flip-flop, output enable, and programmable polarity bit. Programming is performed via industry-standard device programmers and a JTAG/byte-blaster-like interface; erasure of windowed parts (QC package, ceramic) requires 20-30 minutes of 254 nm UV exposure. The 100-pin PQFP provides ample I/O for bus-oriented glue-logic tasks, and the 0.635 mm pitch is compatible with conventional surface-mount assembly and hand-soldered rework. Typical applications for the EPM5130QC-1 include industrial control boards, telecommunications equipment glue logic, address decoding for microprocessor/microcontroller systems, peripheral bus bridges (ISA-to-local bus, parallel-port expansion), and educational/prototype lab platforms that require an erasable, reprogrammable logic device. New designs are usually served by MAX II or MAX V devices, but the EPM5130QC-1 remains in service as a form-fit-function replacement for legacy boards where re-layout is impractical. When designing with the EPM5130QC-1, observe the I/O and supply sequencing rules documented in the MAX 5000 datasheet, and ensure all unused I/O pins are configured as outputs with the output-enable disabled or tied to defined logic levels. Because the part is UV-erasable only, a socket is recommended during firmware bring-up. For high-volume production where UV erasure is undesirable, consider migrating to a one-time-programmable (OTP) MAX 5000 variant or to a MAX 7000S / MAX II successor. This page synthesizes distributor pricing, drop-in same-package alternatives sourced from the Altera MAX 5000 family, datasheet availability, and design considerations that are not compiled in the original manufacturer datasheet PDF.

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EPM5130WC-1 - 128-Macrocell 40ns UV CPLD, 100-pin CQFP | Intel (Altera) MAX 5000
EPM5130WC-1

EPM5130WC-1 - 128-Macrocell 40ns UV CPLD, 100-pin CQFP | Intel (Altera) MAX 5000

The Intel (Altera) EPM5130WC-1 is a 128-macrocell ultraviolet-erasable CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, housed in a 100-pin ceramic windowed QFP (Ceramic Quad Flat Pack) package. It delivers a pin-to-pin propagation delay of 40 ns, a maximum clock frequency of 50 MHz, and a logic density suitable for glue-logic, state-machine, and bus-interface consolidation. The ceramic windowed package allows the device to be erased with UV light and reprogrammed, making it appropriate for prototyping and engineering development. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single die with a central interconnect matrix. CPLDs sit in the programmable logic hierarchy above simple PLDs and below FPGAs; they offer predictable timing, deterministic pin-to-pin delays, and instant-on configuration from on-chip EEPROM/EPROM, which makes them especially valuable in address decoding, peripheral control, and bus-interface bridging where sub-nanosecond timing guarantees are required. The EPM5130WC-1 supports up to 100 user I/O through the QFP package, integrates 128 macrocells across multiple Logic Array Blocks (LABs), and provides a programmable interconnect array that maintains consistent timing regardless of how a design is placed. Its UV-erasable windowed package allows iterative reprogramming during development cycles. The MAX 5000 architecture is fabricated on a CMOS EPROM process, providing non-volatile configuration storage. Architecturally, the MAX 5000 family uses a programmable AND/OR array feeding a configurable macrocell register that can be configured as combinational or registered output. Each macrocell includes a flip-flop with programmable clock, clear, and preset controls. The deterministic interconnect fabric guarantees a fixed propagation delay independent of routing density, simplifying static timing analysis. Typical applications include bus-interface glue logic, peripheral address decoding, state-machine controllers, and legacy industrial control systems that require UV-reprogrammable non-volatile logic. The ceramic QFP package is also suited to military and aerospace-grade designs with MIL-STD-883B screening variants available in the MAX 5000 family. When designing with the EPM5130WC-1, account for its 40 ns propagation delay when targeting high-speed bus interfaces and provide proper decoupling on all VCC pins. UV windowed ceramic packages require a label covering the quartz window after programming to prevent accidental erasure from ambient light exposure. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers source and qualify obsolete Altera MAX 5000 CPLDs.

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EPM5130WC-1AA - 128-Macrocell MAX 5000 PLD, 40ns, 50MHz | Altera
EPM5130WC-1AA

EPM5130WC-1AA - 128-Macrocell MAX 5000 PLD, 40ns, 50MHz | Altera

The Altera (Intel) EPM5130WC-1AA is a 128-macrocell UV-erasable programmable logic device (PLD) from the MAX 5000 family, offered in a Windowed Ceramic WQFP package with industrial-grade specifications. It features a propagation delay of 40 ns and a maximum clock frequency of 50 MHz, making it a legacy high-density general-purpose PLD for glue-logic and state-machine applications. A UV PLD (Ultra-Violet Erasable Programmable Logic Device) is a non-volatile, one-time or windowed-erasable CMOS logic device that lets designers implement custom combinatorial and registered logic. UV PLDs sit at the bottom of the programmable logic hierarchy, below EEPROM-based CPLDs and SRAM-based FPGAs, and were historically used as flexible pin-compatible replacements for 74-series TTL glue logic. The MAX 5000 family pioneered high-density, high-pin-count UV PLDs by integrating multiple PAL-like Logic Array Blocks (LABs) with a global interconnect, delivering the highest logic-to-pin ratio of any general-purpose PLD of its generation. Key features of the EPM5130WC-1AA include 128 macrocells with 48 dedicated I/O lines plus 19 dedicated inputs (68 total inputs and 48 outputs), 5 V CMOS technology, a maximum propagation delay (tPD) of 40 ns, and a maximum toggle frequency (fCNT) of 50 MHz. Programmable I/O architecture, sum-of-products logic synthesis, and JTAG-free boundary-scan testability were ahead-of-their-time features for early-1990s designs. The windowed ceramic package allows the device to be erased with UV light and reprogrammed many times, supporting iterative development. Architecturally, the EPM5130WC-1AA uses Altera's classic MAX (Multiple Array matriX) architecture: macrocells grouped into Logic Array Blocks share a programmable interconnect array (PIA), with each macrocell containing a programmable-AND/fixed-OR array, a flip-flop, and an output enable. The 5 V CMOS process ensures TTL-compatible inputs and high-drive outputs. Typical applications include legacy industrial control boards, military/aerospace systems requiring windowed-erasable PLDs, telecom interface logic, address decoding, and state-machine replacement of discrete 74LS/74F glue logic. The 50 MHz toggle rate allows it to service medium-speed bus interfaces and decoder pipelines. A key design consideration is end-of-life status: the MAX 5000 family has been NRND/obsolete for over a decade. New designs should use modern MAX II/MAX V CPLDs (e.g., EPM240, EPM570) as drop-in replacements in many cases, although pin-by-pin compatibility is rarely guaranteed. Engineers maintaining legacy systems should plan obsolescence mitigation. This page synthesizes distributor stock indicators, parametric comparison against same-family EPM5xxx variants, and practical design notes for legacy MAX 5000 systems not found in the original datasheet alone.

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EPM5130WC-2 - 128-Macrocell UV PLD MAX 5000 | Altera CQFP-100
EPM5130WC-2

EPM5130WC-2 - 128-Macrocell UV PLD MAX 5000 | Altera CQFP-100

The Altera EPM5130WC-2 is a high-density, UV-erasable programmable logic device (PLD) from Altera's MAX 5000 family, delivering 128 macrocells with 45 ns propagation delay in a 100-terminal ceramic CQFP (R-CQFP-G100) windowed package. It is built on a CMOS technology node, supports 19 dedicated inputs and 48 bidirectional I/O lines (totaling 68 inputs and 48 outputs), and operates from a single 5V supply (4.75 V to 5.25 V) at commercial 0°C to 70°C temperature range. The windowed ceramic package allows UV erasure and reprogramming of the on-chip EEPROM configuration cells, making this part suitable for prototype development and design iteration cycles where in-circuit reprogrammability is required. A Programmable Logic Device (PLD) is a digital integrated circuit whose logic function is defined by the user after manufacture, rather than being hard-wired at the fab. UV-erasable PLDs such as the MAX 5000 family sit within the broader taxonomy of programmable logic devices (PLDs -> CPLD/PLD -> programmable logic -> digital logic IC -> semiconductor). They are commonly positioned between discrete TTL/CMOS glue logic and FPGAs, offering deterministic timing, non-volatile configuration, and predictable pin-to-pin delays with far lower complexity than modern FPGAs. Key features of the EPM5130WC-2 include 128 macrocells, 45 ns worst-case pin-to-pin propagation delay (tPD), a 0.650 mm terminal pitch gull-wing CQFP-100 ceramic windowed package, single 5V supply operation, and 48 user I/O lines plus 19 dedicated inputs. The MAX 5000 architecture uses EEPROM configuration cells with multi-level AND/OR array logic, providing deterministic combinatorial and registered logic with predictable timing. The device's CMOS technology and MAX 5000 multi-level AND/OR array deliver high density for a 5V PLD with predictable, deterministic timing. Each macrocell includes a programmable register that can be configured as D, T, JK, or SR flip-flop with independent clock and reset, supporting state-machine and registered-logic designs at speeds suitable for control-plane applications. Typical applications include 5V logic replacement in legacy industrial control systems, bus-interface glue logic, address decoding for microprocessor systems, state-machine controllers, and prototype development using UV erasure. Designers favor the MAX 5000 family for its deterministic timing and rugged ceramic packaging. When designing with this device, verify the host PCB's footprint against the 100-terminal CQFP (R-CQFP-G100) land pattern with 0.650 mm pitch. Programming requires a compatible Altera programmer and a MAX+PLUS II or QUARTUS design flow; UV erasure needs a 254 nm UV lamp rated at approximately 25 W·s/cm² integrated dose. Note the part is no longer in active production - plan for last-time-buy or consider MAX 7000/MAX II family successors.

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EPM5130WM883B-1 - 128-Macrocell UV PLD, 5V, CQFP-100 | Altera MAX 5000
EPM5130WM883B-1

EPM5130WM883B-1 - 128-Macrocell UV PLD, 5V, CQFP-100 | Altera MAX 5000

The Intel (formerly Altera) EPM5130WM883B-1 is a 128-macrocell ultraviolet-erasable programmable logic device (UV PLD) from the MAX 5000 family, supplied in a ceramic-sealed CQFP-100 package and qualified to MIL-STD-883 Class B for high-reliability and military-aerospace applications. It is fabricated in CMOS technology and operates from a single 4.5V to 5.5V supply (nominal 5V), delivering a propagation delay of 55 ns and supporting clock frequencies up to 33.3 MHz. The architecture is built around 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), giving the part a regular, deterministic structure well suited to glue-logic replacement, state-machine implementation and decoder functions in legacy and ruggedised systems. A programmable logic device (PLD) is a non-volatile digital IC whose logic function and interconnect pattern are defined after manufacture by user programming. PLDs sit in the broader hierarchy: PLD -> SPLD/CPLD -> programmable logic -> digital semiconductor. The MAX 5000 series in particular is a Classic SPLD/EPLD line, predecessor to the modern MAX 7000 and MAX II/MAX V CPLD families. Erasable variants such as the EPM5130WM can be erased by exposing the die to UV light through the quartz window of the ceramic package, allowing the same part to be reprogrammed many times - valuable for prototyping and for low-volume production where mask-programmed logic is uneconomic. Key features include 128 macrocells, 19 dedicated inputs and 48 bi-directional I/O pins, one global clock input, and shared input/clock pins with programmable polarity. The I/O structure supports shared inputs and clocks to maximise usable pins and to simplify state-machine and counter designs. With a 55 ns propagation delay the device targets asynchronous logic at moderate frequencies and synchronous logic below 33.3 MHz. The 883B suffix indicates processing in accordance with MIL-STD-883, Test Method Standard for Microcircuits, and the additional '-1' speed/grade suffix denotes a specific propagation-delay bin within the 883B-screened family. The MAX 5000 architecture uses a sum-of-products AND/OR plane plus output macrocells with selectable registered/combinational modes and programmable feedback, allowing implementation of up to 128 product-term logic expressions per device. The 8 LABs feed a central PIA that routes signals between blocks, providing predictable timing that does not depend on placement - a useful property for safety-critical and DO-254 style designs. The device is non-volatile (UV-erasable rather than SRAM-based), so it powers up into the programmed configuration with no external boot memory. Typical applications include military and aerospace avionics, industrial control glue logic, telecom line-card interface logic, instrumentation front-end state machines, and legacy system redesigns where the original PAL/GAL and bipolar PLD must be replaced by a denser, CMOS-equivalent part. The MIL-STD-883B screening also makes it a candidate for ruggedised industrial platforms requiring wider temperature operation and guaranteed baseline reliability. The 'WM' package code denotes a ceramic windowed CQFP-100 suitable for field re-programmability. When designing with the EPM5130WM883B-1, plan power sequencing to avoid latch-up: VCC must ramp monotonically to 5V ±10% before any input or I/O is driven. Inputs are TTL-compatible, but unused inputs should be tied to VCC or GND through a resistor to avoid floating-rail noise. The ceramic windowed package must be shielded from ambient light after programming; opaque labels are recommended. This page synthesises distributor pricing, MIL-STD-883B qualification notes, and pin-compatible drop-in guidance not aggregated on a single manufacturer page.

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EPM5130WM883B-2 - 128-Macrocell MAX 5000 UV PLD | Altera | Military
EPM5130WM883B-2

EPM5130WM883B-2 - 128-Macrocell MAX 5000 UV PLD | Altera | Military

The Altera (now Intel) EPM5130WM883B-2 is a 128-macrocell high-speed, high-density UV-erasable programmable logic device (UV PLD) from the MAX 5000 family, packaged in a military-grade (883B) form factor. It is built on a CMOS process and delivers a worst-case propagation delay of 45 ns (tPD, -2 speed grade), making it suitable for glue-logic and state-machine replacement in legacy industrial and military systems. The device is organized into 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), with 19 dedicated inputs and 48 user I/O lines for a total of 68 inputs and 48 outputs. A programmable logic device (PLD) is a digital IC whose logic function is defined by the customer after manufacture, typically via non-volatile or UV-erasable fuses/antifuses, sitting in the broader hierarchy of programmable logic -> logic IC -> integrated circuit. MAX 5000 devices are organized as an AND/OR macrocell array optimized for combinational and registered logic, with the -883B suffix indicating MIL-STD-883 Class B processing for extended environmental and reliability qualification. The -2 speed grade designates a 45 ns tPD, the fastest bin of the EPM5130 family (the non-883B EPM5130WM883B runs at 55 ns). Key features include 128 macrocells, 8 LABs, 48 I/O pins, 1 dedicated clock input, and shared inputs/clocks routed through the PIA. The UV-erasable window allows field re-programmability, useful for design iteration on legacy boards. Per the Altera datasheet family document, the EPM5130 is supported by the MAX+PLUS II development environment. Typical applications include military/aerospace digital control, legacy industrial PLC glue logic, address decoding, bus interfacing, and state-machine consolidation in avionics and ground-vehicle platforms. The 883B processing makes the device especially suited for environments requiring controlled components. When designing with this part, verify package pinout against the Altera MAX 5000 datasheet - legacy PLDs often share the same JTAG-style programming interface and require a 12V VPP programming pulse during UV-erase/reset cycles. Pin-compatible MAX 5000 variants (EPM5130WC-1, EPM5130QC-1, EPM5130LC) share logic architecture but differ in package and speed. This page synthesizes distributor pricing, military-grade cross-references, and drop-in MAX 5000 alternatives not consolidated in the original Altera datasheet.

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EPM5192-1LC - MAX 5000 CPLD 192-Macrocell 62.5MHz | Altera
EPM5192-1LC

EPM5192-1LC - MAX 5000 CPLD 192-Macrocell 62.5MHz | Altera

The Altera EPM5192-1LC is a 192-macrocell member of the classic MAX 5000 high-speed, high-density programmable logic device family, supplied in a ceramic-windowless ceramic (LC) J-leaded chip-carrier package. It integrates 3,750 usable gates, 192 macrocells and 64 user I/O pins, with a worst-case pin-to-pin propagation delay in the -1 speed grade suited to combinatorial and registered glue-logic tasks at up to 62.5 MHz internal operation. The MAX 5000 architecture combines an EPROM-based AND plane feeding a fixed OR/macrocell array, giving non-volatile, in-system-reprogrammable logic that retains its configuration without battery backup. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that integrates multiple PAL/GAL-style macrocell blocks on a single die. Within the broader taxonomy, CPLDs sit alongside simple PLDs as the "instant-on, deterministic-timing" branch of programmable logic, distinct from SRAM-loaded FPGAs that require a configuration device. MAX 5000 specifically targets high logic-to-pin density in 5 V systems, historically used as bus decoders, address mapping, peripheral glue, and state-machine controllers. Designers choose this family for deterministic propagation delays, zero boot time, and excellent pin-locked retrofits into legacy 5 V backplanes. Key features of the EPM5192-1LC include 192 macrocells across four logic-array blocks (LABs), a programmable interconnect array (PIA), 64 bi-directional I/O pins with individually programmable direction and pull-up resistors, JTAG-compliant IEEE 1149.1 boundary-scan support, and an erasable EPROM process technology that is one-time programmable after window erasure. Power consumption is approximately 0.6 mA standby (outputs disabled) and a few hundred mA dynamic depending on toggle rate and frequency, all on a single 5 V supply. Typical applications for the EPM5192-1LC include 5 V bus arbitration and address decoding in VME/PCI industrial backplanes, peripheral glue logic in legacy telecom and instrumentation chassis, ISA-bus address mapping, custom state machines for motor control, and pin-locked drop-in replacements for vintage 22V10/26V12-style designs requiring higher macrocell count. The 64-pin ceramic J-lead package preserves thermal margin for industrial-grade environments. Designers migrating from 5 V to 3.3 V logic should consider the newer MAX 7000AE or MAX II families; EPM5192-1LC is intended strictly for 5 V legacy systems and is recommended for long-life industrial, military and aerospace retrofits where parts longevity matters more than state-of-the-art density.

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EPM51929C - Altera MAX 5000 High-Density EPLD | Intel
EPM51929C

EPM51929C - Altera MAX 5000 High-Density EPLD | Intel

The Intel (formerly Altera) EPM51929C is a member of the MAX 5000 family of high-speed, high-density Erasable Programmable Logic Devices (EPLDs) designed for integration of multiple programmable logic functions on a single CMOS device. The MAX 5000 family introduced a multi-array matrix architecture, combining fast 20-pin PAL-style logic blocks with a programmable interconnect network, enabling designers to replace dozens of discrete SSI/MSI logic parts with one device. The part is classified as FPGA/CPLD-class programmable logic and is documented in Altera's MAX 5000 datasheet family. A programmable logic device (PLD/EPLD) is a semiconductor integrated circuit that can be configured by the end-user to implement custom digital logic functions. PLDs occupy the intermediate tier between fixed-function ASICs and discrete logic gates: they offer integration density (replacing many 74LS/74HC parts), short development cycles, and in-system reprogrammability for legacy designs. EPLDs use UV-erasable EPROM cells for non-volatile configuration, retaining their logic when power is removed. Within the broader taxonomy: PLD -> EPLD -> CMOS EPLD -> MAX 5000 family -> Altera programmable logic. The EPM51929C specifically targets glue-logic and bus-interface applications requiring high pin count and moderate logic density. Key characteristics include high-density logic integration, multiple macrocell and expander-product-term structures typical of the MAX 5000 family, and CMOS technology for low static power consumption. The MAX 5000 family was widely deployed in late-1980s and 1990s bus-interface, address-decoding, and state-machine designs. Programmability is achieved via EPROM cells, requiring UV erasure for re-programming. The part is sourced today primarily through the obsolete/legacy distribution channel, making it a target for aftermarket and franchised stocking distributors. Typical applications for the EPM51929C include address decoding and chip-select generation in 80x86 microprocessor systems, DMA and interrupt controller glue logic, peripheral bus arbitration in VME/Multibus designs, state-machine controllers in industrial automation, and legacy system refresh where the original MAX 5000 design must be maintained without PCB redesign. The part's high pin count allows integration of multiple wide decoding functions in one package. When designing with the MAX 5000 family, note that parts are programmed using industry-standard PLD programmers that support the JEDEC fuse-map format. UV erasure takes approximately 20-30 minutes under a 12,000 uW/cm^2 UV lamp at 253.7 nm. Static power consumption is low but I/O drive characteristics must be checked against the specific bus interface (TTL/CMOS) used in the target design.

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EPM5192AGC - MAX 5000 EPLD, 192 Macro, 84-Pin PGA | Altera
EPM5192AGC

EPM5192AGC - MAX 5000 EPLD, 192 Macro, 84-Pin PGA | Altera

The Altera EPM5192AGC is a high-speed, high-density CMOS EPLD from the legacy MAX 5000 family, providing 192 macrocells and programmable logic capacity in an 84-pin ceramic PGA package. Marketed as part of the MAX 5000 series "High-Speed, High-Density" line, the device delivers the classic Altera second-generation architecture with pin-compatible speed grades and pin counts spanning the entire EPM5192 family. The "AG" suffix denotes the ceramic PGA package family, while the trailing "C" indicates the commercial speed grade. A UV-erasable / OTP Complex PLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines AND/OR arrays with a fixed OR array and is configured by storing charge on floating-gate transistors. The MAX 5000 family sits within the broader taxonomy of programmable logic: PLD -> EPLD/CPLD -> CMOS EPLD -> MAX series, occupying the same architectural lineage as the classic PAL/GAL devices but with higher usable density and deterministic timing. The MAX 5000 family uses a sum-of-products architecture combined with a flexible macrocell, and is electrically erasable (UV window for UV parts, OTP for windowless parts). Key features include 192 macrocells, 100% factory-tested operation across commercial and industrial temperature ranges, programmable security bit for design protection, and a programmable interconnect fabric supporting high-speed logic. The device is fabricated in CMOS technology, delivering low static power consumption compared to bipolar predecessors such as the classic 22V10 PAL family. Multiple speed grades are offered within the EPM5192 base part number. Typical applications include legacy glue logic replacement, bus interface bridging, address decoding, state-machine implementation, and pin-compatible upgrades for older PAL/PLD designs in industrial control, telecommunications infrastructure, and military/aerospace systems. The EPM5192 family is frequently used in long-lifecycle systems where design stability, established silicon, and toolchain maturity are prioritized over cutting-edge density. When designing with this device, confirm the exact speed grade, package variant (PGA window vs. windowless), and operating-temperature range required by the end system, because the family supports multiple variants such as EPM5192AGC-15 and EPM5192AGC-20 that share the same package and macrocell count but differ in propagation-delay specifications. Designers should also confirm programming hardware and software support (e.g., legacy MAX+PLUS II or Altera/Intel-compatible toolchains), as the device is part of a mature, legacy product family.

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EPM5192AGC-15 - 192-Macrocell MAX 5000 EPLD | Altera | 15ns
EPM5192AGC-15

EPM5192AGC-15 - 192-Macrocell MAX 5000 EPLD | Altera | 15ns

The Altera EPM5192AGC-15 is a high-density, UV-erasable erasable programmable logic device (EPLD) from the classic MAX 5000 family, delivering 192 macrocells, 72 inputs, and a 15 ns pin-to-pin propagation delay in a ceramic PGA package. It belongs to the MAX 5000 series of high-speed, high-density CMOS EPLDs that brought register-rich programmable logic to bus-interface, glue-logic, and state-machine designs in the 1990s and early 2000s. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that uses EPROM/EEPROM storage cells to retain configuration, positioned hierarchically between a PAL/GAL (simple PLD) and a true FPGA. Within the broader taxonomy of programmable logic, EPLDs sit above simple PLDs but below FPGAs in logic density, while offering predictable timing and instant-on behavior at power-up. The MAX 5000 family is the legacy Altera product line that preceded the MAX 7000/MAX II families; devices are programmed via a JTAG-style or dedicated programming interface and are commonly supplied in windowed ceramic packages for prototype/development use. Key specifications include 192 macrocells organized in logic array blocks, 64 I/O pins plus 7 dedicated input pins for a total of 72 inputs, a 15 ns worst-case pin-to-pin propagation delay (-15 speed grade), and CMOS technology operating from a 5 V supply. The device supports in-system programmability through the Altera programming hardware, and the ceramic PGA package is windowed for UV erasure during development. Compared with its slower siblings (EPM5192AGC-20 at 20 ns and EPM5192AGC-25 at 25 ns), the -15 speed grade is the fastest variant in the family and is targeted at high-speed bus-interface applications. Typical applications include 32-bit microprocessor bus decoding, state-machine controllers, address decoding for memory subsystems, and replacement of multiple discrete TTL/CMOS glue-logic packages. The high input count (72 inputs) makes the EPM5192 well suited to monitoring multiple control signals in parallel, while the predictable 15 ns delay allows replacement of multiple 74LS/74F-series decoders with a single device. When designing with this part, ensure that the 5 V VCC supply is well decoupled and that the ceramic PGA socket accommodates the device's pin pattern. Note that the EPM5192 family is mature/legacy; new designs typically migrate to MAX 7000AE or MAX II devices, and long-term availability is constrained. This page synthesizes distributor pricing, drop-in alternative guidance, and practical design notes that complement the Altera datasheet and help engineers source or replace this legacy EPLD in maintenance and modernization projects.

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EPM5192AGC-20 - MAX 5000 EPLD, 192 Macrocells | Altera (Intel)
EPM5192AGC-20

EPM5192AGC-20 - MAX 5000 EPLD, 192 Macrocells | Altera (Intel)

The Intel (formerly Altera) EPM5192AGC-20 is a high-density, high-speed CMOS Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, providing 192 macrocells and 12,000 usable gates in a ceramic-windowed PGA (Pin Grid Array) ceramic package. It operates at a 20 ns pin-to-pin propagation delay, making it suitable for glue-logic, bus-interface, and high-speed state-machine replacement of multiple discrete TTL/CMOS devices. A MAX 5000-series EPLD is a member of the electrically-erasable programmable logic device (EEPLD) family. In the broader component taxonomy, an EPLD sits under programmable logic devices (PLDs) -> programmable logic -> digital logic ICs. MAX 5000 devices use a programmable AND/OR macrocell architecture with non-volatile EEPROM configuration memory, so designs retain their pattern after power-down without an external boot PROM - unlike SRAM-based FPGAs which require a configuration flash. Each macrocell contains a programmable AND plane feeding a fixed OR term, an output register, and a feedback path, allowing both combinatorial and registered logic to be implemented. Key features of the EPM5192 include 192 macrocells, 12,000 usable gates, a 20 ns tPD (pin-to-pin delay), fCNT up to 100 MHz counter frequency, and 96 dedicated I/O pins organized into 8 LABs (Logic Array Blocks). Per the Altera MAX 5000 datasheet, the device supports 5 V in-system programmability via the IEEE 1149.1 JTAG interface, allowing reconfiguration without removal from the board. An enhanced security bit prevents pattern read-back, protecting proprietary designs. Typical applications include high-speed glue logic between microprocessors and peripherals, bus arbitration and address decoding, state-machine replacement for legacy 74LS/74F TTL, and industrial control sequencers. The 20 ns tPD makes it appropriate for systems clocked up to ~33 MHz without pipeline insertion. When designing with the EPM5192AGC-20, verify that the target application does not exceed 5.5 V VCC. Use a ceramic-socketed PGA footprint to take advantage of windowed UV erasure during prototyping. The ceramic 'G' package is rated for commercial 0C to 70C operation; for industrial temperatures use the equivalent -1 or -2 speed grade in a plastic package.

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EPM5192AGC84-15 - 192-Macrocell UV PLD, 15ns | Altera MAX 5000
EPM5192AGC84-15

EPM5192AGC84-15 - 192-Macrocell UV PLD, 15ns | Altera MAX 5000

The Altera EPM5192AGC84-15 is a 192-macrocell UV-Erasable/OTP Complex Programmable Logic Device (PLD) from the MAX 5000 family, housed in an 84-pin Ceramic PGA (Pin Grid Array) package. This CMOS device provides 192 logic macrocells organized into 12 Logic Array Blocks (LABs), 64 user I/O pins, and 7 dedicated inputs, supporting combinational and registered logic with a propagation delay of 15 ns (commercial grade) and a maximum internal clock frequency of 83.3 MHz. It operates from a single 4.5 V to 5.5 V supply, with the -15 speed grade denoting a 15 ns pin-to-pin delay. What is a UV-erasable/OTP PLD? A UV-Erasable Complex PLD (Programmable Logic Device) is a non-volatile, one-time-programmable logic IC whose AND/OR array fuse links can be cleared by exposing the die to ultraviolet light through a quartz window, then re-programmed in a dedicated device programmer. The OTP suffix indicates one-time programmable packaging without an erasure window, while the UV variant retains the quartz lid. The MAX 5000 sits in the historical taxonomy: PLD -> CPLD (Complex PLD) -> MAX family -> UV-erasable high-density logic, predating modern SRAM-based FPGAs. Key features include 192 macrocells with configurable D/T/JK flip-flops, 64 bidirectional I/O lines with TTL/CMOS-compatible thresholds, an internal global clock network with synchronous/asynchronous operation, and a 5 V CMOS process that delivers 15 ns propagation delay with low power consumption. The 84-pin ceramic PGA package offers robust thermal performance for industrial and military temperature grades. Architecturally, the MAX 5000 family uses a sum-of-products PLA structure with distributed AND/OR arrays feeding each macrocell, allowing up to 32 product terms per macrocell. The 12 interconnected LABs provide high integration density for glue logic, address decoding, bus arbitration, and state-machine consolidation in 5 V systems. Typical applications include 5 V bus-interface glue logic, address decoding and interrupt priority encoding in 8086/Motorola 68000 systems, state-machine and sequencer consolidation in industrial controllers, and high-reliability avionics and military systems requiring UV-reprogrammable logic. The -15 speed grade (15 ns tPD) suits most glue-logic tasks where 25 ns devices would be too slow. When designing with this part, note that the 84-pin ceramic PGA package requires a through-hole socket and is significantly larger than modern QFP/BGA CPLDs; verify PCB layout and programmer compatibility before specifying. The CMOS process requires careful ESD handling during programming and in-system integration.

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EPM5192AGC84-20 - 192-Macrocell MAX 5000 UV PLD | Altera | 84-CPGA
EPM5192AGC84-20

EPM5192AGC84-20 - 192-Macrocell MAX 5000 UV PLD | Altera | 84-CPGA

The Altera EPM5192AGC84-20 is a CMOS UV-Erasable/OTP Complex Programmable Logic Device (PLD) from the Altera MAX 5000 family, packaged in an 84-pin Ceramic Pin Grid Array (CPGA, package code WPGA) and qualified for commercial temperature grading. It integrates 192 macrocells, 64 user I/O lines, and 7 dedicated inputs, and is rated for a maximum clock frequency of 66.7 MHz with a 20 ns pin-to-pin logic delay. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on semiconductor that combines multiple PAL-like macrocell blocks with a programmable interconnect matrix on a single die. CPLDs sit between discrete TTL/CMOS glue logic and larger FPGAs in the programmable-logic hierarchy: PLD -> CPLD -> FPGA -> programmable logic. They are valued for deterministic timing, zero-configuration latency, and high pin-to-pin drive strength, which makes them ideal for address decoding, bus interfacing, and state-machine replacement in legacy industrial designs. Key features of the EPM5192AGC84-20 include 192 macrocells (delivering up to ~7,500 usable gates), 64 bi-directional I/O pins organized into 4 I/O banks, 7 dedicated global input pins (GCLK, OE1, OE2, OE3, OE4, CLR, PRE), in-system UV-erase window (ceramic package), and 5-Volt CMOS I/O compatible with TTL levels. The "-20" speed grade corresponds to tPD = 20 ns and fMAX = 66.7 MHz. The device is built on Altera's classic MAX (Multiple Array matriX) architecture, which arranges macrocells into Logic Array Blocks (LABs) connected by a continuous programmable interconnect. The ceramic CPGA package is hermetic and UV-transparent, allowing erasure under a UV lamp; an OTP window is included for production programming. The design supports both combinatorial and registered logic with per-macrocell D/T/JK flip-flop configuration. Typical applications include legacy bus-interface glue logic in industrial controllers, address decoding for microprocessor and DSP systems, peripheral replacement (decoders, multiplexers, state machines), and prototype-to-production migration where deterministic timing and instant-on behavior are required. Its 84-pin CPGA is also well suited to through-hole industrial backplanes and military-style card cages where ceramic packaging is preferred. When designing with this part, verify that the CPGA land pattern matches your socket or PCB footprint; ceramic CPGA sockets are specialty items and may have long lead times. For new designs, modern Altera/Intel MAX II or MAX V devices in PLCC/QFP packages are recommended, but the EPM5192AGC84-20 remains the canonical drop-in for legacy systems requiring UV erase. This page synthesizes distributor pricing, real-time stock, ceramic-package handling guidance, and parametric drop-in alternatives that are not collected in the manufacturer datasheet.

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EPM5192AJC-15 - MAX 5000 EPLD, 192 Macrocells, PLCC-84 | Intel
EPM5192AJC-15

EPM5192AJC-15 - MAX 5000 EPLD, 192 Macrocells, PLCC-84 | Intel

The Intel (formerly Altera) EPM5192AJC-15 is a high-density, high-speed Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, delivering 192 macrocells, 100% connectivity, and a 15 ns pin-to-pin logic delay in a 84-pin PLCC (J-lead) package. The part operates from a 5 V supply and supports in-system programmability via Altera's MAX+PLUS II development environment, making it a drop-in upgrade for legacy MAX 5000 designs. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic component that combines AND/OR arrays with output macrocells, bridging the architectural gap between simple PLDs and complex CPLDs. The MAX 5000 family sits in the broader taxonomy of programmable logic: programmable logic -> CPLD/EPLD -> MAX family -> MAX 5000 series, and historically served glue-logic, bus-interface, and state-machine roles before being superseded by modern MAX II, MAX V, and MAX 10 devices that use LUT-based architectures and flash or SRAM configuration. Key features include 192 macrocells, 100% connectivity, 15 ns combinational propagation delay (tPD), a 5 V VCC tolerance on I/O, and an ultraviolet-erasable windowed package (the "W" variant is windowed; the J-lead ceramic PLCC "JC" is non-windowed production package). The architecture provides up to 4 product terms per macrocell with a configurable XOR gate for polarity control, allowing efficient implementation of wide AND-OR-INVERT logic functions. Densities in the family range from 32 to 192 macrocells, and the EPM5192 sits at the top of the MAX 5000 density range. The MAX 5000 architecture uses a sum-of-products PLA structure with a global interconnect that guarantees 100% routability of all logic - a hallmark Altera design differentiator versus PAL-style fusemap devices. This deterministic routing eliminates place-and-route iterations common in modern FPGA flows and allows the MAX+PLUS II fitter to deliver consistent timing closure across revisions. The trade-off is lower logic density and higher per-macrocell cost versus LUT-based FPGAs, but for legacy 5 V designs the MAX 5000 family remains a proven, long-lived platform. Typical applications include legacy 5 V bus-interface glue logic, address decoding and chip-select generation, state-machine and sequencer logic, peripheral controllers in industrial and telecom backplanes, and replacement of multiple discrete PAL/GAL devices. The 84-pin PLCC package and 5 V operation also make the EPM5192AJC-15 compatible with older through-hole and socketed designs where board rework is impractical. When designing with this device, ensure the MAX+PLUS II toolchain (or modern compatible programmer) is available and verify availability of a 5 V source. Note that Intel/Altera MAX 5000 devices have been in maintenance status for many years; verify long-term supply before new designs. The "-15" speed grade corresponds to a 15 ns tPD; the "-20" and "-25" grades are slower and may be substituted in non-timing-critical sockets. This page synthesizes distributor stock data, same-family pin-compatible alternatives, and practical migration guidance not found in the original datasheet.

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EPM5192AJC-25 - MAX 5000 192-Macrocell EPLD, 25ns | Altera
EPM5192AJC-25

EPM5192AJC-25 - MAX 5000 192-Macrocell EPLD, 25ns | Altera

The Intel / Altera EPM5192AJC-25 is a 192-macrocell, high-density, high-speed Erasable Programmable Logic Device (EPLD) from the legacy MAX 5000 family, housed in a 68-pin PLCC (AJC) windowed ceramic package with 25 ns pin-to-pin propagation delay. The MAX 5000 family was Altera's second-generation EPLD architecture, offering non-volatile UV-erasable programmability, predictable timing, and 5 V tolerant CMOS I/O targeted at glue-logic, bus-interface, and state-machine integration in through-hole industrial designs. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines AND/OR array architecture with macrocell-based output logic, falling within the broader hierarchy of programmable logic devices (PLD) -> EPLD/CPLD -> complex programmable logic. EPLDs sit between simple PAL/GAL devices and modern SRAM-based FPGAs in terms of density and are characterized by deterministic propagation delay that does not depend on routing path length - a critical property for asynchronous bus interfaces and decoder logic. Key features include 192 macrocells organized into multiple Logic Array Blocks (LABs), 100% factory-tested operation, 5 V CMOS I/O with TTL-compatible inputs, programmable output macrocells with configurable flip-flops, and a maximum propagation delay of 25 ns (tPD). The ceramic windowed PLCC package supports UV erasure for prototype and development cycles, while the AJC suffix denotes the PLCC-68 ceramic windowed form factor with industrial-grade operating temperature range. The MAX 5000 architecture uses a classic EPROM-based AND/OR plane feeding output macrocells with selectable registered/combinational modes. Unlike SRAM-based FPGAs, the device requires no external boot PROM, powers up in a defined state, and retains configuration indefinitely. The 25 ns speed grade positions this part for legacy 25-33 MHz bus interfaces rather than modern high-speed designs. Typical applications include legacy PC/AT bus decode logic, peripheral controllers (DMA, interrupt, bus arbitration), industrial state machines, military/aerospace systems (the J-grade marking indicates MIL-STD-883 processing), and prototyping platforms for newer MAX 7000/MAX II designs. Engineers working on long-lifecycle defense and aerospace equipment frequently retain MAX 5000 designs due to form-fit-function stability. When designing with this EPLD, ensure the propagation delay budget accounts for both tPD and tCO (clock-to-output) timing - consult the datasheet for the exact derating curves at junction temperatures above 70°C. UV erasure requires a windowed ceramic package; production plastic-package equivalents (EPM5192AQI, EPM5192AQC) offer one-time programmable (OTP) replacements with identical footprint but no window. This page synthesizes distributor pricing, drop-in same-family alternatives, and design considerations not consolidated in the original Altera datasheet.

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EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15

EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera

The Altera EPM5192AJC84-15 is a UV-erasable/OTP Complex Programmable Logic Device (CPLD) from the MAX 5000 family, featuring 192 macrocells in an 84-pin PLCC (J84C) windowed ceramic package. It operates from a single 5V supply with a propagation delay of 15 ns and a maximum clock frequency of 83.3 MHz, making it suitable for high-speed glue-logic and state-machine integration. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple SPLDs/GALs and large FPGAs in the programmable logic hierarchy (SPLD -> CPLD -> FPGA -> programmable logic). It typically contains multiple PAL-like logic blocks interconnected by a central programmable switch matrix, with non-volatile storage that retains configuration without external memory. The MAX 5000 family was Altera's second-generation high-density EPLD line (the second 'M' family), succeeding the classic MAX 7000 and MAX 3000 lines that became industry workhorses for bus-interface and address-decoding glue logic. Key features include 192 macrocells (each containing a programmable AND/OR array with a flip-flop), 5V CMOS technology, UV-erasable windowed package for re-programmability, and pin-to-pin compatibility across the MAX 5000 series. The 15 ns propagation delay supports synchronous designs up to the rated 83.3 MHz fMAX, and the device supports both combinatorial and registered logic through its macrocell register option. Architecturally, the EPM5192 uses a classic sum-of-products PLA structure with a global interconnect matrix that delivers consistent, deterministic timing across all 192 macrocells. The CMOS EPROM-based configuration cell stores the logic pattern, and the ceramic windowed package (designated 'JC' with quartz window for UV erasure) is intended primarily for prototype development; production units typically migrate to the plastic 'PC' one-time-programmable package. Typical applications include bus address decoding, state-machine controllers, glue logic between microprocessors and peripherals, and legacy industrial-control designs. The wide 5V tolerance also makes it useful as a level shifter between TTL and CMOS logic families on legacy backplanes. When designing with the EPM5192, ensure the 5V VCC rail is well-decoupled with 0.1 uF ceramic capacitors near each supply pin, and verify that all inputs respect the 5.5V absolute maximum rating. For new designs, consider that the MAX 5000 family is mature/EOL — confirm long-term availability before committing to volume production. This page synthesizes distributor stock data, parametric drop-in alternatives, and practical MAX 5000 design notes not collected in any single manufacturer datasheet.

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EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20

EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera

The Altera EPM5192AJC84-20 is a 192-macrocell UV-erasable/OTP Complex Programmable Logic Device (CPLD) from the MAX 5000 family, housed in an 84-pin Plastic Leaded Chip Carrier (PLCC J-Lead, WQCCJ) package with a 33 ns propagation delay and a 66.7 MHz maximum clock frequency. It operates from a single 4.75 V to 5.25 V supply, offers 7 dedicated inputs and 64 user I/O lines, and is fabricated on a CMOS UV-erasable switch-matrix process that allows in-system erasure and re-programming using an ultraviolet lamp. What is a UV-erasable CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on digital IC that implements glue logic, bus arbitration, state machines, and address decoding in a single chip. The UV-erasable (windowed) variant adds a quartz window above the die that lets an external UV lamp reset the on-chip EEPROM-like switches, so the same physical package can be re-programmed many times during prototyping. Within the broader taxonomy, a CPLD belongs to programmable logic devices (PLD), which themselves sit under digital logic ICs and semiconductor devices. Key features include 192 macrocells arranged in Logic Array Blocks (LABs), a programmable interconnect switch matrix, 64 bidirectional I/O pins, 7 dedicated clock/input pins, and a 33 ns pin-to-pin delay (the “-20” speed grade). The device is built on a CMOS EEPROM technology that delivers deterministic propagation delay regardless of logic utilization, which is critical for synchronous designs. Architecturally, the EPM5192 integrates the AND/OR array with output macrocells that contain programmable flip-flops, making it well suited for both combinatorial and registered designs. The UV window enables up to thousands of erase/reprogram cycles during development, although the part is one-time-programmable once the window label is removed for production. Typical applications include glue logic for legacy 5 V microprocessor and DSP systems, bus-interface and address-decoding logic, peripheral controllers in industrial control, and replacement of multiple 74-series TTL/CMOS gates in compact boards. Designers of long-life industrial and military systems also rely on this part for its deterministic timing and field-proven reliability. Designers should plan a 10–15 percent I/O and macrocell margin, use Altera MAX+PLUS II or Quartus for design entry, and budget for the UV-erase cycle (~30 minutes under a 12,000 uW/cm² lamp) if iterative prototyping is required. The 84-pin J-lead PLCC accepts standard socket or surface-mount footprints, easing both production and rework.

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