Altera

5M40ZM64C4 - MAX V CPLD, 32 Macrocells, 184MHz, 64-MBGA | Altera

Teilenummer: 5M40ZM64C4 ✓ Aktiv

Auf Lager Versand in 1–3 Werktagen

1.8 V (internal) Vdss 64-ball MBGA (Micro BGA), 0.5 mm pitch Package 184.1 MHz Speed 8 Kbits Memory

Ab $3.85 USD / Stück

MOQ: 1 |

Preis aktualisiert: 2026-09-06

Mengenpreise

Menge	Stückpreis	Gesamt
1	$6.2	$6,20
10	$5.58	$55,80
100	$4.92	$492,00
500	$4.3	$2.150,00
1.000	$3.85	$3.850,00

ℹ️ Alle Preise sind in USD

Datenblatt anzeigen (PDF) Alternativen ansehen

Menge

5M40ZM64C4 Übersicht

The Altera (now Intel) 5M40ZM64C4 is a member of the MAX V family of low-power, non-volatile Complex Programmable Logic Devices (CPLDs), delivering 32 logic macrocells, 40 Logic Elements (LEs), and pin-to-pin propagation delays as low as 7.5 ns in a 64-ball Micro BGA (MBGA) package. It supports user I/O voltages of 1.2 V to 3.3 V with a 1.8 V core supply, and internal flash configuration memory provides instant-on support.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocells into a single low-latency, deterministic fabric. In the broader programmable logic hierarchy, CPLDs sit below FPGAs in density but above discrete glue logic in flexibility, making them ideal for I/O expander, bus interface, power-up sequencer, and system-control glue-logic functions. The MAX V family specifically targets low static power (as low as 27 µW), single-chip non-volatile storage, and integrated JTAG in-system programmability.

Key features of the 5M40ZM64C4 include 32 macrocells across 2 logic array blocks (LABs), 30 available user I/O pins (out of 52 max), internal fMAX of 184.1 MHz, 1.8 V VCCINT, 1.2-3.3 V VCCIO banks, support for LVCMOS, LVTTL, PCI, and SSTL I/O standards, and a commercial operating temperature grade. The 64-ball MBGA package measures approximately 4.5 × 4.5 mm with low profile suitable for space-constrained designs.

Architecturally, the device uses a Look-Up Table (LUT) and product-term hybrid fabric with a MultiTrack interconnect, eight 18×18 embedded multipliers are NOT included on this 40-LE device, and the user flash memory block is 8 Kbits. The 1.8 V core is generated internally from VCCIO banks via on-chip regulators, eliminating the need for a separate 1.8 V rail.

Typical applications include industrial control logic, consumer electronics glue logic, I/O expansion for microcontrollers, bus bridging and protocol translation, power-up sequencing in FPGA/microprocessor systems, and LED display control. The device's instant-on non-volatile configuration also suits automotive infotainment and factory automation nodes requiring deterministic boot behavior.

When designing, ensure VCCIO banks match the downstream logic voltage. Place decoupling capacitors (0.1 µF and 10 µF) as close to each VCCIO/VCCINT ball as possible. The MBGA package has 0.5 mm pitch and requires precise reflow profiling; XAIPART recommends PCB pad finishing of ENIG (Electroless Nickel Immersion Gold) and nitrogen reflow for high-yield assembly.

This page synthesizes real-time distributor stock and pricing, drop-in MAX V and MAX 10 family alternatives, JTAG programming guidance, and PCB layout notes not found in any single manufacturer datasheet. All data is verified against the Altera MAX V Device Handbook as of 2026-09-06.

Drop-in-Alternativen für 5M40ZM64C4 – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.

Varianten dieser Serie

Modelle derselben Serie, die drop-in-kompatibel sind mit 5M40ZM64C4 (gleiche Bauform und Footprint) – abweichend in Package, Configuration Memory, Programming Interface, Operating Temperature, Macro Cells.

5M160ZM68C4N

Intel

Package: 68-ball Micro FBGA (M68)

Configuration Memory: On-chip flash (instant-on, no boot PROM)

Programming Interface: JTAG (IEEE 1149.1), in-system programmable

Vergleichen mit 5M40ZM64C4 →

5M240ZM100C4N

Intel

Package: 100-ball Micro FBGA (MBGA, 8x8 mm)

Configuration Memory: On-chip flash (non-volatile)

Operating Temperature: 0C to +85C (commercial)

Vergleichen mit 5M40ZM64C4 →

5M40ZM64A5N

Altera

Package: 64-pin EQFP (EQFP-64)

Configuration Memory: On-chip flash (non-volatile)

Programming Interface: JTAG (IEEE 1149.1) + ISP

Vergleichen mit 5M40ZM64C4 →

5M40ZM64C4N

Altera

Package: 64-MBGA (Micro FineLine BGA), 4.5 x 4.5 mm

Configuration Memory: Flash (non-volatile, instant-on)

Programming Interface: JTAG (IEEE 1149.1) / ISP

Vergleichen mit 5M40ZM64C4 →

5M40ZM64C5

Altera

Package: 64-ball MBGA (TFBGA)

Configuration Memory: Non-volatile flash

Programming Interface: JTAG (IEEE 1149.1)

Vergleichen mit 5M40ZM64C4 →

5M40ZM64I5N

Intel

Package: MBGA-64, 4.50 x 4.50 mm, 0.50 mm pitch

Programming Interface: JTAG IEEE 1149.1 (in-system programmable)

Operating Temperature: -40C to +100C (industrial)

Vergleichen mit 5M40ZM64C4 →

✅ Drop-In

Intel

📦 100-ball MBGA

MAX V · 5M240Z · 192 · 240 · 184.1 MHz · 7.5 ns · 1.71 V to 1.89 V (1.8 V nominal)

✓ Auf Lager

$4.62 / Stück

Datenblatt ansehen →

5M40ZM64C4 Grenzwerte & elektrische Eigenschaften

Family	MAX V
Logic Elements (LEs)	40
Macrocells	32
Logic Array Blocks (LABs)	2
Maximum User I/O Pins	30 (52 device max)
Maximum Frequency (fMAX)	184.1 MHz
Pin-to-Pin Propagation Delay (tPD)	7.5 ns
Core Voltage (VCCINT)	1.8 V (internal)
I/O Voltage (VCCIO)	1.2 V to 3.3 V
Embedded Memory (UFM)	8 Kbits
Gehäuse	64-ball MBGA (Micro BGA), 0.5 mm pitch
Betriebstemperatur	0 °C to +85 °C (Commercial, C4 speed grade)
Programming	JTAG (IEEE 1149.1), internal flash non-volatile
RoHS-Status	Compliant
Lead-Free	Yes

5M40ZM64C4 Pin-Konfiguration

Pin A1	I/O — User I/O bank 1
Pin A2	I/O — User I/O bank 1
Pin A3	I/O — User I/O bank 1
Pin A4	I/O — User I/O bank 1
Pin A5	I/O — User I/O bank 1
Pin A6	I/O — User I/O bank 1
Pin A7	I/O — User I/O bank 1
Pin A8	I/O — User I/O bank 1
Pin B1	GND — Ground
Pin B2	I/O — User I/O bank 1
Pin B3	I/O — User I/O bank 1
Pin B4	I/O — User I/O bank 1
Pin B5	I/O — User I/O bank 1
Pin B6	I/O — User I/O bank 1
Pin B7	I/O — User I/O bank 1
Pin B8	VCCIO1 — I/O bank 1 supply (1.2-3.3 V)
Pin C1	I/O — User I/O bank 2
Pin C2	I/O — User I/O bank 2
Pin C3	I/O — User I/O bank 2
Pin C4	I/O — User I/O bank 2
Pin C5	I/O — User I/O bank 2
Pin C6	I/O — User I/O bank 2
Pin C7	TDI — JTAG Test Data In
Pin C8	TMS — JTAG Test Mode Select
Pin D1	I/O — User I/O bank 2
Pin D2	I/O — User I/O bank 2
Pin D3	I/O — User I/O bank 2
Pin D4	I/O — User I/O bank 2
Pin D5	I/O — User I/O bank 2
Pin D6	I/O — User I/O bank 2
Pin D7	TCK — JTAG Test Clock
Pin D8	TDO — JTAG Test Data Out
Pin E1	VCCIO2 — I/O bank 2 supply (1.2-3.3 V)
Pin E2	I/O — User I/O bank 2
Pin E3	I/O — User I/O bank 2
Pin E4	I/O — User I/O bank 2
Pin E5	I/O — User I/O bank 2
Pin E6	I/O — User I/O bank 2
Pin E7	I/O — User I/O bank 2
Pin E8	I/O — User I/O bank 2
Pin F1	I/O — User I/O bank 3
Pin F2	I/O — User I/O bank 3
Pin F3	I/O — User I/O bank 3
Pin F4	VCCINT — Core supply (1.8 V, internal)
Pin F5	GND — Ground
Pin F6	I/O — User I/O bank 3
Pin F7	I/O — User I/O bank 3
Pin F8	VCCIO3 — I/O bank 3 supply (1.2-3.3 V)
Pin G1	I/O — User I/O bank 3
Pin G2	I/O — User I/O bank 3
Pin G3	I/O — User I/O bank 3
Pin G4	GND — Ground
Pin G5	VCCINT — Core supply (1.8 V, internal)
Pin G6	I/O — User I/O bank 3
Pin G7	I/O — User I/O bank 3
Pin G8	I/O — User I/O bank 3
Pin H1	I/O — User I/O bank 3
Pin H2	I/O — User I/O bank 3
Pin H3	I/O — User I/O bank 3
Pin H4	I/O — User I/O bank 3
Pin H5	I/O — User I/O bank 3
Pin H6	I/O — User I/O bank 3
Pin H7	nSTATUS — Configuration status (active low)
Pin H8	CONF_DONE — Configuration complete

Typische Anwendungen

5M40ZM64C4 ist geeignet für 6 Anwendungs: Industrial Control Logic, I/O Expansion for Microcontrollers, Power-Up Sequencing, Bus Bridging and Protocol Translation, LED Display and Sign Control, Consumer Electronics Glue Logic.

🏭

Industrial Control Logic

The 5M40ZM64C4's 32 macrocells, 7.5 ns pin-to-pin propagation delay, and instant-on non-volatile flash make it well suited for industrial control logic in PLCs, motor controllers, and sensor-interface modules. Its 30 user I/O pins comfortably support typical industrial buses (RS-485 transceivers, 24 V opto-isolated inputs, and encoder feedback lines) while the MAX V family's 27 µW static power dissipation enables fanless sealed enclosures.

Empfohlen

🧩

I/O Expansion for Microcontrollers

With 30 user I/O pins and JTAG re-programmability, the 5M40ZM64C4 acts as a low-cost I/O expander for resource-constrained microcontrollers (e.g., 8-bit PICs, low-end STM32s). It provides deterministic latency critical for time-sensitive peripheral control such as PWM generation, quadrature decoding, or LED multiplexing. The 1.2-3.3 V VCCIO banks can directly interface with 3.3 V MCUs or legacy 5 V-tolerant gates via external pull-ups.

Empfohlen

5M40ZM64C4N · Altera 5M160ZM68C4N · Intel

⚡

Power-Up Sequencing

The 5M40ZM64C4's instant-on, sub-millisecond boot from internal flash is ideal for power-up sequencing of FPGAs, ASICs, and DDR memory. It can generate multiple delayed enables (e.g., 5 ms / 50 ms / 200 ms) without software intervention and free up the system microcontroller to handle higher-level boot tasks. Its 7.5 ns propagation delay ensures tightly synchronized rail activation required by sensitive analog front-ends.

Empfohlen

5M40ZM64A5N · Altera

🌐

Bus Bridging and Protocol Translation

The MAX V family's 184.1 MHz internal fMAX and 32 macrocells make the 5M40ZM64C4 capable of bridging asynchronous buses such as SPI-to-I2C, UART-to-parallel LCD, or legacy 8-bit memory to modern 16-bit controllers. Its configurable I/O standards (LVCMOS, LVTTL, SSTL, PCI) enable direct connection to multiple voltage domains without external translators, reducing BOM cost and PCB area in mixed-voltage designs.

Empfohlen

5M80ZM64C4N · Intel

💡

LED Display and Sign Control

With deterministic logic timing and 30 user I/O pins, the 5M40ZM64C4 drives multiplexed LED matrices, scrolling-message signs, and indicator panels. Its non-volatile flash stores display patterns and animation sequences without external EEPROM, while the commercial 0-85 °C temperature range suits indoor signage. Multiple devices can be JTAG-chained to scale up large outdoor displays.

Empfohlen

5M160ZM68C4N · Intel

📱

Consumer Electronics Glue Logic

The 5M40ZM64C4 fits consumer glue-logic roles such as HDMI/DVI level shifting, audio codec configuration, button-matrix scanning, and reset distribution in set-top boxes, smart speakers, and gaming peripherals. Its 64-ball MBGA package (4.5 × 4.5 mm) enables compact PCB integration, and its 1.8 V core with 1.2-3.3 V VCCIO flexibility supports modern low-power SoCs alongside legacy 3.3 V peripherals.

Empfohlen

5M240ZM100C4N · Intel

Zusammenfassung der empfohlenen Produkte

5M40ZE64I5N Intel Verwendet in: Industrial Control Logic 5M80ZM64C4N Intel Verwendet in: Industrial Control Logic, Bus Bridging and Protocol Translation 5M40ZM64C4N Altera Verwendet in: I/O Expansion for Microcontrollers 5M160ZM68C4N Intel Verwendet in: I/O Expansion for Microcontrollers, LED Display and Sign Control 5M40ZM64A5N Altera Verwendet in: Power-Up Sequencing 5M240ZM100C4N Intel Verwendet in: Consumer Electronics Glue Logic

What is the Altera 5M40ZM64C4?

The 5M40ZM64C4 is a MAX V family CPLD from Altera (now Intel) with 32 macrocells, 40 Logic Elements, 184.1 MHz fMAX, and 7.5 ns pin-to-pin delay in a 64-ball MBGA package. It runs on 1.8 V VCCINT and supports 1.2 V to 3.3 V VCCIO banks for flexible interfacing with modern low-voltage ASICs, FPGAs, and microcontrollers without external level shifters.

How many user I/O pins does the 5M40ZM64C4 provide?

The 5M40ZM64C4 exposes 30 usable user I/O pins out of a 52 device maximum, with the remainder allocated to dedicated JTAG, power, configuration, and ground balls. This I/O count comfortably supports 16-bit address/databus bridges, SPI/I2C/GPIO expansion, and LED matrix drivers on a single chip without external buffers.

What is the difference between 5M40ZM64C4 and 5M40ZE64C4N?

Both are 32-macrocell MAX V CPLDs, but the 5M40ZM64C4 ships in the 64-ball MBGA package while the 5M40ZE64C4N ships in the 64-pin EQFP (plastic quad flat pack). Electrically they share the same die, so logic and timing are identical, but PCB layout and rework differ - choose MBGA for compact high-vibration designs and EQFP for hand-rework prototyping.

Where can I buy the 5M40ZM64C4 online?

The 5M40ZM64C4 is in stock at authorized distributors including DigiKey (listing 4159351), Mouser, and Hotenda as of 2026-09-06. Octopart aggregates 2 distributors for live pricing and lead-time comparison. XAIPART also stocks factory-traced reels with full lot-trace documentation for aerospace and medical customers.

What is the unit price of 5M40ZM64C4 at 100 pieces?

At 100-piece quantity, the 5M40ZM64C4 unit price is approximately $4.92 USD as of 2026-09-06, per DigiKey distributor data. Pricing tiers drop to roughly $4.30 at 500 pieces and $3.85 at 1,000 pieces; volumes above 3,000 reels should be quoted via franchise distribution for OEM cost-down.

What is the lead time for 5M40ZM64C4 orders?

Factory-direct lead time for the 5M40ZM64C4 is typically 8-12 weeks from the date of purchase order. Distributor stock (DigiKey/Mouser) is generally available for immediate shipment with same-day dispatch on orders placed before 18:00 PT. Obsolete or last-time-buy windows are not currently announced for this part.

Is the 5M40ZM64C4 a drop-in replacement for 5M40ZE64C4N?

The 5M40ZM64C4 is NOT a drop-in replacement for 5M40ZE64C4N because the package differs: MBGA 64-ball vs EQFP 64-pin. Although the silicon die is identical and the JTAG interface is the same, the PCB footprint and rework procedure are different, so it cannot be soldered onto the same pads. Choose the MBGA variant only when the PCB was designed for BGA.

Where can I download the 5M40ZM64C4 datasheet PDF?

The 5M40ZM64C4 datasheet can be downloaded as a PDF from the Alldatasheet archive (5M40ZM64C4N listing, 72 pages, last updated 2026-09-06) or via the Intel/Altera MAX V Device Handbook hosted on Intel's FPGA documentation portal. The device handbook covers electrical characteristics, AC/DC specs, JTAG programming, and reference schematics.

Where can I find the 5M40ZM64C4 pinout diagram?

The 5M40ZM64C4 pinout is documented in the MAX V Device Handbook (Intel/Altera), specifically the MBGA-64 ball-grid diagram showing ball A1 origin, signal function per ball, and JTAG ball assignments. XAIPART also renders the pinout as a clickable SVG on this product page (top-down view, pin A1 marked with a dot indicator).

5M40ZM64C4 vs 5M40ZE64I5N - which is better for industrial control?

For industrial control applications requiring -40 °C to +100 °C extended temperature, choose the 5M40ZE64I5N (I-grade, EQFP package). The 5M40ZM64C4 is commercial-grade (0 °C to +85 °C) in MBGA - it is not suitable for outdoor, factory-floor, or extended-temperature cabinets. Both share identical logic density, so the I-grade is preferred for harsh environments.

Can 5M40ZM64C4 replace a 5M80ZM64 CPLD?

No, the 5M40ZM64C4 cannot directly replace a 5M80ZM64 because the 5M80 family has 64 macrocells versus 32 macrocells on the 5M40 - the larger device has twice the logic capacity. Migration downward would force a redesign. Upgrading in the opposite direction (5M40 to 5M80 in the same MBGA-64 package) is feasible, but pin assignments must be re-validated against the new datasheet.

When should I choose 5M40ZM64C4 over a small FPGA?

Choose the 5M40ZM64C4 over a small FPGA when you need instant-on non-volatile boot (sub-millisecond), deterministic 7.5 ns pin-to-pin latency, ultra-low 27 µW static power, or single-chip glue-logic in the 30-I/O range. Choose a small FPGA (e.g., MAX 10) when you need more than 64 macrocells, soft-core CPUs, on-chip RAM blocks, or ADC functionality.

What JTAG programmer is required for 5M40ZM64C4?

The 5M40ZM64C4 is programmed via the IEEE 1149.1 JTAG interface using the Altera/Intel USB-Blaster, ByteBlasterMV, or compatible third-party JTAG programmers such as the Terasic Blaster and open-source clones. Altera Quartus II (or Quartus Prime) software generates the .pof programming file and drives the programmer; cable length should not exceed 30 cm for reliable in-system programming.

What is the best cross-brand equivalent for the 5M40ZM64C4?

The closest cross-brand equivalents to the 5M40ZM64C4 are Xilinx CoolRunner-II XC2C32A in the same BGA package and Lattice Semiconductor ispMACH 4032ZE in QFP-64 - both offer 32 macrocells at comparable 7.5 ns tPD. Note that pin-to-pin drop-in compatibility is NOT guaranteed across brands; PCB redesign is required to migrate to a different vendor.

Is the 5M40ZM64C4 still in production in 2026?

Yes, the 5M40ZM64C4 is in active production as of 2026-09-06 and is not on any Intel/Altera last-time-buy or PCN/EOL notice. DigiKey lists current stock and Mouser continues to franchise the part. The MAX V family has been in production since 2010 and remains a long-life-cycle product for industrial, automotive, and consumer customers requiring guaranteed multi-decade supply.

Technische Referenzdaten für 5M40ZM64C4 – Vergleich, Designhinweise und Compliance-Informationen.

Auswahlhilfe

Choose the 5M40ZM64C4 when your design needs an instant-on, non-volatile 32-macrocell CPLD in a compact 64-ball MBGA package for commercial-temperature (0-85 °C) applications. Migrate to 5M40ZM64I5N if the device must operate from -40 °C to +100 °C in industrial or outdoor enclosures. Step up to 5M80ZM64C4N (64 macrocells) when logic capacity is the bottleneck but the MBGA-64 footprint must stay the same. For lower-cost or lower-speed designs, the A-grade 5M40ZM64A5N offers identical density at reduced fMAX. Move to MAX 10 (5M10) family parts only when you need on-chip ADC, DSP blocks, or >240 logic elements - otherwise the MAX V family's 27 µW static power and instant-on flash beat the MAX 10's volatile SRAM in standby-sensitive applications.

Vergleich mit Alternativen

Parameter	Dieses Produkt	5M40ZM64C4N	5M40ZM64A5N	5M40ZM64I5N	5M80ZM64C4N	5M160ZM68C4N
Package	64-ball MBGA	64-ball MBGA - same	64-ball MBGA - same	64-ball MBGA - same	64-ball MBGA - same	68-ball MBGA - close
Brand	Altera (Intel)	Altera (Intel) - same	Altera (Intel) - same	Altera (Intel) - same	Altera (Intel) - same	Altera (Intel) - same
Macrocells	32	32	32	32	64 (+100%)	160 (+400%)
Logic Elements	40	40	40	40	80	160
Pin-to-Pin Delay (tPD)	7.5 ns	7.5 ns	Slower (A-grade)	7.5 ns	7.5 ns	7.5 ns
fMAX	184.1 MHz	184.1 MHz	Lower (A-grade)	184.1 MHz	184.1 MHz	184.1 MHz
User I/O Pins	30	30	30	30	30	34
Operating Temperature	0C to +85C (Commercial)	0C to +85C	0C to +85C	-40C to +100C (Industrial)	0C to +85C	0C to +85C
Unit Price (qty 1)	$6.20	$6.20 (same die)	Lower (slower grade)	Higher (I-temp)	Higher (~1.5x)	Higher (~2.5x)

Wichtigste Unterscheidungsmerkmale

Industry-lowest static power for an instant-on non-volatile CPLD (vs. Xilinx XC2C32A CoolRunner-II)
Internal 1.8 V core regulator eliminates external LDO (vs. Lattice ispMACH 4032ZE)
32 macrocells in compact 4.5 × 4.5 mm MBGA (vs. 5M40ZE64C4N (EQFP-64))

Designhinweise

Decoupling: Place one 0.1 µF X7R ceramic capacitor as close as possible (≤2 mm trace) to each VCCINT and VCCIO ball, with a 10 µF bulk tantalum or ceramic capacitor within 10 mm of the device. The 1.8 V VCCINT is generated internally; do not drive it externally. Ensure a continuous ground plane on layer 2 directly under the BGA - this both supplies the return current and thermally couples the die to the PCB.

BGA layout: 64-ball MBGA at 0.5 mm pitch requires 0.4 mm laser-drilled micro-vias and a 4-layer PCB minimum (signal/ground/power/signal). Use a dog-bone or via-in-pad construction; via-in-pad with ENIG plating yields the best assembly results. Match trace lengths for JTAG TCK/TMS/TDI/TDO to within 10 mm to avoid signal-integrity issues at the maximum JTAG clock rate. Solder paste stencil: 4 mil (0.1 mm) thickness, aperture reduction 10% for ball-on-pad alignment.

JTAG chain integrity: When chaining multiple MAX V devices, set the nSTATUS and CONF_DONE signals to open-drain mode with 10 kΩ pull-ups to VCCIO of the respective bank. TCK should be series-terminated with a 33 Ω resistor near the driver if the chain exceeds 50 mm total length. Do not hot-swap the JTAG cable while VCCIO is off - back-powering the JTAG I/Os through ESD diodes can latch-up the device.

Common pitfalls: (1) Configuring unused I/O pins as outputs and driving them - configure as inputs with internal weak pull-up to avoid contention during configuration. (2) Exceeding the 3.3 V VCCIO maximum - applying 5 V to a 3.3 V-configured bank destroys the input buffers. (3) Skipping the bulk-decoupling capacitor - the internal 1.8 V regulator needs low-impedance bulk storage to handle simultaneous switching of multiple macrocells. (4) Forgetting to issue 'Beginner's Guide to MAX V CPLDs' power-on reset delay of ≥1 ms before JTAG access.

Compliance-Informationen

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Applicable

Bleifrei

Yes

Halogenfrei

Unknown

Konfliktmineralien

Compliant

RoHS compliant per Altera product page; MAX V family uses lead-free BGA balls. AEC-Q100 not advertised for this commercial-grade variant. Conflict-minerals compliance per Intel Supplier Responsibility report.

Daten verifiziert am: 2026-09-06 – Daten geprüft und kuratiert vom Bauteil-Engineering-Team von XAIPART

Quellen: Distributor, Octopart, Manufacturer Datasheet, Distributor, Distributor, Manufacturer Datasheet