PIC16LF15376T-I/ML
PIC16LF15376T-I/ML - 32MHz 8-bit XLP MCU 28KB Flash | Microchip
The Microchip Technology PIC16LF15376T-I/ML is an 8-bit PIC16F-family microcontroller with eXtreme Low-Power (XLP) technology, integrating 28KB (16K x 14 words) of Flash program memory, 2KB of SRAM and 256 bytes of EEPROM, in a 44-pin QFN (8x8 mm) package with exposed pad. It runs up to 32 MHz from a 1.8V-3.6V supply and delivers 16 MIPS peak throughput, with rich Core Independent Peripherals (CIPs) including a 10-bit ADC with Computation, a 5-bit/8-bit DAC, four Configurable Logic Cells (CLC), Complementary Waveform Generator (CWG), four 10-bit PWMs, two EUSARTs and SPI/I2C peripherals.
A microcontroller (MCU) is a single-chip computer that integrates a CPU core, non-volatile program memory, working RAM, and a rich peripheral set around the silicon. The PIC16 family uses a modified Harvard RISC architecture with a 14-bit instruction word, and 'LF' denotes the low-voltage variant that supports sub-2V operation - critical for battery-powered designs. The PIC16F153xx sits between entry-level PIC16F and the higher-pin PIC16F188xx families in the broader 8-bit microcontroller taxonomy: microcontroller -> embedded controller -> 8-bit MCU -> RISC MCU -> PIC16F.
Key features of this part include XLP sleep currents as low as 50 nA typical (DSS - Deep Sleep, with retention), 1.8V minimum Vdd for full-speed operation, IDLE/DOZE power-saving modes, hardware CRC/Scan with NVM lock, and a peripheral pin-select (PPS) system that lets remap most digital I/O to alternate pins. The 44-QFN (8x8) footprint gives 36 general-purpose I/O pins and exposes one full analog/digital feature set on every pin through PPS and the Analog Connection Matrix.
On the architecture side, the PIC16LF15376 uses a 2-stage pipeline RISC core with a hardware multiplier, an 8-level deep hardware stack, and a 16-entry file-select register (FSR) window for linear SRAM access. The ADC with Computation (ADC2) offloads averaging, accumulation, threshold compare, and oversampling from the CPU, dramatically lowering wake/sleep overhead - which is why this family is popular for sensor hubs and battery monitoring. The CWG block can synthesize dead-band control, complementing PWMs to drive half-bridges cleanly.
Typical applications include low-power IoT sensor nodes, BLE-beacon or LoRa-end-node controller companions, home appliances with capacitive-touch user interfaces, battery chargers with multi-cell balancing, smoke/CO detectors, and portable medical devices such as glucose meters and pulse oximeters. Designers also reach for this MCU in industrial control blocks (small PLCs, valve drivers) where deterministic 8-bit I/O and eXtreme Low Power are simultaneously required.
When designing, choose Vdd between 1.8V and 3.6V; if you need 5V tolerance, an external level shifter is required. Decouple Vdd with a 100nF ceramic close to each Vdd/Vss pair, and tie the exposed pad (EP) to a solid ground plane for thermal and electrical reasons. Always configure the PPS registers before enabling peripherals and verify the ADC acquisition time against source impedance.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that are not bundled in the manufacturer datasheet.
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