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EPC2L120N - 5V/3.3V Altera Config Device, 84-Pin PLCC | Intel
EPC2L120N

EPC2L120N - 5V/3.3V Altera Config Device, 84-Pin PLCC | Intel

The Intel (Altera) EPC2L120N is a 3.3V/5V in-system programmable configuration device designed to configure SRAM-based LUT FPGAs such as the Altera Cyclone, APEX, FLEX, Mercury, ACEX, and Stratix families, supplied in a 84-pin PLCC package. It features 400,000 gates of configuration memory, 165,888 bits of configuration flash, and supports 2.7V-3.6V VCCIO logic, with a configuration clock rate of up to 66 MHz. The Configuration Device (config device or EPCS-class successor) is a non-volatile serial memory device used in conjunction with volatile SRAM-based FPGAs to store their configuration bitstream. At power-up the FPGAs' SRAM configuration cells are blank and must be loaded from an external source; the config device provides this non-volatile storage. Within the broader programmable logic ecosystem, the EPC2L120N sits inside the FPGA & CPLD category and the Intel/Altera configuration-device product hierarchy, which historically evolved from the EPC1/EPC1441 to the EPC2 family and was eventually superseded by the EPCS / EPCQ serial flash devices. Key features include 2.7V to 3.6V operating voltage, in-system programmability through the IEEE Std 1149.1 JTAG interface, daisy-chain support for multi-device configuration, and 8 MHz internal oscillator with programmable clock division. The device supports both FPP (Fast Passive Parallel) at up to 66 MHz data rate and PS (Passive Serial) configuration schemes via Altera's proprietary configuration bus, and includes open-drain CONF_DONE / nSTATUS / nCONFIG pins for handshaking with the target FPGA. Architecturally, the EPC2L120N integrates a flash memory array, an internal 8 MHz RC oscillator, JTAG TAP controller for ISP, and a configuration controller that arbitrates between JTAG programming and FPGA configuration modes. The flash cell is rated for 100,000 erase/program cycles and supports byte-level page programming with a typical sector-erase time of 2 seconds. Typical applications include configuring Altera Cyclone II FPGA development boards, APEX 20K / FLEX 10K reference designs, factory-floor control boards, and industrial video / image-processing platforms. Designers select the EPC2L120N when their design targets older Altera SRAM FPGAs and requires multi-voltage (5V tolerant) configuration with high-bit-count storage. When designing with this part, note that the JTAG pins TMS, TDI, TDO and TCK must be pulled-up to VCCIO through 10 kohm resistors; the nINIT_CONF pin must remain high during normal operation. For new designs targeting Cyclone IV or later, the EPCS / EPCQ serial flash family is recommended over the legacy EPC2 device.

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EPC2L1696-10F Altera Configuration Device for SRAM FPGAs | 1696-LUT
EPC2L1696-10F

EPC2L1696-10F Altera Configuration Device for SRAM FPGAs | 1696-LUT

The Altera EPC2L1696-10F is a serial configuration EPROM designed to load configuration bitstreams into SRAM-based LUT devices (look-up table FPGAs). It supports logic densities up to 1,696 LUTs and uses a 5-pin serial interface (nCS, DCLK, DATA, OE, nINIT_CONF) that is directly compatible with Altera FLEX and APEX FPGA configuration schemes. Housed in a 20-pin PLCC package, it is rated for industrial-grade operation with the -10 speed grade indicating a 10 ns access time. A configuration device (also called a configuration PROM) is a non-volatile memory IC dedicated to storing and delivering FPGA configuration bitstreams at power-up. The hierarchy is: configuration PROM -> non-volatile memory -> memory IC -> semiconductor. In a typical boot sequence, the FPGA held in reset loads its configuration from the PROM over a synchronous serial link; once all bits have shifted in, the PROM releases OE and the FPGA enters user mode. This category is a predecessor to modern SPI flash + bitstream compression schemes used today, but legacy Altera designs still rely on it. Key features of the EPC2L1696-10F include 1,696 LUT-equivalent configuration density, 3.3 V single-supply operation, in-system programmability (ISP) through the JTAG-compatible 4-wire serial interface, and a programmable 'nINIT_CONF' pin that can re-trigger a configuration cycle without removing power. The 20-pin PLCC package is socket-friendly and easy to prototype, while supporting reflow profiles suitable for surface-mount production. Technically, the EPC2L1696-10F uses an internal CMOS EEPROM array with built-in address generation, so the host FPGA does not need to drive an explicit address bus - it simply clocks bits out on the rising edge of DCLK. This reduces FPGA pin-count pressure during configuration and keeps the boot BOM small. Program erase and rewrite cycles typically exceed 100,000 per the device family specification. Typical applications include Altera FLEX 10K / APEX 20K boot configuration, industrial PLC controllers, factory automation legacy systems, military and aerospace retrofits, and replacement / repair of legacy Altera reference designs. The -10 speed grade supports DCLK frequencies up to 100 MHz in cascade mode, which is sufficient for most FLEX-class devices. When designing with this part, note that the EPC2 family is a legacy Altera product line now supported through the Altera-to-Intel FPGA transition; verify current lifecycle status with authorized distributors before committing to a new design. For new designs, consider migrating to EPCQ or compatible SPI flash with the MAX II / MAX V CPLD configuration controller. This page synthesizes distributor pricing tiers, drop-in compatible variants from the same Altera EPC2 family, and practical design notes not consolidated in the original Altera datasheet.

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EPC2L20 - 1.6Mb In-System Prog Config PROM | Altera | PLCC-20
EPC2L20

EPC2L20 - 1.6Mb In-System Prog Config PROM | Altera | PLCC-20

The Altera EPC2L20 is a 1.6-Mbit in-system programmable configuration PROM designed to configure SRAM-based LUT devices such as Altera FPGAs in the APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, and Stratix families. The device is housed in a 20-pin J-lead PLCC package and operates from a 3.3 V core supply with 5.0 V or 3.3 V I/O tolerance. What is a configuration PROM? A configuration PROM is a non-volatile memory device that stores the bitstream for an SRAM-based FPGA. Because SRAM loses its configuration when power is removed, every SRAM-FPGA design requires a boot memory that delivers the bitstream on power-up via a serial or parallel configuration interface. The EPC2L20 belongs to the hierarchy: configuration PROM -> programmable logic support memory -> non-volatile memory -> semiconductor memory IC. Altera's EPC2 family replaced the older EPC1 family with higher density, in-system programmability via IEEE 1532, and lower power consumption. Key features include 1.6 Mbit of configuration storage organized as 8-bit bytes, in-system programmability through the JTAG (IEEE 1149.1 / IEEE 1532) interface, a cascadable multi-device daisy-chain architecture for higher density systems, and a low-power CMOS process. The device supports both 5.0 V and 3.3 V operation modes selectable via the VCCSEL pin, and integrates JTAG boundary-scan test capability for board-level manufacturability. The EPC2L20 uses a serial configuration interface that reduces FPGA pin-count overhead, and the cascadable architecture lets multiple EPC2 devices share a single configuration bus on the FPGA, allowing designers to scale up configuration density without changing the FPGA configuration controller. The 3.3 V core with 5 V tolerant I/O simplifies mixed-voltage board designs where older 5 V logic coexists with newer 3.3 V devices. Typical applications include Altera APEX II and APEX 20K configuration, Stratix and Cyclone FPGA boot memory, multi-FPGA configuration chains for DSP and prototyping boards, and industrial controllers using SRAM-based LUT devices. Engineers select the EPC2L20 when their FPGA configuration bitstream fits within 1.6 Mbit and they require the simplicity of a single-chip configuration solution. Designers should verify that their compiled FPGA bitstream does not exceed 1.6 Mbit before selecting this device, and ensure that the JTAG chain is correctly terminated for in-system reprogramming. For higher densities, EPC4 or EPC8/EPC16 in the same family provide more storage in larger packages. This page synthesizes distributor pricing across Nantian, Veswin, Jotrin and FPGAkey alongside pin-to-pin compatible alternatives in the Altera EPC2 family not found in the standalone datasheet.

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EPC2L20N - 1.6Mb Altera FPGA Config PROM | PLCC-20
EPC2L20N

EPC2L20N - 1.6Mb Altera FPGA Config PROM | PLCC-20

The Intel (formerly Altera) EPC2L20N is a 1.6-Mbit in-system-programmable configuration PROM designed to load the configuration bitstream into SRAM-based LUT FPGAs such as the APEX, ACEX, Cyclone, FLEX 10K, and Mercury device families. The part is offered in a 20-pin J-lead PLCC (PLCC-20) package that supports either 3.3 V (3.0 V to 3.6 V) or 5.0 V (4.5 V to 5.5 V) operation, allowing it to drive FPGA configuration pins directly without external level shifting. What is a configuration PROM? A configuration PROM is a non-volatile serial memory that stores the FPGA's configuration bitstream and serially shifts it into the FPGA during power-up or reconfiguration. It sits between the system flash and the FPGA in the boot hierarchy: microprocessor -> flash -> configuration PROM -> SRAM-based FPGA. By isolating the bitstream from system flash, the PROM lets engineers update FPGA firmware in-system without recompiling the host firmware. The EPC2L20N uses an in-system-programmable (ISP) interface so the bitstream can be reloaded through JTAG-style four-wire programming without removing the device from the board. Cascading of multiple PROMs is supported via the chip-enable control to handle configuration images larger than 1.6 Mb, which historically let designers support Cyclone II and APEX 20K designs. Internal oscillator and clock-management circuitry generate the serial configuration clock for the target FPGA. The PLCC-20 (J-lead) package is through-hole-compatible and socket-compatible, allowing easy field replacement and prototype iteration. Operating temperature spans the commercial 0C to +70C range as the standard grade, with industrial-grade variants available for harsher environments. Typical applications include Altera FPGA configuration bitstream storage for industrial control boards, telecom line cards, prototyping platforms, and embedded compute modules where the SRAM-based LUT FPGA must be reconfigured at power-up. When designing with this device, observe Altera's configuration interface timing requirements and verify the cascaded PROM chain supports the total bitstream length for the chosen FPGA family. For new designs, designers should evaluate newer serial configuration devices, as the EPC2 family has been in mature production for many years. This page synthesizes Altera/Intel configuration-device specifications, distributor availability and pricing, drop-in alternatives, and engineering notes not consolidated in any single manufacturer document.

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EPC2L20U - 1.6Mb Configuration PROM 20-PLCC | Altera
EPC2L20U

EPC2L20U - 1.6Mb Configuration PROM 20-PLCC | Altera

The Altera EPC2L20U is a 1.6-Mbit in-system programmable configuration PROM designed to configure SRAM-based LUT devices such as APEX II, APEX 20K, Mercury, Stratix, Cyclone, and ACEX 1K FPGAs, housed in a 20-pin Plastic Leaded Chip Carrier (PLCC) package. A configuration PROM is a non-volatile serial memory device that stores the FPGA bitstream and loads it into the FPGA's SRAM configuration cells at power-up or after a reconfiguration command. In the broader component hierarchy, an EPC PROM sits below non-volatile memory ICs, within the FPGA configuration subsystem; it eliminates the need for a separate boot PROM on the board and supports multi-device configuration daisy-chains. Key features include 1.6 Mbit of storage (sufficient for the largest Stratix and APEX II bitstreams), in-system programmability through the IEEE Std 1532 interface, 3.3V single-supply operation, and JTAG-based boundary-scan test. The low-power 'L' suffix denotes the 3.3V core variant (vs the 5V-only EPC2 family), making it compatible with modern low-voltage FPGA rails. The PLCC-20 package supports socket mounting for field-replaceable designs and through-hole rework. The EPC2L20U uses a serial configuration interface (nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA0) and supports cascade mode where multiple PROMs can be combined for very large bitstreams. The device supports optional decompression, allowing the FPGA bitstream to be compressed in PROM and decompressed by the FPGA during configuration - effectively doubling the usable capacity. Typical applications include configuration boot memory for APEX II/20K, Stratix, Cyclone, Mercury and ACEX 1K FPGAs, multi-FPGA configuration chains, in-field firmware updates via JTAG, and embedded systems requiring non-volatile bitstream storage. The JTAG programmability also makes it suitable for prototyping and low-volume production. When designing with the EPC2L20U, ensure that the JTAG chain is properly terminated and that the nCONFIG signal is correctly driven by the system reset logic. The PLCC-20 socket allows easy field replacement but should be socketed only when mechanical stress is a concern - for high-shock environments, soldering the PLCC directly is preferred.

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EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C

EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel

The Intel (formerly Altera) EPC2L20U-HAF480119C is a 1.6 Mb in-system-programmable configuration PROM designed to load configuration bitstreams into SRAM-based LUT FPGAs such as the Cyclone, Stratix, and APEX families. Built on a 3.3 V core with 5 V tolerant I/O, the device supports serial (1-bit) and parallel (8-bit) configuration data paths and packages the configuration memory in a compact 20-pin PLCC (HAF480119C designation refers to the factory-programmed configuration image suffix and package code). A configuration PROM is a non-volatile memory device whose sole purpose is to store and stream the FPGA's bitstream to the FPGA at power-up. The EPC2 family sits inside the broader hierarchy of FPGA configuration devices: configuration PROM -> non-volatile memory -> semiconductor memory -> integrated circuit. Unlike boot PROMs for microcontrollers, EPC2 devices support in-system reprogrammability via JTAG, IEEE 1149.1 boundary-scan, or dedicated serial/parallel data pins, enabling field updates of the FPGA bitstream without removing the board. Key features include 1.6 Mb of storage capacity, support for FPGAs up to the Cyclone IV and Stratix IV device densities, cascadable JTAG chains for multi-FPGA systems, and an open-drain nSTATUS / CONF_DONE handshake for synchronous configuration completion detection. The EPC2 supports compression-mode bitstreams, allowing the PROM to hold a compressed image that the FPGA decompresses on load, effectively increasing usable capacity by 35-50% depending on the FPGA family. Technically, the EPC2L20 implements Altera's proprietary serial configuration state machine with automatic baud-rate detection between 10 MHz and 40 MHz. Its 20-pin PLCC footprint allows socketed field replacement, which simplifies legacy system maintenance. Compared with newer EPCQ/Avalon-ST configuration devices, the EPC2L20 retains a mature JTAG programming interface that aligns with legacy Quartus II design flows. Typical applications include factory provisioning of Cyclone II/III FPGAs in industrial controllers, Stratix II design prototype boards, broadcast video processing equipment, and legacy aerospace/defense systems that standardized on EPC2 in the 2000-2010 era. The PLCC-20 socketed form factor allows easy inspection and replacement in long-lifecycle programs. When designing with EPC2L20, verify that the target FPGA's configuration scheme matches EPC2L20's supported modes (FPP x8 at 40 MHz, PS, AS, JTAG). For newer Cyclone V / Stratix V devices, migrate to EPCQ256 or active serial flash, as EPC2 supports only legacy configuration controllers. This page synthesizes distributor stock checks, real-time pricing tiers, and pin-compatible alternatives in the same PLCC-20 footprint, providing engineering context not consolidated on the manufacturer datasheet alone.

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EPC2LC02N - 1.6Mb Altera Enhanced Configuration Device PLCC-20
EPC2LC02N

EPC2LC02N - 1.6Mb Altera Enhanced Configuration Device PLCC-20

The Intel (formerly Altera) EPC2LC02N is an enhanced configuration device that provides a single-chip, high-speed configuration solution for very high-density SRAM-based FPGAs, packaged in a 20-pin PLCC housing. The device integrates a configuration controller and 1.6 megabits of flash memory in one IC, eliminating the external boot-PROM complexity that legacy Altera designs required. The EPC2 family supports in-system programmability via JTAG, which simplifies board-level rework and field firmware updates. What is a configuration device? A configuration device (also called a configuration PROM) is a non-volatile memory IC whose sole purpose is to store the bitstream that loads an SRAM-based FPGA on power-up. The hierarchy runs: configuration device -> boot PROM -> FPGA configuration memory -> programmable logic. Because SRAM FPGAs lose their configuration on every power-down, the configuration device is mandatory in standalone systems without an external processor to load the bitstream. The EPC2 enhanced architecture adds several key features beyond the legacy EPC1 family: in-system programmability through the JTAG (IEEE 1149.1) interface, 3.3V single-supply operation (VCC = 3.0 V to 3.6 V), support for multi-device configuration chains, and a dedicated nSTATUS, nCONFIG, and CONF_DONE handshake that simplifies FPGA handshaking. The 1.6 Mb density supports mid-range Altera FPGA bitstreams such as APEX II, APEX 20K, ACEX 1K, FLEX 10K, Mercury, and Stratix-class devices when only partial configuration is required, or smaller FPGAs in full mode. The internal flash array is split into a controller block and a memory block, with the controller handling the serial/parallel configuration sequence, JTAG state machine, and error detection. The flash memory is organized as 8-bit bytes and accessed via a multiplexed address/data interface to the host FPGA during configuration. Typical applications include APEX 20K and ACEX 1K boot configuration, FLEX 10K series standalone boot, multi-FPGA configuration chains on DSP and ASIC prototyping boards, and industrial control modules that need field-reprogrammable FPGA bitstreams. The in-system programmability makes the EPC2LC02N well suited for production lines and field-serviceable designs where JTAG is the only available update interface. When designing with the EPC2LC02N, ensure the JTAG chain includes the EPC2 device plus all downstream FPGAs to enable in-system updates of both the boot PROM contents and the FPGA logic. A 100 nF decoupling capacitor placed within 5 mm of the VCC pin is required to suppress flash write glitches; PLCC packages also benefit from a socketed footprint in prototyping environments where the device may need to be swapped for a higher-density variant (EPC2LC20N at 4 Mb). This page synthesizes distributor pricing, drop-in alternatives from the EPC1/EPC2 family, and practical design notes not consolidated in a single location in the manufacturer datasheet.

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EPC2LC120 - PLCC-120 Altera FPGA Config Device | Intel
EPC2LC120

EPC2LC120 - PLCC-120 Altera FPGA Config Device | Intel

The Altera (now Intel) EPC2LC120 is a 120-pin PLCC Configuration Device designed for programming and configuring SRAM-based look-up table (LUT) FPGAs, including the FLEX, ACEX, APEX, and Mercury families. It provides non-volatile storage of the FPGA configuration bitstream with in-system programmability via JTAG and supports flexible configuration schemes such as serial (PS), parallel (PPA), and multi-device daisy-chaining. The EPC2LC120 is rated for commercial operating temperatures and is supplied in a JEDEC-standard 120-lead plastic leaded chip carrier (PLCC-120) socketed package for field upgrades and manufacturing rework. A configuration device is a non-volatile memory IC that holds the FPGA configuration bitstream and presents it to the target FPGA at power-on via a structured handshake protocol (typically Altera's FPP or PS scheme). It sits in the FPGA boot hierarchy as the third tier: below JTAG-direct programming and below processor-driven configuration, but above the absent-on-board-boot-PROM option. EPC2 devices are specifically tailored to Altera's proprietary configuration state machine, exposing CONF_DONE, nSTATUS, nCONFIG, and DCLK signals that handshake with the FPGA. Unlike generic SPI flash, the EPC2 family integrates compression, error-checking, and remote update logic. Key features of the EPC2LC120 include 2 Mbit (approximately 250 Kbyte) configuration storage density, byte-wide or serial configuration data width selectable per design, 3.3V single-supply operation, JTAG IEEE 1149.1 boundary-scan compliance for in-system programming, and a small footprint PLCC-120 package with socket compatibility for field replacement. The device supports multi-device configuration chains, enabling a single EPC2 to program multiple FPGAs in parallel or serial mode depending on the system architecture. From an architectural standpoint, the EPC2LC120 uses an embedded CMOS non-volatile memory cell array with on-chip charge pumps and a serial/parallel configuration controller. The integrated controller handles Altera's proprietary configuration handshaking and supports optional compression (up to 2:1) of the stored bitstream, effectively doubling usable density. The device also supports remote update via the Altera multi-mode configuration protocol, allowing firmware revisions over JTAG without removing the device from the board. Typical applications include legacy Altera FLEX 10K/ACEX 1K/APEX 20K series FPGA configuration, industrial control boards with field-upgradable logic, military and aerospace systems using older Altera silicon, and prototyping platforms where the configuration memory must be hot-swappable. The PLCC-120 socket makes it well suited to engineering development environments where configuration files change frequently. When designing with the EPC2LC120, ensure the JTAG chain order is correct so that the EPC2 is programmed as a slave device alongside the FPGA. Decoupling caps (0.1uF ceramic placed adjacent to each VCC pin) are recommended to handle the in-system programming write currents. Confirm the FPGA configuration mode (FPP/PS/PPA) matches the EPC2 data-width setting in the Quartus configuration editor.

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EPC2LC20 - 1.6Mb In-System Prog Config PROM 20-PLCC | Altera
EPC2LC20

EPC2LC20 - 1.6Mb In-System Prog Config PROM 20-PLCC | Altera

The Altera EPC2LC20 is a 1.6-Mbit in-system programmable (ISP) configuration PROM designed to load configuration bitstreams into SRAM-based Altera FPGA families at power-up. Housed in a 20-pin J-lead PLCC (9x9 mm) package, the EPC2LC20 supports configuration data widths of x1 in serial mode and connects directly to Altera FPGAs such as ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, and MAX 9000 series. The device is rated for both 5.0-V and 3.3-V ISP through the built-in IEEE 1149.1 (JTAG) Test Access Port (TAP), enabling reconfiguration in-circuit without removing the device from the board. A configuration PROM is a non-volatile memory device that stores the FPGA's configuration bitstream and delivers it serially or in parallel to the target SRAM-based FPGA every time the system powers up or when new configuration data is needed. Because SRAM-based LUT devices are volatile, the EPC2LC20 eliminates the need for a separate boot ROM and reduces BOM cost, PCB area, and design complexity. The EPC2 family sits in the broader hierarchy of FPGA configuration memory: configuration PROM -> non-volatile boot memory -> FPGA companion IC -> programmable logic support silicon. Key features of the EPC2LC20 include 1.6 Mbits of storage capacity, cascadable JTAG-chain support so multiple EPC2 devices can be chained together to configure larger FPGAs, and dedicated open-drain CONF_DONE and nSTATUS pins for handshaking with the target FPGA. The device supports 8-bit or 16-bit JTAG boundary-scan, plus built-in data decompression compatible with Altera Quartus II programming files. Programming is performed via the Altera Programming Unit (APU) or any IEEE 1149.1-compliant JTAG controller. In terms of architecture, the EPC2LC20 is built around a CMOS non-volatile memory array with on-chip charge pumps for ISP operation. It exposes standard JTAG pins (TCK, TMS, TDI, TDO) plus dedicated nCONFIG, nSTATUS, CONF_DONE and DCLK interface pins to the FPGA, so no glue logic is required between the PROM and the FPGA. The JTAG-based ISP allows field upgrades and factory-floor programming using only a 4-wire JTAG cable. Typical applications include boot configuration for Cyclone and Cyclone II FPGA designs, APEX 20K family prototyping cards, multi-FPGA systems that daisy-chain several EPC2 devices in JTAG order, industrial controllers using FLEX 10K/6000 logic, and legacy designs that require a simple non-volatile companion to Altera SRAM-based FPGAs. When selecting between EPC2 variants, choose the EPC2LC20 for low-density designs and cascade additional EPC2s for larger FPGA bitstreams.

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EPC2LC20-T - 1.6Mb FPGA Config PROM PLCC-20 | Altera
EPC2LC20-T

EPC2LC20-T - 1.6Mb FPGA Config PROM PLCC-20 | Altera

The Altera (Intel) EPC2LC20-T is a 1.6 Mb in-system programmable Configuration PROM for SRAM-based FPGAs, housed in a 20-pin PLCC package. It operates at up to 10 MHz serial configuration frequency and supplies non-volatile storage for Altera SRAM-LUT devices such as the ACEX, APEX, Cyclone, FLEX, MAX 7000A/B, MAX II, and Mercury families. The "-T" suffix indicates tape-and-reel packaging for high-volume surface-mount assembly. A Configuration PROM is a serial non-volatile memory that loads bitstream data into an SRAM-based FPGA at every power-up, because SRAM configuration cells are volatile. EPC2-series PROMs sit between the system's flash storage or microcontroller and the FPGA's DATA0/DCLK/nCONFIG/nSTATUS/CONF_DONE pins, presenting the bitstream serially via Altera's FPP or PS configuration schemes. This category sits inside the broader hierarchy: non-volatile memory -> PROM -> configuration memory -> FPGA boot device -> semiconductor. Key features of the EPC2LC20 include 1.6 Mb flash storage, in-system programmability through the JTAG IEEE Std 1149.1-1990 boundary-scan interface, and the ability to cascade multiple devices to support larger bitstreams. The device operates from a single 3.3 V supply and integrates a low-voltage detector that holds the FPGA in reset until VCC is stable, simplifying multi-rail power sequencing. The EPC2 uses a 4-pin serial interface (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) compatible with Altera's PS configuration mode. Internally, a state machine manages configuration timing, CRC checking, and optional data compression. The JTAG port supports ISP (In-System Programming) so designers can update firmware in the field without removing the PROM. Typical applications include industrial control boards, military and aerospace FPGA systems, telecommunications line cards, medical imaging hardware, and test-and-measurement equipment using Altera/Intel FPGAs. The wide JTAG support also makes the EPC2LC20-T well suited for remote firmware updates. Design consideration: Because EPC2-series PROMs are pre-loaded via JTAG or the Altera Programming Unit, plan ISP access through the FPGA's JTAG chain or a dedicated header. When cascading multiple EPC2s, the nCASC pin propagates enable to the next device in the chain. This page consolidates distributor pricing, drop-in pin-compatible alternatives, and engineering design notes that extend beyond the original Altera datasheet.

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EPC2LC20-U - 1.6Mb FPGA Config PROM, 20-PLCC | Altera (Intel)
EPC2LC20-U

EPC2LC20-U - 1.6Mb FPGA Config PROM, 20-PLCC | Altera (Intel)

The Altera EPC2LC20-U is an in-system programmable configuration PROM designed to load configuration bitstreams into Altera/Intel SRAM-based FPGAs at power-up, delivering 1.6 Mb of flash-backed configuration storage in a 20-pin PLCC (9x9) package with 10 MHz serial interface speed. It supports 3.3V operation and includes JTAG-based in-system programmability (ISP) via the IEEE 1149.1 boundary-scan chain, eliminating the need for an external programmer. A configuration PROM is a non-volatile memory device dedicated to storing the FPGA bitstream. On every power-up the FPGA's SRAM configuration cells must be reloaded because SRAM is volatile; the EPC2 family is purpose-built for this task and connects to the FPGA's dedicated serial configuration pins (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE). Compared with generic SPI flash, configuration PROMs reduce board complexity by offering a guaranteed-timing, drop-in storage device for legacy Altera APEX, FLEX, Cyclone, ACEX and Arria GX families. Key features include 1.6 Mb storage (sufficient for mid-density FPGAs), a 10 MHz serial configuration clock, in-system programmability via JTAG, cascadable architecture for larger bitstreams, and a low pin count 20-PLCC footprint that simplifies PCB layout. The device operates from 3.0V to 3.6V across the industrial -40C to +85C range. The EPC2 uses a 4-pin serial interface plus JTAG, with on-chip voltage generation for the program/erase charge pump and a built-in oscillator for internal timing. The cascadable feature allows two or more EPC2 devices to be chained to configure larger FPGAs, with the master/slave handoff handled automatically over the serial interface. Typical applications include legacy Altera APEX 20K / APEX II / ACEX 1K / FLEX 10K configuration, Cyclone and Cyclone II boot memory, Arria GX configuration, industrial control cards that pair a small FPGA with non-volatile storage, and any 3.3V system that needs reliable in-system reprogrammable configuration memory. The JTAG ISP capability also supports field firmware updates without removing the board. When designing with this part, place a 0.1 uF decoupling capacitor within 5 mm of VCC and keep the JTAG chain length under about 150 mm to preserve signal integrity. For bitstreams larger than 1.6 Mb, cascade a second EPC2 device - the FPGA's MSEL pins select the cascade mode and CONF_DONE handling is automatic. This page synthesizes distributor stock, verified drop-in alternatives such as EPC2LI20 and EPC2LC20N, lifecycle status, and design considerations not found in the bare datasheet.

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EPC2LC20-V - 1.6Mb FPGA Config PROM, 20-PLCC | Altera
EPC2LC20-V

EPC2LC20-V - 1.6Mb FPGA Config PROM, 20-PLCC | Altera

The Altera (Intel) EPC2LC20-V is a 1.6-Mbit in-system programmable Configuration PROM designed for configuring SRAM-based look-up table (LUT) FPGAs, housed in a 20-pin Plastic Leaded Chip Carrier (PLCC) package optimized for legacy through-hole and socketed production flows. A configuration PROM is a non-volatile memory device that stores the FPGA bitstream and loads it into the SRAM-based LUT device at power-up, reset, or upon reconfiguration request. Within the broader hierarchy, configuration PROMs sit at the boot-memory layer beneath FPGAs and CPLDs, between power-on reset events and the user logic — EPC1/EPC2 series parts specifically support Altera (now Intel) APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, and MAX 9000 device families, simplifying single-chip configuration and enabling remote in-system reconfiguration via JTAG. Key features include 1.6 Mbit of Flash-based configuration storage, a serial configuration interface clocked up to 10 MHz, in-system programmability through the IEEE 1149.1 (JTAG) boundary-scan port, and a cascadable daisy-chain interface that allows multiple EPC2 devices to be linked for designs exceeding the single-device capacity. The -V suffix indicates the commercial operating temperature range of 0 °C to +70 °C, while the LC family provides the low-cost tier of the EPC2 line. Technically, the EPC2LC20-V uses a 3.3 V core supply (VCC) with 5 V-tolerant I/O on configuration interface pins, four JTAG pins (TMS, TCK, TDI, TDO) supporting boundary-scan and ISP, and dedicated nCS, nSTATUS, CONF_DONE, and DCLK pins for the FPGA configuration handshake. The 20-pin PLCC package (JEDEC MS-018) provides a socket-friendly footprint suitable for prototyping sockets, field upgrades, and legacy replacement scenarios. Typical applications include configuring APEX 20K and ACEX 1K FPGA prototype boards, industrial control systems with field-upgradable logic, telecommunications line cards using FLEX 10K devices, and military/aerospace ground-test fixtures built around MAX 9000 parts. The 1.6 Mbit density is dimensioned for mid-density APEX 20K designs and most ACEX 1K configurations. Designers should budget for the dedicated JTAG header and ensure that the PROM-to-FPGA DCLK/nSTATUS/CONF_DONE handshake traces are kept short. For multi-PROM cascading, ensure that the cascaded chain does not exceed the FPGA's maximum configuration clock frequency or supported PROM count. This page consolidates distributor pricing, drop-in alternatives in the same 20-PLCC footprint, and practical design considerations not directly summarized in the Altera configuration-device datasheet — distinct information gain relative to manufacturer PDF and Octopart listings.

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EPC2LC20CAD - 1.6Mb Config PROM for SRAM FPGAs | Altera
EPC2LC20CAD

EPC2LC20CAD - 1.6Mb Config PROM for SRAM FPGAs | Altera

The Altera EPC2LC20CAD is a 1.6 Mb in-system programmable configuration PROM designed to load configuration data into SRAM-based Altera FPGAs such as the APEX, ACEX, Cyclone, and Stratix device families. It is housed in a 20-pin J-lead PLCC (PLCC-20) package and operates from a single 3.3V supply. The device supports serial (bit-wide) configuration of single FPGAs through a dedicated serial-data interface and can be cascaded for multi-device chains. An FPGA configuration PROM is a non-volatile memory device whose sole purpose is to store the bitstream image that an SRAM-based LUT FPGA needs at every power-up because SRAM cells lose their configuration when power is removed. The EPC2 family sits in the boot-memory hierarchy between the FPGA and the system host: at power-on the FPGA reads its bitstream serially from the PROM, then enters user mode. Modern Altera/Intel parts replaced the EPC2 family with active serial (AS) flash configuration devices, so the EPC2LC20CAD is now widely used as a drop-in legacy replacement and for repair/maintenance of installed systems. Key features include 1.6 Mb storage capacity, in-system programmability through the IEEE Std 1149.1 JTAG interface, 3.3V single-supply operation with 5V tolerant I/O, and a JTAG-based ISP that allows the bitstream to be updated on-board without removing the device. Programming is performed through the standard JTAG pins (TCK, TMS, TDI, TDO) so no dedicated programmer socket is required, simplifying manufacturing flow. The EPC2 architecture is a serial Flash PROM optimized for one-time-or-occasional update use rather than high-endurance writes. Internally it contains an oscillator, address counter, and serial interface state machine that streams the configuration bits to the FPGA. The 20-pin PLCC package provides a through-hole or socketed footprint that was standard for late-1990s and early-2000s Altera reference designs. Typical applications include Altera APEX 20K, ACEX 1K, Cyclone (original), and Stratix FPGA configuration in industrial controllers, telecommunications line cards, and legacy networking equipment. The device is also used in test fixtures and as a repair/maintenance part for legacy Altera boards where the original configuration PROM has failed or needs to be re-programmed. When designing with this device, ensure the JTAG chain is properly terminated and that the PROM's nSTATUS/CONF_DONE handshaking matches the target FPGA's configuration mode. The 3.3V supply must be stable before the FPGA releases its nCONFIG signal, otherwise the FPGA may enter an undefined state and require re-configuration. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the manufacturer datasheet alone, providing engineers with a single reference for sourcing and replacement decisions.

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EPC2LC20EM - 1.6Mb Configurable PLD, 20-Pin PLCC | Intel
EPC2LC20EM

EPC2LC20EM - 1.6Mb Configurable PLD, 20-Pin PLCC | Intel

The Intel EPC2LC20EM is a 1.6-Mbit serial-configuration (EPC2) erasable programmable read-only memory device, packaged in a 20-pin Plastic Leaded Chip Carrier (PLCC) and rated for the industrial temperature range. It is a member of Intel's EPC2 enhanced-configuration family and is intended as a configuration-memory companion for Stratix, Cyclone, APEX, ACEX, FLEX, and MAX series FPGAs as well as Excalibur and HardCopy structured ASICs. The EPC2LC20EM provides 1.6 Mbits of non-volatile storage organized into multiple configuration bitstream images selectable via chip-select lines. Programmable logic devices (PLDs) such as FPGAs normally require an external non-volatile boot-memory that holds the configuration bitstream at power-up. The EPC2 family replaced the older EPC1 generation with higher density, faster programming time, and an in-system programmability (ISP) interface that uses a 4-pin JTAG-compatible bus. By embedding configuration memory in a single 20-pin PLCC, designers eliminate the need for parallel EPROMs and reduce board area. Key features of the EPC2LC20EM include 1.6 Mbit density, a parallel-mode or serial-mode data interface, dedicated nCS, nCLK, and DCLK pins, and an operating voltage of 3.3 V core. The PLCC-20 plastic package supports surface-mount reflow assembly and the industrial temperature range of -40C to +85C, making the part suitable for factory-floor, automotive, and outdoor telecom hardware that drives an Altera/Intel FPGA. Typical applications include FPGA configuration-memory backup for prototyping and production boards, factory-floor industrial controllers based on Cyclone III/IV, communications line cards using Stratix or APEX 20K, and military or aerospace designs where data-retention and in-system reprogrammability over JTAG are required. The serial configuration interface reduces pin count to just DATA, DCLK, nCS, and nCONFIG, leaving FPGA I/O free. When designing with the EPC2LC20EM, ensure that the JTAG chain length does not exceed the IEEE 1149.1 specification limits, allow at least 4 ms after power-up before configuration begins, and verify that the nINIT_CONF pin is correctly handled for multi-device cascading. Because the EPC2 family uses 3.3 V signaling, level translation may be required when driving 5 V-only FPGAs. This page synthesizes distributor stock, parameter reference data, and same-family alternatives not found in the manufacturer datasheet, helping engineers evaluate long-term sourcing.

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EPC2LC20ES - 1.6Mb ISP Config PROM for FPGAs | Intel / Altera
EPC2LC20ES

EPC2LC20ES - 1.6Mb ISP Config PROM for FPGAs | Intel / Altera

The Intel (formerly Altera) EPC2LC20ES is an in-system programmable (ISP) configuration memory device designed for SRAM-based FPGAs and LUT devices, providing 1.6 Mbit of non-volatile storage in a 20-pin PLCC (J-lead) package. The device stores configuration bitstreams that are loaded into the FPGA's SRAM configuration cells at power-up, and supports 5.0 V and 3.3 V operation including in-system programmability through the built-in IEEE Std. 1149.1 JTAG interface. The EPC2LC20ES is functionally equivalent to the EPC2LC20 with the "ES" suffix denoting a specific lead-free or industrial temperature grade variant. A Configuration PROM (Programmable Read-Only Memory) for FPGAs is a non-volatile serial memory device that holds the FPGA's configuration bitstream. When the FPGA powers up, it reads its configuration data from the PROM via a serial or parallel configuration interface. These devices sit in the broader memory hierarchy as: PROM -> non-volatile memory -> configuration memory -> FPGA support IC, and are essential for standalone FPGA designs that need to self-configure without an external microprocessor or download cable. Key features of the EPC2LC20ES include 1.6 Mbit storage capacity suitable for mid-density Altera FPGAs such as the ACEX 1K, APEX 20K, Cyclone, and Mercury families, JTAG-based ISP that allows field upgrades without removing the device, and built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1. The device supports both DCLK-based serial and parallel configuration modes, providing flexibility across multiple FPGA targets. Low standby current and 3.3 V/5 V tolerance make it well suited for mixed-voltage system designs. Architecturally, the EPC2LC20ES uses a serial interface with a built-in oscillator and state machine that streams configuration data to the FPGA through the DATA, DCLK, and nCONFIG/nSTATUS control signals. The on-chip JTAG TAP controller enables both ISP and boundary-scan test access. The PROM operates as a slave device on the JTAG chain, allowing multiple devices to be programmed and verified in a single boundary-scan pass. Typical applications include configuration storage for Altera ACEX 1K, APEX 20K, Cyclone, Mercury, and Stratix-class FPGAs, factory-floor JTAG programming stations, and field-upgradable embedded systems. Designers also use this PROM in industrial controllers and military/aerospace prototypes where a self-booting FPGA is required without an external configuration controller. When designing with this device, note that the EPC2LC20ES is rated for industrial temperature range and ships as a lead-free PLCC-20 J-leaded package for through-hole or socketed mounting. The device is in production but considered a legacy Altera configuration solution; for new designs, designers should evaluate Altera/Intel EPCQ-series serial configuration devices (AS mode) for newer FPGA families. This page synthesizes distributor pricing, same-brand and cross-brand drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers quickly validate EPC2LC20ES as a configuration memory solution for legacy and current Altera FPGA designs.

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EPC2LC20N - 1.6Mb FPGA Configuration PROM, 20-PLCC | Intel
EPC2LC20N

EPC2LC20N - 1.6Mb FPGA Configuration PROM, 20-PLCC | Intel

The Intel (formerly Altera) EPC2LC20N is a 1.6-Mbit in-system programmable Flash configuration PROM designed to load configuration bitstreams into SRAM-based LUT FPGAs at every power-up. Housed in a 20-pin PLCC (J-lead, 9x9 mm) package, it operates from dual-rail supplies of 3.0 V to 3.6 V and 4.75 V to 5.25 V, supports JTAG-ISP (IEEE 1532 / IEEE 1149.1) and Altera serial configuration modes, and runs the configuration clock up to 8 MHz. A configuration PROM (Programmable Read-Only Memory) is a non-volatile serial memory device whose sole purpose is to store the bitstream for an SRAM-based programmable logic device. Because SRAM-LUT FPGAs are volatile, their configuration must be reloaded on every power-up or reconfiguration event; the EPC2 family performs that role in a single-chip solution, replacing discrete EPROMs, microcontrollers, or boot-PROM arrangements. EPC2 devices sit in the boot-source hierarchy beneath FPGAs (CPLD -> glue logic -> PROM -> FPGA) and are an integral part of the Altera/Intel FPGA power-on sequencing ecosystem. Key features of the EPC2LC20N include 1.6 Mbit of Flash storage, in-system programmability via JTAG, a built-in 8 MHz internal oscillator, and support for both 3.3 V and 5 V supply rails. It also provides a dedicated nSTATUS, nCONFIG, and CONF_DONE handshake to the target FPGA, eliminating the need for external glue logic in most designs. The EPC2LC20N uses a 4-pin serial interface (DATA0, DCLK, nCONFIG, nSTATUS) to cascade-multiple PROMs can be chained to support larger FPGAs. The device supports FPGAs from the Altera APEX, Cyclone, Stratix, ACEX, and MAX 7000 families, with automatic baud-rate detection between the PROM and target device. Typical applications include Altera/Intel Cyclone and APEX prototype boards, industrial control logic, telecom base-station FPGA boot cards, military/aerospace FPGA subsystems, and any system requiring multi-configuration support. The in-system programmability allows field upgrades without removing the PROM from the board. When designing with this device, ensure proper decoupling (0.1 uF + 10 uF) on both VCC rails and respect the JTAG chain order if multiple PROMs are cascaded. The 5 V rail tolerance simplifies designs that mix 3.3 V FPGA I/O with 5 V configuration memory logic. This page synthesizes distributor stock levels, drop-in Altera/Intel PROM alternatives, and JTAG-chain design notes not found on the original manufacturer datasheet.

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EPC2LC20N-W - 1.6Mb In-System Prog Config PROM | Altera | PLCC-20
EPC2LC20N-W

EPC2LC20N-W - 1.6Mb In-System Prog Config PROM | Altera | PLCC-20

The Intel/Altera EPC2LC20N-W is a 1.6-Mbit in-system programmable (ISP) configuration PROM designed for serial configuration of SRAM-based LUT FPGAs such as APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, and Cyclone families. It is supplied in a 20-pin PLCC (J-lead) package with a 3.0V-3.6V or 4.75V-5.25V dual-rail supply range and supports 66.7 MHz internal oscillator-based serial data delivery. The "-W" suffix denotes the tape-and-reel packaging option of the base EPC2LC20N part. A configuration PROM is a non-volatile memory that stores FPGA bitstream data and serially transfers it to the target FPGA at power-up via the DATA, DCLK, OE, and nCS handshake lines. In the broader hierarchy, the EPC2 sits under Altera's enhanced-configuration-device family (EPC4/EPC8/EPC16/EPC2/EPC1/EPC1441), which itself belongs to the FPGA-support ecosystem (configuration memory -> memory IC -> semiconductor). The 3.3V/5V dual supply, JTAG ISP support, and 1.6-Mbit density make the EPC2LC20N-W one of the most widely used legacy Altera configuration devices. Key features include 1.6 Mbit EPROM density, serial configuration clock up to 66.7 MHz, in-system programmability through the JTAG (Joint Test Action Group) interface, 4-pin serial interface (DATA, DCLK, nCS, OE), and support for cascading with other EPC devices. The device is non-cascadable in the enhanced-configuration-device family when targeting newer high-density Stratix FPGAs; for those applications Altera recommends EPC4/EPC8/EPC16. The EPC2LC20N-W uses an EPROM core that is erased by UV exposure (windowed package variants) and reloaded via JTAG. The internal address counter is clocked by DCLK from the target FPGA, while nCS and OE gate the tri-state DATA output. The combination of a small footprint and a robust serial protocol has made the EPC2 a de-facto standard for APEX 20K and ACEX 1K designs. Typical applications include APEX 20K / ACEX 1K / FLEX 10K FPGA boot configuration, Stratix-series configuration on legacy boards, industrial control system FPGA boot memory, and test equipment FPGA bitstream storage. For designs migrating to Cyclone III/IV/V or Stratix V/10, Altera recommends newer configuration devices or active serial flash. Designers should verify that the target FPGA is compatible with the EPC2 device family using the Altera Configuration Device Compatibility table before PCB layout. The 20-pin PLCC J-lead package requires a socket or reflow profile compatible with J-leaded devices. This page synthesizes distributor pricing, drop-in alternatives, pinout data, and practical design notes not found in the manufacturer datasheet. Lifecycle, supply voltage, and pinout values are extracted verbatim from the Altera EPC2 Configuration Devices datasheet.

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EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20
EPC2LC20NA

EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20

The Altera EPC2LC20NA is an in-system programmable (ISP) Configuration PROM designed to configure SRAM-based LUT FPGAs such as Altera APEX, ACEX, FLEX, and Cyclone families, providing 1.6 Mb of configuration memory in a 20-pin PLCC package. It supports 3.3V operation and is offered in industrial operating temperature grade. A configuration PROM (Programmable Read-Only Memory) is a non-volatile memory device that stores FPGA bitstream data and delivers it to the FPGA at power-up via a serial configuration interface. The EPC2 family belongs to the broader category of FPGA configuration memory, sitting hierarchically under programmable logic boot/storage and above generic serial PROMs. Engineers select configuration PROMs based on bitstream size, target FPGA density, voltage compatibility, and in-system reprogrammability. Key features of the EPC2LC20NA include 1.6 Mbit density, in-system programmability via IEEE 1532 JTAG, 3.3V VCC operation, and a serial configuration data output to the target FPGA. The device supports multi-device daisy-chaining and offers short programming/erase times compared to legacy EPC1 alternatives. The PLCC-20 (9x9 mm) through-hole-compatible surface-mount package facilitates socketed programming and field-replacement workflows. The EPC2LC20NA utilizes Altera's proven floating-gate memory cell array with on-chip charge pumps and a serial state machine that handles the configuration handshake with the host FPGA. The JTAG interface complies with IEEE Std 1149.1 boundary-scan and IEEE 1532 ISP, allowing bitstream updates without removing the device from the PCB. The internal oscillator and timing logic drive the configuration clock to the FPGA in passive serial (PS) mode, eliminating the need for an external configuration clock source. Typical applications include boot configuration for Altera APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, and Mercury FPGA devices; industrial control boards; telecom line cards; and prototyping platforms requiring field firmware updates. The 1.6 Mb capacity comfortably fits bitstreams for mid-density FPGAs up to approximately 200,000 gates. When designing with EPC2LC20NA, ensure the configuration mode (passive serial) of the target FPGA is selected and that the MSEL pins are set accordingly. Place a decoupling capacitor close to VCC and observe JTAG chain ordering when multiple devices share the same TAP controller. This page synthesizes distributor stock levels, drop-in same-package alternatives, and design considerations not found in the manufacturer datasheet, providing practical guidance for legacy system maintenance and new designs targeting Altera FPGA families.

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EPC2LC20NU - 1.6Mb ISP Config PROM 20-PLCC | Intel / Altera
EPC2LC20NU

EPC2LC20NU - 1.6Mb ISP Config PROM 20-PLCC | Intel / Altera

The Intel / Altera EPC2LC20NU is a 1.6-Mbit in-system programmable (ISP) configuration PROM designed to store and deliver configuration bitstreams to SRAM-based LUT FPGAs in the Altera / Intel device family, housed in a 20-pin J-lead PLCC package suitable for surface-mount production lines. An FPGA configuration PROM is a non-volatile memory device that holds the bitstream used to program a volatile SRAM-based FPGA at every power-up. Because SRAM LUTs lose their configuration when power is removed, every system containing an SRAM FPGA requires an external boot memory - either a configuration PROM, a flash, or a microcontroller that emulates the configuration bus. EPC2-series devices implement Altera's serial configuration protocol (compatible with FPGAs such as APEX, Cyclone, and older families) and are re-programmable in-system via JTAG, removing the need for a stand-alone programmer in production. Key features of the EPC2LC20NU include 1.6 Mb of usable configuration memory, an industry-standard 4-pin serial configuration interface (nCS, DCLK, DATA, nINIT_CONF), in-system programmability through the IEEE 1149.1 JTAG port, 3.3 V core supply with 5 V tolerant I/O on most pins, and built-in cascading support so multiple EPC2 devices can be daisy-chained to configure FPGAs larger than 1.6 Mb. The J-lead PLCC-20 footprint has been a long-standing Altera configuration standard and matches the land pattern of earlier EPC1 devices. Technically the EPC2LC20NU is built on a floating-gate CMOS process with on-chip charge pumps to support in-system erase and reprogram cycles without external high voltages. The 4-pin interface lets the host FPGA generate DCLK and read DATA, while a dedicated nINIT_CONF / OE pin releases the bus at power-up or after a reconfiguration event. Programming endurance is rated in the thousands of cycles with data retention measured in decades, allowing field firmware updates. Typical applications include Altera APEX II, APEX 20K, Mercury, FLEX 10K, ACEX 1K, and Cyclone-series SRAM-based LUT FPGAs in industrial controllers, telecom line cards, and military / aerospace prototypes that still rely on the legacy serial configuration protocol. Designers should pair the EPC2LC20NU with the appropriate Altera Quartus configuration file format and verify that the target FPGA bitstream size does not exceed the 1.6 Mb capacity.

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EPC2LC20NUBAF48 - Altera 2Mb Config Device for SRAM FPGAs | FPGA
EPC2LC20NUBAF48

EPC2LC20NUBAF48 - Altera 2Mb Config Device for SRAM FPGAs | FPGA

The Altera (now Intel FPGA) EPC2LC20NUBAF48 is a 2-megabit enhanced-configuration device designed to configure SRAM-based Look-Up Table (LUT) devices, including the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, and FLEX 6000 families. Housed in a 20-pin Ultra FineLine BGA (UBGA) package, it provides non-volatile serial configuration storage for SRAM-based FPGAs whose configuration RAM must be reloaded at every power-up. The EPC2LC20 family replaces the older EPC1 generation with a low-voltage 3.3V core, in-system programmability, and a built-in 2.7V-to-3.6V voltage reference that simplifies mixed-voltage design. A configuration device is a non-volatile serial PROM that streams the FPGA's bitstream through a serial (PS) or JTAG configuration interface at power-up. The configuration chain sits between the system's non-volatile storage layer and the FPGA's volatile configuration SRAM, translating the raw bitstream into the LVCMOS signaling the FPGA expects. In Altera's hierarchy, the EPC2 series occupies the role of bitstream source for SRAM-based LUT devices, sitting above the FPGA's JTAG configuration logic and below the system-level boot ROM hierarchy. Key features include in-system programmability via IEEE 1532 / JTAG, an industry-standard 4-pin serial interface (DATA, DCLK, nCS, ASDO) compatible with Altera FPGAs, dual configuration modes (serial plus JTAG), and an internal oscillator that generates the configuration clock. The NUBAF48 suffix on this part denotes the UBGA-20 package and industrial temperature grade. Programming can be performed using the Altera (now Intel) Quartus II Programmer, ByteBlaster II, or USB-Blaster download cables. Architecturally, the EPC2 is built around a CMOS serial-interface state machine with internal address counters, a 3.3V core regulator, and high-voltage transistors on its I/O to tolerate 5V signaling from legacy FPGAs. Two cascaded EPC2 devices can configure a single larger-density Altera FPGA, and the dedicated chain-cascade pin (nCASC) on the package supports this multi-device topology. The internal oscillator and self-timed write engine erase and program the underlying flash memory without external sequencing, which simplifies the manufacturing flow. Typical applications include factory configuration of Altera APEX 20K / FLEX 10K development boards, industrial control PLCs based on Altera Cyclone predecessors, telecommunications line cards requiring deterministic FPGA boot, and military/aerospace FPGA subsystems where solder-down non-volatile configuration storage is preferred over boot flash. Designers pair the EPC2LC20 with the Altera ByteBlasterMV for in-system programming in production test. When designing with this device, note that the 'L' suffix denotes the 3.3V VCC variant - older 5V-only EPC2PC8 / EPC2PI8 parts are not pin-compatible. Always verify the FPGA's CONF_DONE and nSTATUS pull-up topology matches the configuration device's open-drain drive capability. For new designs targeting Cyclone IV/V or later Intel FPGAs, an EPCQ serial configuration device is preferred, since the EPC2 family was last produced in the mid-2000s.

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EPC2LC20V - Altera 1.6Mb Flash Config Device, PLCC-20 | Intel
EPC2LC20V

EPC2LC20V - Altera 1.6Mb Flash Config Device, PLCC-20 | Intel

The Altera EPC2LC20V (now under Intel) is a 1.6 Mb Flash-memory-based Configuration Device designed to load the configuration bitstream of SRAM-based Look-Up Table (LUT) FPGAs such as the Altera Cyclone, Stratix, APEX, and ACEX families. Housed in a 20-pin Plastic Leaded Chip Carrier (PLCC-20) package, it provides in-system programmability via a standard JTAG (IEEE 1149.1) interface and operates at a 10 MHz serial configuration clock with a maximum configuration data width of 8 bits. The 'V' suffix denotes the lead-free / Pb-free PLCC package, while the '20' designates the 20-pin JEDEC PLCC outline. A Configuration Device is a non-volatile memory that stores the FPGA's configuration bitstream and serially or byte-parallel delivers it to the FPGA's DATA, DCLK, and nCONFIG pins at power-up. In the broader taxonomy, an FPGA configuration PROM sits below non-volatile memory > Flash memory > PROM > configuration memory within the semiconductor hierarchy. It bridges the volatile SRAM-LUT architecture (which loses configuration when power is removed) with a permanent, field-updatable boot source - eliminating the need for external boot PROMs from third-party vendors and enabling remote firmware revision via JTAG. Key features include 1.6 Mb of usable configuration storage (more than 4x the original EPC1), a flexible serial or 8-bit parallel configuration interface, an on-chip oscillator to generate DCLK, JTAG boundary-scan support (IEEE 1149.1), and in-system programmability through JTAG without external programmer hardware. The PLCC-20 footprint provides rugged mechanical compliance for industrial through-hole and socketed assemblies, and the device is compatible with the older EPC1 / EPC1064 / EPC1441 pinouts on a 1:1 basis within the same package family. Typical applications include standalone boot of Altera Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III, ACEX 1K, APEX 20K, APEX II, and older FLEX 10K / FLEX 8000 devices in industrial controllers, telecommunications line cards, test & measurement chassis, and military/aerospace FPGA systems. Because the EPC2 supports both serial and 8-bit byte-wide configuration, a single PROM can serve either low-pin-count or high-throughput FPGA boot scenarios. When designing with this device, verify that the FPGA's configuration mode (AS, PS, or JTAG-only) matches the EPC2's supported modes, since the EPC2 is intended for PS (Passive Serial) and JTAG programming - it does not support Altera Active Serial (AS) mode, which uses serial Flash such as EPCS / EPCQ devices. Add a 0.1 uF decoupling capacitor near the VCC pin and ensure nINIT_CONF and nSTATUS are correctly tied to the FPGA's nCONFIG / nSTATUS pins. This page synthesizes distributor pricing, drop-in compatible configuration-memory alternatives, JTAG programming notes, and PLCC-20 package cross-references not found in the original Altera datasheet - giving a single source for engineers re-spinning legacy Altera FPGA designs.

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EPC2LC21N - Altera/Intel Configuration PROM for SRAM FPGAs
EPC2LC21N

EPC2LC21N - Altera/Intel Configuration PROM for SRAM FPGAs

The Altera/Intel EPC2LC21N is a 1.6-Mbit in-system-programmable configuration PROM designed to load configuration bitstreams into Altera SRAM-based FPGAs and Complex Programmable Logic Devices (CPLDs). It is supplied in a 20-pin PLCC package and supports 3.3V operation, making it a drop-in companion for legacy Altera APEX, ACEX, FLEX, Cyclone, and MAX-series FPGAs. The device uses a simple serial configuration interface and provides JTAG-based in-system programmability (ISP), which allows the configuration bitstream to be updated on the populated PCB without removing the part. A configuration PROM is a non-volatile memory device that stores the FPGA's configuration bitstream and presents it serially to the target FPGA at power-up. It belongs to the broader category of non-volatile memories, sitting hierarchically between EPROM/EEPROM and flash, and serves as a one-chip boot source for SRAM-based programmable logic. The EPC2 family combines the configuration storage role with ISP, so designers can rework a board's logic image without hot-air rework or socket swaps. Key features of the EPC2LC21N include 1.6 Mbit of configuration storage, 3.3V single-supply operation, JTAG-ISP support, an open-drain CONF_DONE signal for handshaking with the FPGA, and a low-power CMOS process. The serial interface minimizes FPGA pin consumption, while the JTAG path supports boundary-scan and field upgrades. The PLCC-20 footprint is through-hole friendly and remains compatible with older Altera reference designs that predate the migration to surface-mount EPCQ/QSPI flash. The EPC2LC21N's underlying technology is a high-density EPROM/EEPROM-style cell array with on-chip charge-pump programming logic, wrapped in a controller that streams data to the FPGA's DCLK/DATA pins. The part is designed for unlimited configuration reads (FPGA always reads at POR) and a finite ISP-write endurance. Its 3.3V I/O and lack of a separate program voltage supply simplify power-tree design relative to older 5V EPC1 parts. Typical applications include legacy Altera APEX 20K and FLEX 10K configuration loading, industrial control boards that still ship on Altera MAX/Cyclone FPGAs, prototyping carriers, and field-upgradeable logic modules. The PLCC package is particularly attractive for through-hole assembly and for repair-friendly board designs in industrial equipment. When designing with this part, route the JTAG chain (TCK/TMS/TDO/TDI) so the EPC2 shares the FPGA's boundary-scan path; this enables in-system reconfiguration via a single Altera USB-Blaster or ByteBlaster. Confirm that the target FPGA's configuration mode selects serial PROM and that the EPC2's nCS pin is wired to the correct FPGA nSTATUS or mode pin. Leave nINIT_CONF tied correctly per the Altera configuration handbook to avoid false reconfiguration cycles. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single source for lifecycle, replacement, and application guidance on the EPC2LC21N.

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EPC2LC22N - 1.6Mb Altera Configuration PROM | PLCC-22
EPC2LC22N

EPC2LC22N - 1.6Mb Altera Configuration PROM | PLCC-22

The Altera EPC2LC22N is an in-system programmable configuration PROM designed for loading configuration bitstreams into SRAM-based Altera FPGAs. According to the EPC2 configuration device datasheet from Intel/Altera, the part stores 1.6 Mbits of configuration data and is offered in a 22-pin Plastic Leaded Chip Carrier (PLCC-22) package with through-hole mounting. A configuration PROM is a non-volatile memory device that holds the FPGA's configuration bitstream. When the FPGA powers up, it reads its configuration data from a configuration PROM (typically via JTAG or a dedicated serial interface). Configuration PROMs belong to the broader category of non-volatile memory ICs and serve as boot memory for SRAM-based FPGAs (which lose their configuration when power is removed). The EPC2 family specifically targets Altera's legacy APEX, Mercury, ACEX, Cyclone, and Stratix FPGAs. Key features of the EPC2LC22N include in-system programmability via IEEE 1149.1 (JTAG) boundary-scan, cascadable architecture for multi-device configuration chains, and low-power CMOS technology. The device supports Altera's serial configuration protocol and can be cascaded to support arbitrarily large bitstreams. The 2.5V core (LC designation) provides lower power consumption than the 5V and 3.3V variants in the EPC2 family. The EPC2LC22N uses a 4-pin JTAG interface (TCK, TMS, TDI, TDO) for in-system programming, eliminating the need for a separate PROM programmer. The cascadable design allows multiple EPC2 devices to be chained together to configure FPGAs with bitstreams larger than 1.6 Mbits. The device includes an internal oscillator and timing control, simplifying board design by removing the need for external configuration clock generation. Typical applications include legacy Altera APEX 20K / APEX II FPGA configuration, ACEX 1K boot memory, Mercury device support, and embedded systems requiring in-field FPGA reconfiguration via JTAG. The PLCC-22 through-hole package is suited for prototyping, legacy board designs, and applications where socketed configuration memory is preferred for field serviceability. When designing with the EPC2LC22N, ensure the JTAG chain is properly terminated and the FPGA's MSEL pins are set to the correct configuration mode for serial PROM boot. Note that this part is now in legacy status and is replaced in many new designs by newer Cyclone/MAX series FPGAs with built-in flash configuration memory, eliminating the external PROM altogether. This page synthesizes Intel/Altera datasheet information, distributor pricing, and drop-in compatible EPC2 family alternatives not found in a single manufacturer document, providing practical sourcing guidance for legacy FPGA design maintenance.

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EPC2LC2QN - 2Mb SRAM-Based LUT FPGA Config Device | Altera
EPC2LC2QN

EPC2LC2QN - 2Mb SRAM-Based LUT FPGA Config Device | Altera

The Altera EPC2LC2QN is a 2-megabit serial configuration device designed to load configuration data into SRAM-based Altera FPGAs that use LUT (look-up table) architecture, including the APEX II, Cyclone, and Stratix device families. The device supports a 3.3V core supply, operates from 0°C to +70°C commercial temperature range, and is housed in a 100-pin PQFP package. According to Altera (now Intel FPGA) configuration-device collateral, the EPC2LC2QN supports flexible configuration schemes including JTAG-based in-system programmability and serial daisy-chain multi-device configuration, enabling designers to update bitstreams in the field without removing the FPGA from the board. A configuration device is a non-volatile serial Flash memory specifically engineered to store and stream FPGA configuration bitstreams to an SRAM-based LUT FPGA at power-up. Because SRAM-based LUT devices lose their configuration when power is removed (volatile technology), a companion configuration device such as the EPC2LC2QN is required to reload the bitstream on every POR (power-on reset) event. This category sits within the broader hierarchy of non-volatile memory ICs, parallel and serial boot Flash devices, and FPGA configuration memory, and is essential to any system that uses SRAM-based LUT FPGAs. Key features include 2 Mb of configuration storage, a 4-wire serial interface to the host FPGA (DATA, DCLK, nCONFIG, nSTATUS), in-system programmability through the JTAG (IEEE 1149.1) boundary-scan interface, support for multi-device daisy-chain configuration of up to 8 FPGAs, and built-in decompression of Altera-compressed bitstreams. The 100-pin PQFP (Plastic Quad Flat Pack) surface-mount package provides sufficient pin count for the configuration control signals and JTAG test access port, while maintaining a compact board footprint compared to older PLCC packages. Technically, the EPC2LC2QN uses an internal oscillator to generate the configuration clock (DCLK) and supports both serial and parallel configuration modes. The device accepts compressed bitstreams from the Quartus II / Quartus Prime programmer and decompresses them on the fly before forwarding to the target FPGA, effectively doubling the usable storage. The 3.3V single-supply operation simplifies power-tree design in 3.3V-centric boards that pair with APEX II or first-generation Cyclone FPGAs. Typical applications include Altera APEX II EP2A15/EP2A25/EP2A40 configuration, Cyclone EP1C3/EP1C4/EP1C6/EP1C12 boot, Stratix EP1S10/EP1S20/EP1S25 memory loading, JTAG-based field firmware update in industrial controllers, and multi-FPGA prototyping boards where daisy-chain configuration reduces board complexity. Designers also use the EPC2LC2QN in legacy migration designs that must remain pin-compatible with older Altera reference schematics. When designing with this device, ensure the JTAG chain includes the configuration device's TMS, TCK, TDI, and TDO pins wired in series with the FPGA's JTAG port to allow boundary-scan programming. Verify the VCC ramp time meets the 100 µs minimum required by the EPC2 configuration controller to avoid POR ambiguity. This page synthesizes distributor pricing, drop-in Altera-family configuration alternatives, and practical design notes not collected in the standalone Altera datasheet.

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