EPC2LC20 vs EPC21LC20 比較

詳細な並列比較: EPC2LC20 メーカー: Altera および EPC21LC20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPC2LC20 EPC21LC20
ブランド Altera Intel
カテゴリ Memory ICs Memory ICs
ライフサイクル状態 NRND 有効
在庫状況 In Stock In Stock
単価(USD) $7.20 $10.40
メモリタイプ Non-volatile configuration PROM Serial Configuration PROM (Flash-based, in-system programmable)
メモリサイズ 1.6 Mbit —
Configuration Interface Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE —
Programming Interface IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant IEEE 1149.1 (JTAG)
Supply Voltage VCC 3.0 V to 3.6 V (3.3-V operation) —
ISP Voltage Range 5.0 V or 3.3 V —
Supported FPGA Families ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 —
Cascade Support Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams —
パッケージ 20-pin PLCC (J-lead, 9x9 mm) —
実装タイプ Surface Mount Surface Mount (PLCC socket or solder)
動作温度 -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] —
RoHS ステータス Non-Compliant (original Altera Pb-containing part) [DATA_NEEDED: confirm from Altera product page]
Lead-Free Version EPC2LC20N available as lead-free equivalent —
Programming Support Altera Programming Unit (APU), Quartus II, JTAG programmer —
Boundary-Scan IEEE 1149.1 compliant, 8-bit or 16-bit JTAG —
Density — 2 Mb (2,097,152 bits)
Configuration Mode Supported — Serial (PS) for Altera SRAM-based LUT FPGAs
Maximum DCLK Frequency — 10 MHz
Access Time — approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure]
Program/Erase Endurance — 100 cycles minimum [DATA_NEEDED: confirm from datasheet]
Operating Voltage (VCC) — 3.0 V to 3.6 V (3.3 V typical)
Standby Current — [DATA_NEEDED: ICCSB value]
Active Read Current — [DATA_NEEDED: ICC active current]
Operating Temperature (commercial) — 0 °C to +70 °C (LC suffix)
Operating Temperature (industrial) — [DATA_NEEDED: -40 to +85 °C for LI variant]
パッケージ / ケース — 20-pin PLCC (J-lead, JEDEC MS-018)
MSLレベル — [DATA_NEEDED: confirm moisture sensitivity level]
Lead-Free (Pb-free) — [DATA_NEEDED: confirm]
Compatible FPGA Families — ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT)
JTAG Boundary-Scan Compliant — Yes (IEEE Std 1149.1)
Data Width — 1 bit (serial DATA output)

データシート&リソース

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