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i7-5700HQ - 4C/8T Broadwell-H Mobile CPU up to 3.5GHz | Intel
i7-5700HQ

i7-5700HQ - 4C/8T Broadwell-H Mobile CPU up to 3.5GHz | Intel

The Intel Core i7-5700HQ is a 4-core, 8-thread mobile processor built on Intel's 14nm Broadwell-H architecture, launched in June 2015 at a $378 MSRP. It operates at a 2.70 GHz base clock with Intel Turbo Boost up to 3.50 GHz, integrates 6 MB of L3 cache, and is soldered onto the motherboard in a BGA-1364 package (also referenced as FCBGA-1364). The i7-5700HQ supports dual-channel DDR3L-1600 memory and is rated at a 47 W TDP, making it a mainstream performance CPU for 2015-era gaming and workstation notebooks. A mobile quad-core processor (HQ-class) is Intel's high-performance tier for laptops, sitting above U-series (ultrabook) and H-series dual-core parts. The Core i7 brand indicates Hyper-Threading, larger cache, and higher Turbo ceilings than Core i5/i3 siblings. Broadwell-H represents the 5th-generation Core microarchitecture, succeeding Haswell with a 14nm tri-gate process, an updated integrated Iris Pro 6200 GPU, and improved instruction-per-clock efficiency. These processors are soldered (BGA) and not user-upgradeable. Key features include 4 physical cores with Hyper-Threading for 8 logical threads, a 6 MB shared L3 cache, and a configurable TDP-down mode of 35 W for thermal-constrained chassis. The integrated Iris Pro 6200 graphics with 48 execution units and 128 MB of eDRAM (L4 cache) provides modest gaming capability and Quick Sync video acceleration. AVX2 and AES-NI instructions accelerate compute and cryptographic workloads. Architecturally, Broadwell-H pairs an updated out-of-order core with a ring interconnect to the System Agent, integrated memory controller, and GT3e-class graphics. The 14nm process allowed higher frequencies at the same 47 W envelope versus the 22nm Haswell predecessor, while the 128 MB eDRAM side-cache boosts both CPU and GPU bandwidth when working on data sets that fit inside it. Typical applications include 2015-2016 era gaming laptops, mobile workstations running CAD or video editing software, and high-performance ultrabooks where the 47 W TDP can be cooled. The quad-core/8-thread configuration suits multi-tasking, video encoding, and lightly threaded productivity. The integrated GPU also enables headless media transcode via Quick Sync. Design consideration: because this is a BGA-1364 soldered part, replacement requires motherboard-level rework. When sourcing refurbished laptops, verify the BIOS supports the i7-5700HQ stepping and pair with dual-channel DDR3L-1600 SODIMMs to avoid memory bandwidth bottlenecks to the integrated GPU. This page synthesizes distributor listings, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.

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iCE40LP384-SG48 - 384 LUT Ultra-Low-Power FPGA | Lattice Semi
iCE40LP384-SG48

iCE40LP384-SG48 - 384 LUT Ultra-Low-Power FPGA | Lattice Semi

The Lattice Semiconductor iCE40LP384-SG48 is an ultra-low-power Field Programmable Gate Array (FPGA) from the iCE40 LP family, delivering 384 Look-Up Tables (LUTs) in a 48-pin QFN (SG48) package with 1.2V core voltage and 21 user I/O. It is fabricated on a 40 nm CMOS process optimized for minimal static and dynamic power consumption, targeting mobile, handheld, and energy-harvesting designs where battery life dominates the bill of materials. The device integrates a hardened I2C core, SPI configuration interface, and on-chip PLL blocks, providing a complete glue-logic platform in a sub-1 mW active power envelope. An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit composed of configurable logic blocks (LUTs), programmable interconnect, and I/O cells that can be re-programmed to implement arbitrary digital logic. Low-power FPGAs such as the iCE40 LP family occupy a unique tier in the programmable logic hierarchy - sitting above fixed-function ASICs (which offer zero flexibility) and below high-density FPGAs from Xilinx and Intel (which offer millions of LUTs at the cost of watts). The iCE40 LP family is the de-facto choice when an application needs custom logic, multiple interfaces, or hardware acceleration, but the system can only afford a few hundred microwatts of quiescent draw. Within the Lattice portfolio, iCE40LP sits between the older iCE65 and the higher-density ECP5 family. Key features include 384 4-input LUTs, 21 user I/O pins, embedded RAM (4 kbits block RAM equivalent), two 16-bit timers/counters, two I2C controllers, one SPI controller, and a hard PLL supporting clock multiplication. The device operates from a 1.14 V to 1.26 V core supply with separate I/O bank supplies from 1.71 V to 3.465 V, enabling direct interfacing to 1.8 V, 2.5 V, and 3.3 V peripherals. Typical static current is below 100 uA at 25 C, and active current scales linearly with toggle rate and logic utilization. Architecturally, the iCE40LP384 uses a non-volatile SRAM configuration cell (volatile SRAM, but loaded from NV memory at boot) backed by NVCM or SPI Flash. Logic is implemented as 4-input LUTs feeding a programmable interconnect fabric, with carry chains for arithmetic and block RAM for storage. The hard I2C and SPI controllers reduce LUT usage for common bus interfaces, leaving more logic free for application-specific state machines and datapaths. Typical applications include mobile device glue logic, IoT sensor hubs, wearable sensor aggregation, low-power display controllers (SPI/parallel LCD), handheld medical peripherals, and battery-powered industrial sensor nodes. The 48-pin QFN package balances I/O count with hand-solder-friendly footprint for prototype work. When designing with this device, remember that the 1.2 V core rail must be sequenced within 50 ms of the I/O rails to prevent I/O cell back-powering through ESD diodes. Use the Lattice iCEcube2 design suite for synthesis, place-and-route, and bitstream generation.

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iCE40UP5K-SG48 - 5280 LUT UltraPlus FPGA QFN-48 | Lattice
iCE40UP5K-SG48

iCE40UP5K-SG48 - 5280 LUT UltraPlus FPGA QFN-48 | Lattice

The Lattice Semiconductor iCE40UP5K-SG48 is an iCE40 UltraPlus low-power FPGA with 5280 Look-Up Tables (LUTs), 128 Kbit of dual-port block RAM, 1 Mbit of single-port RAM, and eight 16x16 DSP MAC blocks, housed in a 48-pin VFQFN exposed-pad (SG48) package. A Field Programmable Gate Array (FPGA) is a reconfigurable logic device that implements digital circuits through programmable interconnect and logic blocks. Within the semiconductor hierarchy, FPGAs sit alongside microcontrollers and ASICs as programmable silicon; the iCE40 UltraPlus family occupies the ultra-low-power end of the FPGA spectrum, targeting mobile, IoT, and AI/ML edge applications where milliwatts matter. Key features include two hard-IP SPI and two hard-IP I2C controllers that offload protocol handling from soft logic, two internal oscillators (10 kHz and 48 MHz) that eliminate external clock sources in cost-sensitive designs, three 24 mA constant-current RGB outputs with hard RGB PWM IP for direct LED drive, and dedicated DSP blocks with 16x16 multiply and 32-bit accumulate for lightweight neural network inference. Architecturally, the iCE40UP5K combines a 4-input LUT plus carry chain plus flip-flop fabric with 120 Kbit of distributed sysMEM block RAM and 1 Mbit SPRAM, a phase-locked loop (PLL) for clock synthesis, and low-power 1.2V core operation consistent with the family's positioning as the lowest-power machine learning solution in its class. Typical applications include sensor aggregation and pre-processing for mobile platforms, always-on AI/ML inference at the edge, and system management or bridge logic where two SPI and two I2C hard IPs reduce firmware complexity. The SG48 QFN footprint also suits compact boards such as the iCEBreaker open-source FPGA platform. Design consideration: use the SG48 package with QSPI flash configuration and account for the exposed thermal pad in PCB layout for reliable ground return. This page synthesizes distributor listings, drop-in family alternatives, and practical design notes not consolidated in the manufacturer datasheet.

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