ISPLSI 1032-60LT - 128-Macrocell 5V CPLD, 60MHz, TQFP-100 | Lattice
MPN: 1032-60LT ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
1032-60LT Overview
What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that sits between simple SPLDs/PLAs and large FPGAs in the programmable-logic taxonomy (CPLD -> PLD -> programmable logic -> digital semiconductor). It uses a small-block, sum-of-products architecture with macrocells, making it ideal for implementing wide combinational and registered logic, glue logic, bus decoding, state machines, and address decoding. Unlike SRAM FPGAs, the ispLSI 1032 is non-volatile and in-system programmable via a standard 5-pin JTAG chain, so designs can be updated on production hardware without removing the device.
Key features of the ISPLSI 1032-60LT include 32 logic elements (each containing 16 macrocells with associated I/O), 6000 gates of usable logic, 4 dedicated clock inputs feeding four global clock buffers, asynchronous clear and preset per register, JTAG/IEEE 1149.1 boundary-scan test support, and 5 V CMOS I/O with TTL-compatible thresholds. The GRP provides a deterministic, fixed interconnect delay regardless of placement, simplifying timing closure for registered and combinatorial logic.
Typical applications include wide address decoding, bus interface glue logic, state-machine controllers, peripheral interface latching, fast counters, frequency and pulse-width measurement, and any design requiring non-volatile, deterministic-timing 5 V glue logic in industrial control, telecom backplane, and embedded processor bus systems.
When designing with this device, ensure the 5 V supply is within the 4.75 V to 5.25 V range and that all I/O banks are referenced to a single 5 V rail. Decouple VCC with 0.1 uF and 10 uF capacitors close to the pins. Note that Lattice's own ispMACH 4000V is the recommended modern replacement family for new designs.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for 1032-60LT — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ISPLSI 1032-70LT
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ISPLSI 1032-60L
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LC4128V-75T100
✅ Drop-In📋 Reference alternative (not in catalog)
LC4064V-75T100
✅ Drop-In📋 Reference alternative (not in catalog)
ATF1508AS-10AU100
✅ Drop-In📋 Reference alternative (not in catalog)
XC95108XL-10TQ100
✅ Drop-In📋 Reference alternative (not in catalog)
1032-60LT Maximum Ratings & Electrical Characteristics
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | ispLSI 1000 |
| Number of Macrocells | 128 |
| Number of Logic Elements/Blocks | 32 |
| Number of Gates | 6000 PLD gates |
| Number of Registers | 192 |
| Number of Universal I/O Pins | 64 |
| Number of Dedicated Input Pins | 8 |
| Number of Dedicated Clock Input Pins | 4 |
| Maximum Propagation Delay (tpd) | 20 ns |
| Maximum Operating Frequency (fMAX) | 60 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Programmable Type | In-System Programmable (ISP) / JTAG |
| Package | 100-pin TQFP |
| Mounting Type | Surface Mount |
| JTAG / Boundary Scan | IEEE 1149.1 compliant |
1032-60LT Pin Configuration
| Pin 1 | GND — Ground |
| Pin 2 | Y4/RESET — Dedicated clock input or global reset |
| Pin 3 | I/O — Universal I/O pin (group A) |
| Pin 4 | I/O — Universal I/O pin (group A) |
| Pin 5 | I/O — Universal I/O pin (group A) |
| Pin 6 | I/O — Universal I/O pin (group A) |
| Pin 7 | I/O — Universal I/O pin (group A) |
| Pin 8 | I/O — Universal I/O pin (group A) |
| Pin 9 | I/O — Universal I/O pin (group A) |
| Pin 10 | I/O — Universal I/O pin (group A) |
| Pin 11 | GND — Ground |
| Pin 12 | VCC — +5 V supply |
| Pin 13 | I/O — Universal I/O pin (group B) |
| Pin 14 | I/O — Universal I/O pin (group B) |
| Pin 15 | I/O — Universal I/O pin (group B) |
| Pin 16 | I/O — Universal I/O pin (group B) |
| Pin 17 | I/O — Universal I/O pin (group B) |
| Pin 18 | I/O — Universal I/O pin (group B) |
| Pin 19 | I/O — Universal I/O pin (group B) |
| Pin 20 | I/O — Universal I/O pin (group B) |
| Pin 21 | GND — Ground |
| Pin 22 | VCC — +5 V supply |
| Pin 23 | I/O — Universal I/O pin (group C) |
| Pin 24 | I/O — Universal I/O pin (group C) |
| Pin 25 | I/O — Universal I/O pin (group C) |
| Pin 26 | I/O — Universal I/O pin (group C) |
| Pin 27 | I/O — Universal I/O pin (group C) |
| Pin 28 | I/O — Universal I/O pin (group C) |
| Pin 29 | I/O — Universal I/O pin (group C) |
| Pin 30 | I/O — Universal I/O pin (group C) |
| Pin 31 | GND — Ground |
| Pin 32 | VCC — +5 V supply |
| Pin 33 | I/O — Universal I/O pin (group D) |
| Pin 34 | I/O — Universal I/O pin (group D) |
| Pin 35 | I/O — Universal I/O pin (group D) |
| Pin 36 | I/O — Universal I/O pin (group D) |
| Pin 37 | I/O — Universal I/O pin (group D) |
| Pin 38 | I/O — Universal I/O pin (group D) |
| Pin 39 | I/O — Universal I/O pin (group D) |
| Pin 40 | I/O — Universal I/O pin (group D) |
| Pin 41 | GND — Ground |
| Pin 42 | VCC — +5 V supply |
| Pin 43 | Y0 — Dedicated clock input 0 |
| Pin 44 | Y1 — Dedicated clock input 1 |
| Pin 45 | Y2 — Dedicated clock input 2 |
| Pin 46 | Y3 — Dedicated clock input 3 |
| Pin 47 | IN0 — Dedicated input 0 |
| Pin 48 | IN1 — Dedicated input 1 |
| Pin 49 | IN2 — Dedicated input 2 |
| Pin 50 | IN3 — Dedicated input 3 |
| Pin 51 | GND — Ground |
| Pin 52 | VCC — +5 V supply |
| Pin 53 | TDI — JTAG test data input |
| Pin 54 | TMS — JTAG test mode select |
| Pin 55 | TCK — JTAG test clock |
| Pin 56 | TDO — JTAG test data output |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | I/O — Universal I/O pin (group E) |
| Pin 59 | I/O — Universal I/O pin (group E) |
| Pin 60 | I/O — Universal I/O pin (group E) |
| Pin 61 | I/O — Universal I/O pin (group E) |
| Pin 62 | GND — Ground |
| Pin 63 | VCC — +5 V supply |
| Pin 64 | I/O — Universal I/O pin (group E) |
| Pin 65 | I/O — Universal I/O pin (group E) |
| Pin 66 | I/O — Universal I/O pin (group E) |
| Pin 67 | I/O — Universal I/O pin (group E) |
| Pin 68 | I/O — Universal I/O pin (group F) |
| Pin 69 | I/O — Universal I/O pin (group F) |
| Pin 70 | I/O — Universal I/O pin (group F) |
| Pin 71 | I/O — Universal I/O pin (group F) |
| Pin 72 | GND — Ground |
| Pin 73 | VCC — +5 V supply |
| Pin 74 | I/O — Universal I/O pin (group F) |
| Pin 75 | I/O — Universal I/O pin (group F) |
| Pin 76 | I/O — Universal I/O pin (group F) |
| Pin 77 | I/O — Universal I/O pin (group F) |
| Pin 78 | I/O — Universal I/O pin (group G) |
| Pin 79 | I/O — Universal I/O pin (group G) |
| Pin 80 | I/O — Universal I/O pin (group G) |
| Pin 81 | I/O — Universal I/O pin (group G) |
| Pin 82 | GND — Ground |
| Pin 83 | VCC — +5 V supply |
| Pin 84 | I/O — Universal I/O pin (group G) |
| Pin 85 | I/O — Universal I/O pin (group G) |
| Pin 86 | I/O — Universal I/O pin (group G) |
| Pin 87 | I/O — Universal I/O pin (group G) |
| Pin 88 | I/O — Universal I/O pin (group H) |
| Pin 89 | I/O — Universal I/O pin (group H) |
| Pin 90 | I/O — Universal I/O pin (group H) |
| Pin 91 | I/O — Universal I/O pin (group H) |
| Pin 92 | GND — Ground |
| Pin 93 | VCC — +5 V supply |
| Pin 94 | I/O — Universal I/O pin (group H) |
| Pin 95 | I/O — Universal I/O pin (group H) |
| Pin 96 | I/O — Universal I/O pin (group H) |
| Pin 97 | I/O — Universal I/O pin (group H) |
| Pin 98 | I/O — Universal I/O pin (group H) |
| Pin 99 | I/O — Universal I/O pin (group H) |
| Pin 100 | I/O — Universal I/O pin (group H) |
Typical Applications
1032-60LT is suitable for 6 applications: Wide Address Decoding in Embedded Systems, Bus Interface Glue Logic, State Machine Controllers, Fast Counters and Frequency Measurement, Peripheral Interface Latching and Timing, Industrial Control and Backplane Logic.
Wide Address Decoding in Embedded Systems
The ISPLSI 1032-60LT is well suited to wide address decoding in 16/32-bit embedded processor systems where multiple peripherals share the bus. The 128 macrocells easily handle chip-select decoding for memories, peripherals, and bus buffers, while the 64 I/O provide enough pins to decode full 24-bit or 26-bit address spaces. The 20 ns propagation delay adds minimal wait-state overhead at 60 MHz system clocks, and JTAG ISP allows last-minute board redefinition. Placed between the processor and memory bus, the device replaces dozens of 74-series decoders with a single non-volatile part that survives power cycles without reload.
Recommended
Bus Interface Glue Logic
For board-level glue logic between microprocessors, DSPs, ASICs, and bus transceivers, the ISPLSI 1032-60LT consolidates multiple 74-series logic functions into one programmable part. The 6000 gates and 192 registers handle data-bus multiplexing, handshaking, and protocol translation in a single device. Its 5 V tolerance matches TTL/CMOS peripherals, while JTAG ISP enables post-incident iteration to fix logic bugs without respinning the PCB. The non-volatile configuration means no boot PROM is required, simplifying the BOM and shortening the bring-up cycle.
Recommended
State Machine Controllers
The ISPLSI 1032-60LT implements complex state machines, sequencers, and protocol controllers that would otherwise require a microcontroller. Wide input gating (16-product-term macrocells with shared expanders) and the deterministic GRP interconnect make timing closure straightforward even for 8- or 16-state machines. Typical uses are industrial controller sequencers, motor drive state machine, and protocol controllers in telecom backplanes. The 60 MHz fMAX grade handles real-time state transitions at typical 10-25 MHz state-machine clock rates, leaving margin for synchronous I/O. The JTAG boundary scan aids board-level test of the state machine I/O.
Recommended
Fast Counters and Frequency Measurement
The ISPLSI 1032-60LT serves as a fast counter, period/frequency counter, or pulse-width measurement engine. The 4 dedicated clock inputs feed four global clock buffers that can drive counters synchronously, while the 192 registers accommodate multi-stage ripple or synchronous counters up to 24 bits. The 60 MHz fMAX grade handles direct frequency counting up to 60 MHz without prescaling, and wide input gating allows combining counters with comparators and decoders in the same device. Used in instrumentation, telecom line cards, and motor speed measurement.
Recommended
Peripheral Interface Latching and Timing
For latching data from high-speed peripherals such as parallel ADCs, DACs, or LVDS interfaces, the ISPLSI 1032-60LT provides 64 I/O with deterministic 20 ns tpd and 192 registers for multi-byte data pipelines. The GRP simplifies timing closure by giving every registered output the same clock-to-output skew, ideal for source-synchronous interfaces. JTAG boundary scan simplifies board-level test of all 64 I/O, which is critical in dense surface-mount designs where traditional test points are inaccessible.
Recommended
Industrial Control and Backplane Logic
In industrial control cabinets, motor drive backplanes, and telecom line cards, the ISPLSI 1032-60LT implements the deterministic 5 V logic glue between processors, drivers, and bus transceivers. Its 5 V supply, 64 I/O, and 192 registers handle optocoupler inputs, relay drivers, encoder/encoder contacts, and serial communication. The deterministic GRP timing supports hard real-time control loops at 1-10 kHz with deterministic latencies, which is essential in safety-critical and motor control systems. The non-volatile EEPROM configuration survives brown-outs without boot PROMs.
Recommended
Recommended Products Summary
Engineering reference data for 1032-60LT — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ISPLSI 1032-70LT | ISPLSI 1032-60L | LC4128V-75T100 | LC4064V-75T100 | ATF1508AS-10AU100 | XC95108XL-10TQ100 |
|---|---|---|---|---|---|---|---|
| Brand | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Microchip Technology | Xilinx |
| Package | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 |
| Macrocells | 128 | 128 | 128 | 128 | 64 | 128 | 108 |
| Propagation Delay (tpd) | 20 ns | 15 ns | 20 ns | 7.5 ns | 7.5 ns | 10 ns | 10 ns |
| Supply Voltage | 5 V (4.75 V - 5.25 V) | 5 V (4.75 V - 5.25 V) | 5 V (4.75 V - 5.25 V) | 3.3 V (3.0 V - 3.6 V) / 5 V tolerant | 3.3 V (3.0 V - 3.6 V) / 5 V tolerant | 5 V (4.75 V - 5.25 V) | 3.3 V (3.0 V - 3.6 V) / 5 V tolerant |
| In-System Programmable (ISP) | Yes (JTAG IEEE 1149.1) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Active | Active | Active | Obsolete |
Key Differentiators
- Non-volatile EEPROM configuration - no boot PROM required (vs SRAM FPGAs in the same gate-count class)
- Deterministic GRP timing - no placement-dependent delays (vs XC95108XL-10TQFP-100 (Xilinx))
- 5 V native supply - direct interface to TTL/CMOS peripherals (vs LC4128V-75T100 (Lattice ispMACH 4000V))
Design Notes
Power the ISPLSI 1032-60LT from a 5 V rail regulated within 4.75 V to 5.25 V; per Lattice datasheet, operation outside this range is not guaranteed. Decouple each VCC pin with a 0.1 uF ceramic capacitor and provide at least one 10 uF bulk capacitor near the device. ISP programming requires stable VCC during the programming cycle, so avoid large inrush loads on the same rail during programming.
Route JTAG signals (TDI, TMS, TCK, TDO) as a daisy chain from the connector to all JTAG devices on the board, with 10 kohm pull-ups on TDI/TMS/TCK to VCC. Keep JTAG traces short and away from clock signals to reduce noise. Use at least four via-stitched ground connections around the TQFP-100 footprint for thermal and EMI performance, since the 1032 dissipates roughly 1.5 W worst case.
Do not exceed 5.25 V on any pin or damage will occur to the CMOS I/O cells. When migrating to the ispMACH 4000V replacement family (LC4128V or LC4064V), confirm pinout against the Lattice migration guide - although TQFP-100 is shared, the VCC and GND pin assignments may differ slightly. Ensure unused I/O pins are left floating or driven to a defined state; do not tie them directly to VCC or GND.
Estimated: With all 64 outputs toggling at 60 MHz into 50 pF loads, the ISPLSI 1032-60LT dissipates approximately 1.5 W (CV^2 f = 64 x 50e-12 x 5^2 x 60e6 = 4.8 W theoretical, derated for typical 30% activity). The TQFP-100 has typical theta_JA of 35 C/W, so junction temperature rise above ambient is approximately 53 C; provide copper pours at low elevations and 100+ vias under the exposed pad area.
Compliance Information
RoHS/lead-free status is not confirmed in the verified web data. The ISPLSI 1032-60LT is an obsolete legacy 5 V part; Lattice datasheet mirror does not explicitly state RoHS compliance. AEC-Q100 not applicable for a 5 V industrial CPLD.
