AD9237BCPZRL7-65 - 12-Bit 65 MSPS ADC, 32-LFCSP | Analog Devices
MPN: AD9237BCPZRL7-65 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.45 | $18.45 |
| 10 | $16.62 | $166.20 |
| 100 | $14.78 | $1,478.00 |
| 500 | $13.31 | $6,655.00 |
| 1,000 | $11.83 | $11,830.00 |
| 2,500 | $10.95 | $27,375.00 |
AD9237BCPZRL7-65 Overview
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed, multi-stage switched-capacitor architecture that resolves a few bits per stage and combines them with a digital correction stage. Compared to successive-approximation register (SAR) and flash ADCs, pipelined ADCs dominate the 10-250 MSPS range because they deliver the highest sampling rate at moderate resolution (8-14 bits) while keeping die size, power, and cost low. As a member of this category, the AD9237BCPZRL7-65 sits in the broader hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor.
Key features include a flexible analog input range from 1 V p-p to 4 V p-p (differential inputs with adjustable common-mode), an output enable pin for bus multiplexing, internal voltage reference, and ultralow power dissipation scaled to speed grade (lowest at 20 MSPS, highest at 65 MSPS). The single 3 V supply and small 5x5 mm LFCSP footprint make it suited for portable and densely populated boards.
Typical applications include communications IF sampling, ultrasound imaging receive channels, portable instrumentation, and low-cost medical imaging front-ends. The output enable pin is useful when multiple ADCs share a digital bus for interleaved or multiplexed data capture.
Design tip: the analog inputs are differential - drive them with a low-impedance differential amplifier (such as an AD8138 or ADA4937) for best SFDR, and keep the input common-mode voltage at AVDD/2 to maximize input swing. Decouple AVDD and DRVDD separately with 0.1 uF and 10 uF capacitors placed within 5 mm of the supply pins.
Drop-in alternatives for AD9237BCPZRL7-65 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with AD9237BCPZRL7-65 (same form factor and footprint) — differing in Package, Architecture, Operating Temperature Range, Analog Input Type, Analog Supply Voltage (AVDD).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
AD9237BCPZ-65
✅ Drop-In✓ In Stock
$8.04 / Unit
View Datasheet →AD9237BCPZRL7-40
✅ Drop-In📋 Reference alternative (not in catalog)
AD9237BCPZRL7-20
✅ Drop-In✓ In Stock
$13.45 / Unit
View Datasheet →AD9235BCPZ-65
✅ Drop-In📋 Reference alternative (not in catalog)
AD9629BCPZRL7-65
✅ Drop-In📋 Reference alternative (not in catalog)
AD9629BCPZ-80
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AD9051BRSRL-2V
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View Datasheet →AD9051BRSRL
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View Datasheet →AD9237BCPZRL7-65 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Sample Rate | 65 MSPS |
| Architecture | Pipelined |
| Number of Channels | 1 |
| Supply Voltage (AVDD) | 3 V (2.7 V to 3.6 V) |
| Supply Voltage (DRVDD) | 3 V (2.5 V to 3.6 V) |
| Analog Input Type | Differential |
| Input Voltage Range | 1 V p-p to 4 V p-p (selectable) |
| SNR | 66 dBc to Nyquist at 65 MSPS |
| SFDR | 80 dBc to Nyquist at 65 MSPS |
| DNL | +/-0.7 LSB |
| Output Enable Pin | Yes |
| Internal Reference | Yes |
| Operating Temperature | -40C to +85C |
| Package | 32-LFCSP-WQ (5x5 mm) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
AD9237BCPZRL7-65 Pin Configuration
| Pin 1 | DRVDD — Digital output driver supply |
| Pin 2 | DGND — Digital ground |
| Pin 3 | D11 — Data output bit 11 (MSB) |
| Pin 4 | D10 — Data output bit 10 |
| Pin 5 | D9 — Data output bit 9 |
| Pin 6 | D8 — Data output bit 8 |
| Pin 7 | D7 — Data output bit 7 |
| Pin 8 | D6 — Data output bit 6 |
| Pin 9 | D5 — Data output bit 5 |
| Pin 10 | D4 — Data output bit 4 |
| Pin 11 | D3 — Data output bit 3 |
| Pin 12 | D2 — Data output bit 2 |
| Pin 13 | D1 — Data output bit 1 |
| Pin 14 | D0 — Data output bit 0 (LSB) |
| Pin 15 | OE — Output enable (active high) |
| Pin 16 | DRVDD — Digital output driver supply |
| Pin 17 | DRVDD — Digital output driver supply |
| Pin 18 | DGND — Digital ground |
| Pin 19 | CLK+ — Differential clock input (positive) |
| Pin 20 | CLK- — Differential clock input (negative) |
| Pin 21 | AVDD — Analog supply |
| Pin 22 | AGND — Analog ground |
| Pin 23 | REFT — Reference decoupling top |
| Pin 24 | REFB — Reference decoupling bottom |
| Pin 25 | AGND — Analog ground |
| Pin 26 | AVDD — Analog supply |
| Pin 27 | VCM — Common-mode voltage output |
| Pin 28 | AIN- — Differential analog input (negative) |
| Pin 29 | AIN+ — Differential analog input (positive) |
| Pin 30 | AGND — Analog ground |
| Pin 31 | AVDD — Analog supply |
| Pin 32 | SENSE — Reference mode select |
| Pin 33 | EPAD — Exposed die paddle (must be soldered to AGND for thermal dissipation) |
Typical Applications
AD9237BCPZRL7-65 is suitable for 6 applications: Communications IF Sampling, Ultrasound Imaging Receive Channel, Portable Test and Measurement Instrumentation, Low-Cost Medical Imaging Front-End, Industrial Data Acquisition Systems, Wired/Wireless Baseband Receiver.
Communications IF Sampling
The AD9237BCPZRL7-65 is widely used in communications receivers to directly sample intermediate-frequency (IF) signals up to Nyquist (about 32 MHz at 65 MSPS). Its 66 dBc SNR and 80 dBc SFDR translate into clean downconversion of narrowband channels, and the 12-bit resolution provides 72 dB of theoretical dynamic range. Driven by an AD8138 differential amplifier from a SAW-filtered IF strip, the ADC feeds digital demodulators running on an FPGA or DSP. Pin compatibility with the AD9235 means existing 3 V IF chain designs can drop in the AD9237 without PCB rework, gaining the selectable 1-4 V p-p input range that simplifies AGC design. Decoupling AVDD/DRVDD separately remains critical to keep digital switching noise out of the analog front end.
Recommended
Ultrasound Imaging Receive Channel
In portable and cart-based ultrasound systems the AD9237BCPZRL7-65 digitizes receive-beamformed RF signals at up to 65 MSPS, capturing harmonics up to 32 MHz. The 12-bit pipeline delivers 72 dB dynamic range - more than sufficient for second-harmonic imaging - while the 3 V single supply simplifies battery-powered cart designs. Low power at 65 MSPS keeps thermal budgets manageable in a sealed transducer handle. Designers typically pair the ADC with an AD8021 low-noise op-amp in the time-gain-control (TGC) stage; both run from the same 3 V rail. The 32-LFCSP-WQ 5x5 mm footprint enables compact 8- or 16-channel receiver boards.
Recommended
Portable Test and Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and data-acquisition modules use the AD9237BCPZRL7-65 to digitize signals up to 30 MHz with 12-bit resolution. The selectable input range (1-4 V p-p) lets one ADC serve both high- and low-gain front-end paths, reducing BOM. Differential analog inputs reject common-mode noise from USB chargers and battery-boost switching regulators - a common pain point in portable designs. With 66 dBc SNR and an integrated reference, the part eliminates a separate reference IC, saving board area and bill-of-materials cost in dense portable enclosures.
Recommended
Low-Cost Medical Imaging Front-End
The AD9237BCPZRL7-65 enables cost-optimized diagnostic imaging front-ends - including low-end ultrasound, optical-coherence tomography (OCT), and pulse-oximetry DSP channels - where 12-bit resolution and 65 MSPS suffice. The integrated voltage reference eliminates one external analog component, and the output enable pin allows multiple ADCs to share a parallel bus in multi-channel probes. Combined with an AD8331 variable-gain amplifier, the AD9237 captures full dynamic-range echoes without saturating. The 5x5 mm LFCSP keeps per-channel board area small, important for 32- and 64-element probes.
Recommended
Industrial Data Acquisition Systems
Multi-channel industrial DAQ modules use the AD9237BCPZRL7-65 to digitize vibration, acoustic-emission, and machine-condition signals. The 12-bit/65 MSPS capability captures rotating-equipment harmonics to several hundred kHz after aliasing into the Nyquist band, while differential inputs reject the common-mode noise ubiquitous on factory floors. The output enable pin simplifies designs where multiple ADCs are bused to an FPGA MGT/parallel interface, time-multiplexing samples. Pin compatibility with the AD9235 gives a cost-down path if 40 MSPS is later deemed sufficient.
Recommended
Wired/Wireless Baseband Receiver
Software-defined radio (SDR) baseband receivers and broadband cable-modem tuner cards use the AD9237BCPZRL7-65 to capture wideband I/Q signals. At 65 MSPS, the part delivers enough oversampling for software-defined channel filtering. Pin compatibility with the AD9235 lets module vendors reuse existing analog front ends while gaining the selectable input range and output enable feature of the AD9237. The integrated SHA eliminates the need for a dedicated track-and-hold, reducing BOM and front-end design time for SDR developers.
Recommended
Recommended Products Summary
Engineering reference data for AD9237BCPZRL7-65 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | AD9237BCPZ-65 | AD9237BCPZRL7-40 | AD9235BCPZ-65 | AD9629BCPZRL7-65 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 32-LFCSP-WQ (5x5) | 32-LFCSP-WQ (5x5) - same | 32-LFCSP-WQ (5x5) - same | 32-LFCSP-WQ (5x5) - same | 32-LFCSP-WQ (5x5) - same |
| Sample Rate | 65 MSPS | 65 MSPS | 40 MSPS | 65 MSPS | 65 MSPS |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Supply Voltage | 3 V | 3 V | 3 V | 3 V | 1.8 V |
| Output Enable Pin | Yes | Yes | Yes | No | Yes |
| Selectable Input Range | 1 V p-p to 4 V p-p | 1 V p-p to 4 V p-p | 1 V p-p to 4 V p-p | Fixed 2 V p-p | 1 V p-p to 4 V p-p |
Key Differentiators
- Selectable 1-4 V p-p input range (vs AD9235BCPZ-65)
- Output enable pin for bus multiplexing (vs AD9235BCPZ-65)
- Single 3 V supply (vs AD9629BCPZRL7-65)
Design Notes
Estimated: at 65 MSPS the AD9237BCPZRL7-65 draws roughly 100 mW from AVDD and 30 mW from DRVDD, for a total ~130 mW board dissipation. Use an LDO such as ADP3339 for each rail, decoupled with 0.1 uF + 10 uF ceramic within 5 mm of each AVDD/DRVDD pin. A ferrite bead between AVDD and DRVDD supplies prevents digital switching transients from coupling into the analog front end.
Route analog (AIN+, AIN-, VCM, REFT, REFB) and digital (D0-D11, OE, CLK+, CLK-) traces on separate layers, joining the ground return at the exposed paddle only. The exposed die paddle (EPAD) MUST be soldered to a continuous AGND copper pour to achieve rated thermal and electrical performance; a star-ground topology further improves SNR. Keep the clock trace length matched for CLK+ and CLK- to within 1 mm to preserve 50% duty cycle at the ADC sample instant.
Driving single-ended inputs into the differential AIN+/AIN- pins halves effective SNR and degrades SFDR by 10-15 dB - use a differential driver (AD8138, ADA4937) for production designs. Also, the SENSE pin must be tied to AGND for the internal reference mode (default 2 V p-p full scale) or to AVDD for an external reference; floating this pin leaves the reference in an undefined state.
Series-terminate each digital output (D0-D11) with a 33-100 ohm resistor placed within 5 mm of the ADC pin when the FPGA/ASIC receiver is more than 50 mm away. This dampens reflections on the parallel bus and prevents double-clocking in the capture register at 65 MSPS. For best SFDR, also enable spread-spectrum clocking at the FPGA or use a clock generator with low jitter (< 1 ps RMS).
Compliance Information
RoHS and lead-free per Analog Devices product page. The AD9237 is specified for -40C to +85C commercial/industrial operation; it is NOT AEC-Q100 qualified - select an automotive-grade ADC such as the ADAS1135 or similar for automotive applications.
