ADS5433IPJYG3 - 14-Bit 80 MSPS ADC, 52-Pin PQFP | Texas Instruments
MPN: ADS5433IPJYG3 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $30.85 | $3,085.00 |
| 500 | $27.4 | $13,700.00 |
| 1,000 | $24.95 | $24,950.00 |
ADS5433IPJYG3 Overview
Background Knowledge: An analog-to-digital converter (ADC) is a data-conversion integrated circuit that samples continuous-time analog signals and produces discrete digital codes, typically in parallel or serial form. The hierarchy is: ADC -> data converter -> data acquisition IC -> signal chain IC -> semiconductor. Pipelined ADCs are the workhorse of medium-to-high speed applications (10 MSPS to 250 MSPS), splitting the conversion into low-resolution stages that operate concurrently, providing an excellent trade-off between sample rate, resolution, and power. Key ADC metrics include SNR (signal-to-noise ratio), SFDR (spurious-free dynamic range), ENOB (effective number of bits), aperture delay, and INL/DNL linearity.
Key features of the ADS5433IPJYG3 include 14-bit resolution, 80 MSPS maximum sample rate, 74.4 dBc typical SNR at 30 MHz IF, 96.5 dBc typical SFDR at 30 MHz IF, and parallel CMOS outputs on a 52-pin PQFP package. The dual-supply topology (5 V analog, 3.3 V digital) allows the analog front-end to swing cleanly while the digital outputs interface directly to 3.3 V FPGAs, ASICs, or DSPs without level translation.
The pipelined core uses switched-capacitor gain stages with a proprietary calibration routine that corrects inter-stage gain and offset errors at power-up, achieving the >91 dBc SFDR guarantee without external trimming. The differential input architecture rejects common-mode noise and harmonics from upstream drivers, while the internal reference simplifies board-level design by eliminating an external reference IC. The 3.3 V CMOS output bus is double-data-rate friendly and easily captured by modern FPGAs.
Typical applications include communications receivers, radar signal processing, medical imaging front-ends, CCD digitizers, and high-speed data acquisition systems. Industrial vibration analysis and ultrasonic non-destructive testing are also common use cases that benefit from the part's wide input bandwidth and 80 MSPS throughput.
When designing with this ADC, allocate analog and digital ground regions joined at a single point near the AGND/DGND pins, and place 0.1 uF bypass capacitors within 2 mm of every supply pin. The 5 V analog supply should be sourced from a low-noise LDO; do not power the analog rail from a switching converter without significant filtering.
This page synthesizes verified distributor pricing, drop-in pin-compatible alternatives, application guidance, and PCB layout best practices that go beyond the bare datasheet specification table.
Drop-in alternatives for ADS5433IPJYG3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADS5433IPJYG3 (same form factor and footprint) — differing in Package, Input Type, Digital Output Type, Operating Temperature Range, Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADS5433IPJY
✅ Drop-In📋 Reference alternative (not in catalog)
ADS5424IPJYG3
✅ Drop-In✓ In Stock
$25.1 / Unit
View Datasheet →ADS5423MPJYEP
✅ Drop-In✓ In Stock
$52.85 / Unit
View Datasheet →ADS5422Y/1K5G4
✅ Drop-In✓ In Stock
$11.45 / Unit
View Datasheet →ADS5433IPJYG3 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Sample Rate | 80 MSPS (max) |
| Architecture | Pipelined |
| Number of Channels | 1 |
| Input Type | Differential |
| Output Type | Parallel CMOS (3.3 V) |
| Analog Supply Voltage | 5 V |
| Digital Supply Voltage | 3.3 V |
| Typical SNR (30 MHz, 80 MSPS) | 74.4 dBc |
| Typical SFDR (30 MHz, 80 MSPS) | 96.5 dBc |
| Guaranteed SFDR | 91 dBc |
| Operating Temperature Range | -40 C to +85 C |
| Package | 52-Pin PQFP (Tray) |
| Package Code | PJY |
| Terminal Pitch | 0.65 mm |
| Seated Height (max) | 1.6 mm |
| RoHS Status | Compliant |
| Reference Type | Internal |
ADS5433IPJYG3 Pin Configuration
| Pin 1 | AGND — Analog ground |
| Pin 2 | AVDD — 5 V analog supply |
| Pin 3 | AGND — Analog ground |
| Pin 4 | INA+ — Differential analog input, positive |
| Pin 5 | INA- — Differential analog input, negative |
| Pin 6 | AGND — Analog ground |
| Pin 7 | AGND — Analog ground |
| Pin 8 | AVDD — 5 V analog supply |
| Pin 9 | VREF — Internal reference voltage |
| Pin 10 | AGND — Analog ground |
| Pin 11 | AGND — Analog ground |
| Pin 12 | AVDD — 5 V analog supply |
| Pin 13 | AGND — Analog ground |
| Pin 14 | CLK — Sample clock input |
| Pin 15 | CLK — Complementary sample clock input |
| Pin 16 | AGND — Analog ground |
| Pin 17 | AGND — Analog ground |
| Pin 18 | AVDD — 5 V analog supply |
| Pin 19 | DRVDD — 3.3 V digital output supply |
| Pin 20 | DRGND — Digital ground |
| Pin 21 | D0 — Digital output bit 0 (LSB) |
| Pin 22 | D1 — Digital output bit 1 |
| Pin 23 | D2 — Digital output bit 2 |
| Pin 24 | D3 — Digital output bit 3 |
| Pin 25 | D4 — Digital output bit 4 |
| Pin 26 | D5 — Digital output bit 5 |
| Pin 27 | D6 — Digital output bit 6 |
| Pin 28 | D7 — Digital output bit 7 |
| Pin 29 | D8 — Digital output bit 8 |
| Pin 30 | D9 — Digital output bit 9 |
| Pin 31 | D10 — Digital output bit 10 |
| Pin 32 | D11 — Digital output bit 11 |
| Pin 33 | D12 — Digital output bit 12 |
| Pin 34 | D13 — Digital output bit 13 (MSB) |
| Pin 35 | DRGND — Digital ground |
| Pin 36 | DRVDD — 3.3 V digital output supply |
| Pin 37 | DRGND — Digital ground |
| Pin 38 | DRVDD — 3.3 V digital output supply |
| Pin 39 | DRGND — Digital ground |
| Pin 40 | NC — Not connected (per datasheet) |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | DRGND — Digital ground |
| Pin 43 | DRVDD — 3.3 V digital output supply |
| Pin 44 | DRGND — Digital ground |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | NC — Not connected (per datasheet) |
| Pin 47 | AVDD — 5 V analog supply |
| Pin 48 | AGND — Analog ground |
| Pin 49 | AGND — Analog ground |
| Pin 50 | AVDD — 5 V analog supply |
| Pin 51 | AGND — Analog ground |
| Pin 52 | AVDD — 5 V analog supply |
Typical Applications
ADS5433IPJYG3 is suitable for 6 applications: Communications Receiver IF Sampling, Radar Pulse-Doppler Signal Processing, Medical Ultrasound Beamforming, CCD / CMOS Image Sensor Digitization, Industrial Vibration & Acoustic Analysis, High-Speed Data Acquisition Card.
Communications Receiver IF Sampling
The ADS5433IPJYG3's 80 MSPS sample rate and 74.4 dBc typical SNR allow clean digitization of IF signals in the 10-40 MHz range commonly used in cellular base-station and software-defined-radio receivers. Placing the ADC after the final IF mixer preserves signal integrity; the 3.3 V CMOS outputs feed directly into an FPGA demodulator without level translation. The 91 dBc minimum SFDR keeps intermodulation spurs well below the noise floor, supporting 256-QAM and higher-order modulation.
Recommended
Radar Pulse-Doppler Signal Processing
Radar receivers require ADCs with wide dynamic range and clean spurious response; the ADS5433IPJYG3 delivers 96.5 dBc typical SFDR at 30 MHz, ensuring pulse-Doppler returns are digitized without spurs obscuring low-RCS targets. The differential input rejects common-mode noise from the RF front-end, and the 80 MSPS rate captures the full IF bandwidth of typical surveillance radar. Use this ADC in the IF strip just before the FPGA-based pulse compressor and Doppler processor.
Recommended
Medical Ultrasound Beamforming
Medical ultrasound arrays demand per-channel ADCs with at least 12 effective bits and 40+ MSPS; the ADS5433IPJYG3's 74.4 dBc SNR (about 12 ENOB) and 80 MSPS throughput fit mid-range cart-based ultrasound systems. Its low spurious content preserves the dynamic range needed to visualize small cysts and tissue boundaries, while the CMOS outputs stream data into an FPGA for beamforming and image reconstruction. The 52-pin PQFP package is straightforward to lay out under a multi-channel board.
Recommended
CCD / CMOS Image Sensor Digitization
Scientific CCD and high-resolution CMOS imagers generate video-rate analog signals that need clean, low-noise digitization. The ADS5433IPJYG3's differential input accepts the typical +/-1 V swing from a correlated double-sampling amplifier, and its 14-bit resolution captures the full dynamic range of cooled astronomy CCDs. The 80 MSPS throughput easily handles multi-megapixel sensors running at standard video rates.
Recommended
Industrial Vibration & Acoustic Analysis
Vibration monitoring of motors, bearings, and acoustic emission testing require ADCs that capture transients without ringing or excessive aliasing. The ADS5433IPJYG3's 80 MSPS bandwidth lets engineers sample 30+ kHz mechanical resonances well above the Nyquist limit, while the 14-bit resolution reveals subtle harmonics. The PQFP package and industrial -40 C to +85 C temperature range handle factory-floor environments.
Recommended
High-Speed Data Acquisition Card
PCIe-based data acquisition cards for laboratory instruments benefit from the ADS5433IPJYG3's high sample rate and CMOS parallel outputs that interface directly to an FPGA FIFO. The 74.4 dBc SNR ensures that digitized waveforms are representative of the true input, and the 91 dBc SFDR prevents spurs from masquerading as signal features. The 52-pin PQFP package lays out cleanly next to DDR memory and a PCIe bridge ASIC.
Recommended
Recommended Products Summary
Engineering reference data for ADS5433IPJYG3 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS5433IPJY | ADS5424IPJYG3 | ADS5423MPJYEP | ADS5422Y/1K5G4 |
|---|---|---|---|---|---|
| Package | 52-pin PQFP (PJY) | 52-pin PQFP (PJY) - same | 52-pin PQFP (PJY) - same | 52-pin PQFP (PJY) - same | 52-pin PQFP (PJY) - same |
| Brand | Texas Instruments | Texas Instruments - same | Texas Instruments - same | Texas Instruments - same | Texas Instruments - same |
| Resolution | 14 bit | 14 bit | 14 bit | 12 bit | 12 bit |
| Sample Rate (max) | 80 MSPS | 80 MSPS | 40 MSPS | 40 MSPS | 40 MSPS |
| Analog Supply | 5 V | 5 V | 5 V | 5 V | 5 V |
| Digital Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Input Type | Differential | Differential | Differential | Differential | Differential |
| Output Type | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -55 C to +125 C (EP) | -40 C to +85 C |
Key Differentiators
- Highest sample rate in the ADS542x/ADS543x 52-pin PQFP family (vs ADS5424IPJYG3)
- Two extra bits of resolution over 12-bit family members (vs ADS5423MPJYEP)
- Industrial temperature range compatible with most outdoor and factory environments (vs ADS5423MPJYEP)
Design Notes
The ADS5433IPJYG3 uses separate 5 V (AVDD) and 3.3 V (DRVDD) supply rails. Place a ferrite bead in series with each supply and a 10 uF tantalum + 0.1 uF ceramic decoupling pair within 2 mm of every supply pin. Source the 5 V analog rail from a low-noise LDO such as the TPS7A4701 rather than a switching converter; noise on AVDD directly degrades SNR and SFDR.
Split the PCB into an analog section (left/under the ADC analog pins) and a digital section (right/under the CMOS outputs), joined at a single ground bridge directly under the IC's exposed pad or analog/digital ground pins. The differential clock traces (CLK, CLK-bar) must be length-matched and routed as a 100-ohm differential pair; jitter on the clock directly degrades aperture uncertainty and SNR.
Route the 14 CMOS output bits as a bus with matched lengths (within 2 mm) and add 33 ohm series-termination resistors near the driver pins to dampen reflections into the 50-65 ohm FPGA traces. Keep the digital bus at least 5 mm away from the analog INA+/INA- traces to avoid digital switching noise coupling into the analog input and corrupting SFDR.
Do not power DRVDD with a 5 V supply - the parallel CMOS outputs are 3.3 V-rated and will drive excessive voltage into 3.3 V FPGAs. Do not float the unused NC pins; if the datasheet specifies a tie, follow it. The differential input must be DC-biased near the common-mode voltage (typically 2.5 V) using a transformer or driver-amplifier network - leaving the inputs floating results in saturated output codes.
Compliance Information
RoHS-compliant PQFP package per the G3 suffix designation. Not AEC-Q100 qualified - choose ADS5423MPJYEP for automotive-grade requirements.
