ATSAMA5D27C-CN - 500MHz ARM Cortex-A5 MPU | Microchip
MPN: ATSAMA5D27C-CN ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.92 | $18.92 |
| 10 | $17.05 | $170.50 |
| 100 | $14.62 | $1,462.00 |
| 500 | $13.1 | $6,550.00 |
| 1,000 | $11.78 | $11,780.00 |
ATSAMA5D27C-CN Overview
An ARM Cortex-A5 microprocessor is the central processing unit of an embedded system, executing 32-bit instruction sets at frequencies typically below 1 GHz and serving a different role than microcontrollers (MCUs). Cortex-A5 cores run full operating systems such as Linux, running in the MPU -> embedded microprocessor -> application processor -> SoC taxonomy, and require external DDR memory plus a sophisticated power management tree. The SAMA5D2 family targets industrial-grade HMI, gateways, and IoT edge nodes where deterministic real-time behavior and Linux application flexibility must coexist with low standby power.
Key features include support for DDR2, DDR3, LPDDR1, LPDDR2, LPDDR3, and QSPI Flash memories; one Gigabit Ethernet MAC with IEEE 1588 hardware timestamp support; one 10/100 Ethernet MAC; USB 2.0 High-Speed host and device ports; up to two CAN-FD interfaces; multiple SDMMC, SPI, TWI, and UART peripherals; a 12-bit ADC; and a 24-bit parallel LCD controller. The on-chip cryptographic accelerator delivers AES at line rate, and the secure-boot chain anchors TrustZone-protected firmware verification. The device operates from a single 1.2 V core supply with separate I/O and DDR rails.
Architecturally, the SAMA5D27C-CN combines the Cortex-A5 core with a multi-layer AHB/AXI fabric, dedicated peripheral DMA channels, and a low-power backup domain containing a 32 kHz real-time clock and tamper pins. The hardware crypto block executes AES-256, SHA-1/SHA-256, and true random number generation autonomously without CPU involvement, offloading security tasks from the application layer. This SoC integration allows engineers to build a complete Linux-capable product with a minimal external bill of materials.
Typical applications include industrial human-machine interfaces (HMIs) with capacitive touch and TFT LCD, building automation gateways, smart energy metering and substation controllers, IoT edge nodes running Linux, medical device controllers, and point-of-sale terminals. The 289-LFBGA package enables compact board layouts while supporting wide memory bandwidth.
Designers should pay close attention to PCB layout: the 0.8 mm BGA pitch requires laser-via or microvia PCB technology, and the DDR interface needs matched-length routing and reference-voltage decoupling. For Linux bring-up, use Microchip's AT91Bootstrap loader and the provided Device Tree sources to initialize clocks, DDR timing, and peripheral muxing before the kernel takes control.
This page synthesizes distributor pricing, SAMA5D2 family alternatives, peripheral set details, and practical hardware-layout guidance not found in the standalone datasheet, giving procurement and engineering teams a unified reference.
Drop-in alternatives for ATSAMA5D27C-CN — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ATSAMA5D27C-CN (same form factor and footprint) — differing in External Memory Support, CAN, Ethernet, Package, Backup Mode Current.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ATSAMA5D27B-CU
✅ Drop-In✓ In Stock
$11.85 / Unit
View Datasheet →ATSAMA5D27B-CUR
✅ Drop-In✓ In Stock
$11.85 / Unit
View Datasheet →ATSAMA5D27A-CN
✅ Drop-In✓ In Stock
$20.5 / Unit
View Datasheet →ATSAMA5D27A-CU
✅ Drop-In✓ In Stock
$7.83 / Unit
View Datasheet →ATSAMA5D27A-CNR
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →ATSAMA5D27C-CU
✅ Drop-In✓ In Stock
$11.9 / Unit
View Datasheet →ATSAMA5D27C-D1G
✅ Drop-In📋 Reference alternative (not in catalog)
ATSAMA5D27C-CN Maximum Ratings & Electrical Characteristics
| Processor Core | ARM Cortex-A5 (32-bit) |
| Maximum CPU Clock | 500 MHz |
| Number of Cores | 1 |
| On-chip SRAM | 128 KB |
| Instruction Set Architecture | ARMv7-A with TrustZone |
| External Memory Support | DDR2, DDR3, LPDDR1, LPDDR2, LPDDR3, QSPI Flash, e.MMC |
| Package | 289-LFBGA (14x14 mm, 0.8 mm pitch) |
| Supply Voltage (Core) | 1.2 V typical |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature Range | -40 C to +85 C (industrial) |
| Ethernet | 1x Gigabit MAC + 1x 10/100 MAC (IEEE 1588 supported) |
| USB | USB 2.0 High-Speed Host and Device |
| CAN | Up to 2x CAN-FD controllers |
| Display Controller | 24-bit parallel LCD, up to XGA |
| Hardware Cryptography | AES, SHA-1/SHA-256, TRNG, secure boot |
| RoHS Status | Compliant |
ATSAMA5D27C-CN 289-lfbga (14x14 mm, 0.8 mm pitch) Pin Configuration Guide
Pin configuration for ATSAMA5D27C-CN (289-lfbga (14x14 mm, 0.8 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for ATSAMA5D27C-CN.
Refer to the datasheet for full pin configuration.
Typical Applications
ATSAMA5D27C-CN is suitable for 6 applications: Industrial Human-Machine Interface (HMI), Building Automation Gateway, Edge IoT Sensor Hub, Medical Device Controller, Smart Energy Substation Controller, Point-of-Sale (POS) Terminal.
Industrial Human-Machine Interface (HMI)
The ATSAMA5D27C-CN is well suited for industrial HMI panels because it combines a 500 MHz Cortex-A5 application core for Linux/Qt or Web rendering with a built-in 24-bit parallel LCD controller that drives XGA-resolution TFT displays directly, eliminating an external graphics chip. Hardware-accelerated AES/SHA offloads secure boot and signed firmware updates, which is mandatory for IEC 62443 industrial security compliance. Dual Ethernet MACs with IEEE 1588 hardware timestamping enable deterministic PROFINET or EtherCAT bridging. Reference designs are available on Microchip's SAMA5D2 platform page and pair with PIC32 microcontrollers for safety-critical I/O.
Recommended
Building Automation Gateway
Smart-building gateways need a low-power Linux host with dual Ethernet for network segmentation, and the ATSAMA5D27C-CN delivers exactly that - one Gigabit MAC for upstream IP and one 10/100 MAC for the fieldbus side. The hardware crypto engine handles TLS 1.3 and BACnet secure session keys without loading the CPU, leaving headroom for protocol translation between BACnet, Modbus TCP, and KNX. CAN-FD is available for direct HVAC controller attach. The 289-LFBGA package fits into slim DIN-rail enclosures, and the industrial -40 C to +85 C temperature grade supports unheated equipment rooms.
Recommended
Edge IoT Sensor Hub
Edge IoT hubs aggregate Modbus, CAN, and analog sensor data and forward it over Ethernet or cellular to the cloud, and the ATSAMA5D27C-CN's dual Ethernet plus CAN-FD plus 12-bit ADC allow direct connection to industrial sensor buses without external glue logic. The 128 KB on-chip SRAM and DDR controller let designers run lightweight edge-analytics on Linux without an external MPU companion. Hardware TRNG and secure boot protect against physical tamper attacks in unattended cabinets. Pairing with a sub-1 GHz or LoRa transceiver board turns the design into an LPWAN aggregator.
Recommended
Medical Device Controller
Patient-monitoring and diagnostic-assist devices need a deterministic Linux host with strong security, and the ATSAMA5D27C-CN meets that requirement with the Cortex-A5 core, hardware crypto, and TrustZone-protected secure island. The integrated LCD controller drives bedside displays directly, while the parallel camera interface can attach a small CMOS image sensor for disposable diagnostic tools. USB 2.0 High-Speed device mode simplifies tethered firmware update by clinicians. Medical OEMs should verify IEC 60601-1 system-level compliance at the device level rather than relying on any single IC's certification.
Recommended
Smart Energy Substation Controller
Substation controllers for IEC 61850-compliant distribution equipment run Linux on a deterministic platform with redundant Ethernet, and the ATSAMA5D27C-CN fits with its dual Ethernet MACs, hardware 1588 timestamping, and industrial -40 C to +85 C temperature grade. The crypto accelerator handles secure DNP3 and IEC 62351-3 session keys without CPU loading. CAN-FD bridges to downstream IEDs and battery chargers. The unit is not AEC-Q100 qualified, so for utility substation outdoor cabinets the engineer should pair the MPU with a separate watchdog and conformal coating at the board level.
Recommended
Point-of-Sale (POS) Terminal
POS terminals require secure transaction processing, Ethernet or Wi-Fi backhaul, and a touchscreen LCD, all of which the ATSAMA5D27C-CN provides on a single chip. The hardware crypto engine accelerates PCI PTS POI transaction cryptography, and the secure-boot chain authenticates firmware on every power-up, helping OEMs meet the PCI PTS 6.x modular evaluation requirements. The 24-bit LCD controller drives the merchant-facing display, while USB 2.0 High-Speed connects to PIN pads and printers. DDR3L or LPDDR2 external memory is typically chosen to balance cost and standby power.
Recommended
Recommended Products Summary
Engineering reference data for ATSAMA5D27C-CN — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ATSAMA5D27B-CU | ATSAMA5D27A-CN | ATSAMA5D27C-CU | ATSAMA5D27C-D1G |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 289-LFBGA (14x14, 0.8 mm) | 289-LFBGA (14x14) - same | 289-LFBGA (14x14) - same | 289-LFBGA (14x14) - same | 289-LFBGA (14x14) - same |
| CPU Core | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz | ARM Cortex-A5 500 MHz |
| Silicon Revision | Revision C | Revision B (earlier errata) | Revision A (earliest) | Revision C (identical) | Revision C + integrated LPDDR2 |
| Operating Temperature | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) |
| On-chip SRAM | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
| External Memory | DDR2/3, LPDDR1/2/3, QSPI | DDR2/3, LPDDR1/2/3, QSPI | DDR2/3, LPDDR1/2/3, QSPI | DDR2/3, LPDDR1/2/3, QSPI | Integrated 1 Gbit LPDDR2 |
| Hardware Crypto Engine | AES, SHA, TRNG | AES, SHA, TRNG | AES, SHA, TRNG | AES, SHA, TRNG | AES, SHA, TRNG |
| Ethernet | 1x GbE + 1x 10/100 (IEEE 1588) | 1x GbE + 1x 10/100 (IEEE 1588) | 1x GbE + 1x 10/100 (IEEE 1588) | 1x GbE + 1x 10/100 (IEEE 1588) | 1x GbE + 1x 10/100 (IEEE 1588) |
Key Differentiators
- Newest silicon revision with tightened DDR timing margins (vs ATSAMA5D27A-CN)
- Lower-cost commercial-temperature variant available (vs ATSAMA5D27C-CU)
- Integrated LPDDR2 option for compact designs (vs ATSAMA5D27C-D1G)
Design Notes
The ATSAMA5D27C-CN uses a 0.8 mm-pitch 289-LFBGA package that requires laser-via or microvia HDI PCB stackup. Place the DDR3 chips on the same layer as the MPU ball grid if possible, or use short via-in-pad escape routes. Stitch the inner ground planes with a via fence around the BGA outline to control return currents; reference-vias must be placed within 1 ball pitch of every VDD/VSS pair.
Power the ATSAMA5D27C-CN from a 1.2 V core LDO or DC-DC converter rated for at least 1 A transient load, with separate rails for VDDI/O (1.8 V or 3.3 V) and the DDR reference voltage (typically 0.675 V for DDR3L, 1.2 V for LPDDR2). Bulk-decouple each rail with 22 uF ceramic plus 0.1 uF X7R near every power pin pair, and use Microchip's recommended Power Management IC (MIC2800 or equivalent) sequencing to bring rails up in the correct order. Estimated rail current at 500 MHz core speed with peripherals active is roughly 200 mA on VDDCORE plus 100 mA on VDDI/O.
Always program the SAMA5D27C-CN secure-boot fuses before deploying a unit in the field, otherwise an attacker can reflash unsigned firmware. Verify that the LFBGA package has not exceeded its MSL floor-life; reflow outside the JEDEC J-STD-033 profile can cause solder-ball voids. When migrating an existing Linux BSP from revision B silicon, revalidate DDR3L timing because revision C tightened some setup/hold windows.
The DDR3/LPDDR2 interface on the ATSAMA5D27C-CN requires matched-length routing on byte groups with a tolerance of roughly 25 mil (0.6 mm) and impedance of 50 ohm single-ended. Use fly-by topology for the DDR clocks and avoid T branches - signal integrity degrades rapidly above 500 MHz. Series-stamp 33 ohm resistors on the DDR control signals close to the MPU balls if signal-integrity simulations show ringing. Do not share ground-reference planes between the DDR region and noisy switcher node.
Compliance Information
RoHS and lead-free status confirmed via Microchip environmental data sheet and DigiKey product page. AEC-Q100 not applicable in the industrial MPU product line - consult Microchip for SAMA5 automotive equivalents. Halogen-free status not explicitly published; refer to Microchip material declaration for lot-specific confirmation.