CD74HCT165M96 - 8-Bit Parallel-In/Serial-Out Shift Register | TI
MPN: CD74HCT165M96 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.41 | $0.41 |
| 10 | $0.36 | $3.60 |
| 100 | $0.27 | $27.00 |
| 500 | $0.22 | $110.00 |
| 1,000 | $0.18 | $180.00 |
CD74HCT165M96 Overview
What is a parallel-in/serial-out shift register? A shift register is a sequential logic block that stores and shifts multi-bit data along a chain of flip-flops on each clock edge. A parallel-in/serial-out (PISO) variant accepts 8 bits in parallel, then clocks them out one bit at a time over a serial line. Within the broader IC taxonomy, PISO registers sit under the Logic IC family -> Shift Registers -> PISO registers, and they are the building block of which microcontroller peripherals (UART, SPI) are typically constructed. PISO devices are used to reduce the I/O count on a host MCU by converting parallel button or sensor data into a single-wire serial stream.
The CD74HCT165M96 features buffered inputs, complementary Q7/Q7-bar outputs, asynchronous parallel load, and a wide fanout of 10 LSTTL loads on standard outputs and 15 LSTTL loads on bus-driver outputs. The asynchronous load (active-low PL) lets the system load parallel data without waiting for a clock edge, which is critical when capturing fast events. Complementary outputs enable easy wire-OR or polarity-inversion without an external inverter.
Architecturally, the CD74HCT165 uses HCT-CMOS silicon gates, which deliver CMOS-style low static power (typically microampere quiescent supply current) while presenting TTL-compatible input thresholds (VIL = 0.8 V, VIH = 2.0 V). The serial data path is implemented as 8 master-slave D flip-flops clocked by the rising edge of the CLK input, with the DS serial data input multiplexed through the PL-controlled input gate. The HCT family operates from a single 4.5 V to 5.5 V supply.
Typical applications include scanning a matrix of front-panel push-button switches, multiplexing 8 lines of digital sensor data into a single microcontroller UART, expanding GPIO on low-pin-count MCUs, industrial control front-ends, and keyboard/mouse matrix scanners. In each case the part reduces host-side pin count and PCB routing complexity by converting parallel inputs to a single serial bit stream.
When designing with this device, keep trace lengths short between parallel data sources and the D0-D7 inputs to minimize skew, and route the CLK and PL signals with a ground return to avoid transient capture errors. Power-supply decoupling of 0.1 uF next to VCC is recommended for noise-sensitive designs.
This page synthesizes distributor stock, datasheet pinout, parametric drop-in alternatives, and PCB design notes not found in the manufacturer datasheet alone, giving procurement and engineering teams a single source for sourcing and replacement decisions.
Drop-in alternatives for CD74HCT165M96 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
CD74HCT165M96E4
✅ Drop-In📋 Reference alternative (not in catalog)
CD74HCT165M
✅ Drop-In📋 Reference alternative (not in catalog)
CD74HCT165ME4
✅ Drop-In📋 Reference alternative (not in catalog)
SN74HCT165DR
✅ Drop-In📋 Reference alternative (not in catalog)
74HCT165D
✅ Drop-In📋 Reference alternative (not in catalog)
MC74HCT165ADR
✅ Drop-In📋 Reference alternative (not in catalog)
CD74HCT165M96 Maximum Ratings & Electrical Characteristics
| Function | Shift Register (Parallel-In/Serial-Out) |
| Logic Family | HCT (High-Speed CMOS, TTL-compatible inputs) |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Output Type | Complementary (Q7 and Q7-bar) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V |
| Input Type | Buffered |
| Operating Temperature | -55 C to +125 C |
| Package | 16-pin SOIC (D) |
| Mounting Type | Surface Mount |
| Output Current (Standard) | Fanout 10 LSTTL loads |
| Output Current (Bus Driver) | Fanout 15 LSTTL loads |
| Parallel Load (PL) | Asynchronous, active-low |
| Package Height | 1.5 mm (max) |
| Package Width | 3.9 mm |
| Package Length | 9.9 mm |
| RoHS Status | Compliant |
CD74HCT165M96 Pin Configuration
| Pin 1 | PL — Parallel Load (active-low asynchronous load) |
| Pin 2 | CLK — Serial Shift Clock (rising-edge triggered) |
| Pin 3 | CLK INH — Clock Inhibit (HIGH disables shift clock) |
| Pin 4 | SER — Serial Data Input (DS) |
| Pin 5 | GND — Ground |
| Pin 6 | D0 — Parallel Data Input 0 |
| Pin 7 | D1 — Parallel Data Input 1 |
| Pin 8 | D2 — Parallel Data Input 2 |
| Pin 9 | Q7 — Serial Data Output from last stage |
| Pin 10 | D3 — Parallel Data Input 3 |
| Pin 11 | D4 — Parallel Data Input 4 |
| Pin 12 | D5 — Parallel Data Input 5 |
| Pin 13 | Q7-bar — Complementary Serial Data Output |
| Pin 14 | D6 — Parallel Data Input 6 |
| Pin 15 | D7 — Parallel Data Input 7 |
| Pin 16 | VCC — Supply Voltage (4.5 V to 5.5 V) |
Typical Applications
CD74HCT165M96 is suitable for 6 applications: Front-Panel Switch Matrix Scanner, GPIO Expander for Low-Pin-Count MCUs, Industrial Sensor Multiplexing, Keyboard and Keypad Matrix Interface, Digital Data Acquisition Front-End, Automotive Body Control Modules.
Front-Panel Switch Matrix Scanner
The CD74HCT165M96 reduces an 8x N matrix of push-button or DIP switches into a single MCU-friendly serial stream. With 8-bit parallel load via the asynchronous PL pin and complementary Q7/Q7-bar outputs, it captures button events without latency and shifts them out over a single GPIO pin, freeing MCU pins for other functions. Placed between the switch matrix and the host UART/SPI peripheral, the HCT 5V TTL-compatible inputs interface cleanly with bipolar switch debounce circuits. Compared with discrete shift-register chains, the integrated buffered inputs and 10/15 LSTTL fanout eliminate external pull-ups and reduce BOM count in industrial HMIs and front-panel control boards.
Recommended
GPIO Expander for Low-Pin-Count MCUs
The CD74HCT165M96 adds 8 parallel inputs to a small MCU that has too few GPIOs for sensor reading, requiring only 3 MCU pins (PL, CLK, Q7) to access all 8 inputs. The asynchronous parallel load captures data in a single CPU cycle, while the serial shift clocked by the host MCU avoids any external oscillator. HCT input thresholds (VIL 0.8 V, VIH 2.0 V) ensure direct 5V CMOS sensor compatibility, and the -55C to +125C operating range supports industrial and outdoor deployments. Designers often chain two CD74HCT165s to get 16 inputs over the same 3-wire interface.
Recommended
Industrial Sensor Multiplexing
The CD74HCT165M96 multiplexes 8 lines of digital sensor data (limit switches, photoelectric sensors, proximity detectors) into a single industrial UART or RS-485 link, drastically reducing cable and connector cost. The -55C to +125C operating temperature handles factory-floor and outdoor cabinet environments, and the HCT sub-family's TTL-compatible inputs interface directly with 5V industrial sensor outputs. Asynchronous parallel load lets an interrupt service routine capture all 8 sensor states in a single cycle, while the high fanout (10/15 LSTTL) allows the register to drive long industrial bus lines without buffering.
Recommended
Keyboard and Keypad Matrix Interface
The CD74HCT165M96 reads an 8-row keyboard matrix by scanning each row's switch closures in parallel and clocking the result out to the host MCU over one wire. With 8-bit parallel load via PL and complementary Q7/Q7-bar outputs, both open-collector and totem-pole row scan signals can be handled. The HCT TTL-compatible inputs work with 5V scanned-row drivers, and the wide -55C to +125C range supports ruggedized human-machine interface panels. Compared with charlieplexing or diode-matrix decoding, this approach is simpler and cheaper.
Recommended
Digital Data Acquisition Front-End
The CD74HCT165M96 captures parallel digital data from parallel-output ADCs, frequency counters, or parallel data buses and serializes them for a single SPI or UART link to a host processor. The asynchronous PL pin performs single-cycle parallel acquisition, while the CLK-driven serial output maintains deterministic timing aligned to the host's sample clock. The 5V HCT logic directly interfaces with legacy 5V parallel ADCs and data-acquisition ASICs without level shifters, and the -55C to +125C operating range handles laboratory and field-instrument environments.
Recommended
Automotive Body Control Modules
The CD74HCT165M96 reads 8 parallel switch inputs (door locks, window position, mirror selectors) in body control modules and serializes them to the BCM host MCU. While not AEC-Q100 qualified itself, the part operates over -55C to +125C and at 5V supply, matching the BCM environment; alternatively, the SN74HCT165DR variant offers closer AEC-Q100 automotive pedigree. According to the TI datasheet, asynchronous parallel load lets the BCM capture switch state in microseconds, critical for window anti-pinch and door-ajar detection.
Recommended
Recommended Products Summary
Engineering reference data for CD74HCT165M96 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | CD74HCT165M96E4 | CD74HCT165M | SN74HCT165DR | 74HCT165D | MC74HCT165ADR |
|---|---|---|---|---|---|---|
| Package | 16-SOIC (D) | 16-SOIC - same | 16-SOIC - same | 16-SOIC - same | 16-SOIC - same | 16-SOIC - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Nexperia | onsemi |
| Logic Family | HCT | HCT | HCT | HCT | HCT | HCT |
| Operating Temperature | -55 C to +125 C | -55 C to +125 C | -55 C to +125 C | -40 C to +85 C | -40 C to +125 C | -55 C to +125 C |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Parallel Load | Asynchronous, active-low | Asynchronous, active-low | Asynchronous, active-low | Asynchronous, active-low | Asynchronous, active-low | Asynchronous, active-low |
| Output Type | Complementary Q7 / Q7-bar | Complementary Q7 / Q7-bar | Complementary Q7 / Q7-bar | Complementary Q7 / Q7-bar | Complementary Q7 / Q7-bar | Complementary Q7 / Q7-bar |
Key Differentiators
- Wide military-grade operating temperature range (vs SN74HCT165DR)
- Asynchronous parallel load with no latency (vs CD74HCT595 (SIPO variant))
- Complementary Q7/Q7-bar outputs eliminate external inverters (vs 74HCT165D (Nexperia))
Design Notes
Place a 0.1 uF ceramic decoupling capacitor between VCC (pin 16) and GND (pin 5) within 5 mm of the package, with a ground via directly at pin 5. For multi-register chains, add a 10 uF bulk tantalum or ceramic capacitor at the chain's VCC entry. Per the TI datasheet, the HCT sub-family has low static current draw but can inject switching transients on VCC that couple into adjacent analog stages if the decoupling is poor.
Keep parallel data traces D0-D7 length-matched to within 5 mm to avoid capture skew on rising CLK edges. Route CLK and PL traces over a continuous ground return path to prevent transient capture errors. Series-terminate the Q7 output with a 33-47 ohm resistor when driving traces longer than 50 mm, especially in noisy industrial environments. According to TI datasheet guidance, the asynchronous PL feature can capture data within 30 ns of assertion, but slow PL edges can cause metastability - keep PL rise/fall times under 100 ns.
Do not leave the CLK INH (pin 3) floating - tie it to GND to enable the shift clock. Do not exceed VCC of 5.5 V; the HCT sub-family does NOT support 6 V operation (use CD74HC165 for 6 V tolerance). The complementary Q7-bar output (pin 13) is internally driven; never tie it to VCC or GND directly. For cascaded designs, the Q7 output of the upstream register must feed the SER (pin 4) of the downstream register, and the Q7-bar output should be left unconnected unless used for polarity inversion. Estimate from TI datasheet: at 5 V and 25 C, quiescent supply current is approximately 4 uA per device, so 16 cascaded devices draw ~64 uA total quiescent current.
Place the CD74HCT165M96 close to the host MCU's GPIO pins to minimize serial-clock trace length and reduce EMI. For switch-matrix scanning, add 100 kohm pull-down resistors on D0-D7 if the switch matrix does not actively drive them low in the open state. Provide a guard ground trace between the parallel data bus (D0-D7) and the serial outputs (Q7, Q7-bar) to prevent switching transients from coupling back into the next acquisition. Per the TI datasheet, output transition times are typically 8-15 ns at 5 V/25 pF load.
Compliance Information
RoHS and REACH compliant per TI product page. The CD74HCT165M96 is NOT AEC-Q100 qualified; for automotive applications use SN74HCT165DR-Q1 or SN74HCT165QDRQ1. Lead-free (Pb-free) finish confirmed by the M96E4 suffix variant.
