CP80C88-2Z - 80C88 8MHz CMOS CPU 40-PDIP | Renesas/Intersil
MPN: CP80C88-2Z β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $49.51 | $49.51 |
| 10 | $47.03 | $470.30 |
| 100 | $44.56 | $4,456.00 |
| 500 | $42.09 | $21,045.00 |
| 1,000 | $39.61 | $39,610.00 |
CP80C88-2Z Overview
A microprocessor (MPU) is the central processing unit of a computer system: it fetches instructions from memory, decodes them, and executes arithmetic, logic, and I/O operations. The 80C88 sits within the x86 processor hierarchy (8086 -> 8088 -> 80C88 -> 80186/80286), making it software-compatible with the vast ecosystem of 8086/8088 code, BIOS implementations, and peripherals such as the 8284 clock generator and 8288 bus controller.
Key features of the CP80C88-2Z include an 8 MHz maximum clock frequency, a multiplexed 8-bit external data bus with a 16-bit internal architecture, a 20-bit address bus addressing up to 1 MB of memory, and two operating modes: MINimum mode for small single-processor systems and MAXimum mode for larger multiprocessor applications. CMOS fabrication (self-aligned silicon gate, scaled SAJI IV process) gives it far lower static and dynamic power draw than the original NMOS 8088.
Technically, the device uses a prefetch queue and bus interface unit separated from the execution unit, allowing instruction fetch and execution to overlap. The 2 suffix denotes the 8 MHz speed grade, and the Z suffix denotes lead-free, RoHS-compliant construction. Compatible support chips (8284A, 8288, 8259A, 8237A) allow a full board-level system design.
Typical applications include legacy industrial control systems, embedded x86 single-board computers, avionics and test-equipment maintenance, and educational/retro-computing platforms that require authentic 8088 bus timing.
Design consideration: use the 8284A clock generator for a properly phased CLK signal, and ensure READY-based wait states for slow EPROM/EEPROM memories; do not exceed the 5 V +/-10% supply range.
This page synthesizes distributor pricing, drop-in alternatives, pinout data, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for CP80C88-2Z β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
CP80C88-2
β Drop-Inπ Reference alternative (not in catalog)
CP80C88Z
β Drop-Inπ Reference alternative (not in catalog)
CP80C88-B
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
D80C88-2
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
P8088-2
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
CP80C88-2Z Maximum Ratings & Electrical Characteristics
| Core | 80C88 |
| Architecture | 8-bit external / 16-bit internal |
| Number of Cores | 1 |
| Maximum Clock Frequency | 8 MHz |
| Operating Supply Voltage | 5 V |
| Data Bus Width | 8 bit / 16 bit |
| Address Bus Width | 20 bit (1 MB address space) |
| Process Technology | CMOS (self-aligned silicon gate, scaled SAJI IV) |
| Operating Modes | MINimum and MAXimum mode |
| Minimum Operating Temperature | 0 C |
| Maximum Operating Temperature | +70 C |
| Package | 40-PDIP (0.600 in, 15.24 mm) |
| Mounting Style | Through Hole |
| I/O Voltage | 5 V |
| Product Type | Microprocessors - MPU |
| RoHS Status | RoHS Compliant |
| Lead Free Status | Lead Free |
CP80C88-2Z Pin Configuration
| Pin 1 | GND β Ground |
| Pin 2 | A14 β Address bus bit 14 |
| Pin 3 | A13 β Address bus bit 13 |
| Pin 4 | A12 β Address bus bit 12 |
| Pin 5 | A11 β Address bus bit 11 |
| Pin 6 | A10 β Address bus bit 10 |
| Pin 7 | A9 β Address bus bit 9 |
| Pin 8 | A8 β Address bus bit 8 |
| Pin 9 | AD7 β Multiplexed address/data bus bit 7 |
| Pin 10 | AD6 β Multiplexed address/data bus bit 6 |
| Pin 11 | AD5 β Multiplexed address/data bus bit 5 |
| Pin 12 | AD4 β Multiplexed address/data bus bit 4 |
| Pin 13 | AD3 β Multiplexed address/data bus bit 3 |
| Pin 14 | AD2 β Multiplexed address/data bus bit 2 |
| Pin 15 | AD1 β Multiplexed address/data bus bit 1 |
| Pin 16 | AD0 β Multiplexed address/data bus bit 0 |
| Pin 17 | NMI β Non-maskable interrupt request |
| Pin 18 | INTR β Maskable interrupt request |
| Pin 19 | CLK β System clock input (from 8284A) |
| Pin 20 | GND β Ground |
| Pin 21 | RESET β System reset input |
| Pin 22 | READY β Wait-state control input |
| Pin 23 | TEST β Test input used by WAIT instruction |
| Pin 24 | INTA β Interrupt acknowledge (min mode) / QS1 (max mode) |
| Pin 25 | ALE β Address latch enable (min mode) / QS0 (max mode) |
| Pin 26 | DEN β Data enable (min mode) / SSO (max mode) |
| Pin 27 | DT/R β Data transmit/receive (min mode) / IO/M (max mode) |
| Pin 28 | M/IO β Memory or I/O select (min mode) / LOCK (max mode) |
| Pin 29 | WR β Write strobe (min mode) / S2 (max mode) |
| Pin 30 | HLDA β Hold acknowledge (min mode) / S1 (max mode) |
| Pin 31 | HOLD β Hold request (min mode) / S0 (max mode) |
| Pin 32 | RD β Read strobe |
| Pin 33 | MN/MX β Minimum/Maximum mode select strap |
| Pin 34 | SSO β Status output (min mode) / high (max mode) |
| Pin 35 | A19/S6 β Address bit 19 / status S6 |
| Pin 36 | A18/S5 β Address bit 18 / interrupt-enable status S5 |
| Pin 37 | A17/S4 β Address bit 17 / segment status S4 |
| Pin 38 | A16/S3 β Address bit 16 / segment status S3 |
| Pin 39 | A15 β Address bus bit 15 |
| Pin 40 | VCC β Power supply, 5 V |
Typical Applications
CP80C88-2Z is suitable for 6 applications: Legacy Industrial Control Systems, Embedded x86 Single-Board Computers, Test and Measurement Equipment Maintenance, Avionics and Regulated-Industry Sustaining Engineering, Retro-Computing and Educational Platforms, Multiprocessor / MAXimum-Mode Systems.
Legacy Industrial Control Systems
Many industrial controllers, PLC front-ends, and data-acquisition boards from the 1980s-1990s are built around the 8088 bus running at 5-8 MHz. The CP80C88-2Z fits these systems exactly: it reproduces 8088 MIN/MAX bus timing at 8 MHz, drives the same multiplexed AD0-AD7 bus, and works with period-correct support chips such as the 8284A clock generator and 8237A DMA controller. Its CMOS process reduces power dissipation versus NMOS predecessors, easing thermal constraints in sealed cabinets. When a failed NMOS 8088 or a discontinued 80C88 must be replaced, the -2Z keeps the board certified and operational without PCB changes.
Recommended
Embedded x86 Single-Board Computers
Single-board computers (SBCs) based on the 8088 architecture use the CP80C88-2Z as the CPU with a 20-bit address bus providing 1 MB of DRAM/EPROM space. The multiplexed 8-bit data bus simplifies PCB routing on two-layer legacy boards, and MINimum mode removes the need for an external bus controller in minimal designs. At 8 MHz, typical instruction throughput supports ROM-BIOS style firmware and DOS-compatible environments. Because the part is CMOS, battery-backed and low-fan SBC enclosures run cooler, and the 5 V single-rail supply matches period-correct power-supply designs. RoHS compliance (Z suffix) allows continued manufacture of updated SBC revisions for EU markets.
Recommended
Test and Measurement Equipment Maintenance
Bench instruments - frequency counters, logic analyzers, and signal generators of the era - frequently used the 80C88 as the system CPU running proprietary firmware in EPROM. Repair labs maintaining such equipment need an electrically identical, reliably sourced CPU: the CP80C88-2Z provides 8 MHz timing identical to the -2 speed grade, preserving calibration-related timing loops in firmware. Its 40-PDIP socketed package allows quick replacement without hot-air rework, and RoHS/lead-free construction simplifies handling compliance in modern service facilities. stocking the -2Z alongside the 8284A and 8259A covers the most common CPU-section failures in 8088-based instruments.
Recommended
Avionics and Regulated-Industry Sustaining Engineering
Avionics sub-systems, ground-support equipment, and defense spares pools often must sustain 8088-based line-replaceable units for decades. Recertifying such units around a modern processor is usually more expensive than sourcing an authentic replacement CPU. The CP80C88-2Z offers the exact 8088 real-mode instruction set, MIN/MAX bus behavior, and 8 MHz timing of the original -2 part, with CMOS power benefits and RoHS construction. Its documented, stable silicon makes configuration-management paperwork straightforward: no stepping changes or errata surprises. Procurement should treat it as a last-time-buy item and lock in sufficient quantities for the remaining service life of the platform.
Recommended
Retro-Computing and Educational Platforms
Builders of PC/XT-class retro computers and university computer-architecture labs choose the CP80C88-2Z because it is a genuine 8088-executing CPU in a hand-solderable 40-pin PDIP. At 8 MHz it runs classic BIOS and DOS software at authentic speeds, while CMOS construction cuts current draw significantly compared with hot-running NMOS 8088s - important for open-frame replicas and long lab sessions. The Z suffix provides RoHS-compliant soldering for new board fabrication. Its multiplexed AD0-AD7 bus and MIN/MAX mode strap also make it an excellent teaching vehicle for demultiplexing latches (74LS373), bus controllers, and interrupt structures.
Recommended
Multiprocessor / MAXimum-Mode Systems
In MAXimum mode (MN/MX tied low), the CP80C88-2Z offloads bus command generation to an external 8288 bus controller, enabling multi-master systems with HOLD/HLDA arbitration and the INTA/LOCK signaling needed for coprocessor or shared-bus designs. Legacy multiprocessing boards, 8087 math-coprocessor hosts, and dual-CPU industrial controllers rely on this mode. The -2Z sustains full 8 MHz operation so that 8087 and 8288 timing budgets remain identical to the original design. Designers should verify READY synchronization and lock-prefix behavior against the manufacturer datasheet AC timing tables, as CMOS output edges differ slightly from NMOS predecessors.
Recommended
Recommended Products Summary
Engineering reference data for CP80C88-2Z β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | CP80C88-2 | CP80C88Z | P8088-2 |
|---|---|---|---|---|
| Package | 40-PDIP (0.600 in) | 40-PDIP (0.600 in) - same | 40-PDIP (0.600 in) - same | 40-PDIP (0.600 in) - same |
| Brand | Renesas / Intersil | Renesas / Intersil | Renesas / Intersil | Intel |
| Max Clock Frequency | 8 MHz | 8 MHz | 5 MHz | 8 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V |
| Process Technology | CMOS | CMOS | CMOS | NMOS |
| RoHS / Lead Free | RoHS compliant, lead free (Z) | Non-Z (verify) | RoHS compliant (Z) | No (legacy NMOS) |
| Power Consumption | Low (CMOS) | Low (CMOS) | Low (CMOS) | High (NMOS) |
| Data Bus Width | 8 bit external / 16 bit internal | 8/16 bit | 8/16 bit | 8/16 bit |
Key Differentiators
- Full 8 MHz speed grade with RoHS construction (vs CP80C88Z)
- CMOS power efficiency (vs P8088-2)
- RoHS/lead-free compliance for new builds (vs CP80C88-2)
- Trade-off: commercial temperature range only (vs CP80C88-2)
Design Notes
Power the CP80C88-2Z from a clean 5 V rail (nominal 5 V +/-10% for this family per period-correct practice). Decouple VCC (pin 40) with a 100 nF ceramic capacitor placed within 10 mm of the pin, plus 10 uF bulk per board. One key benefit of the CMOS 80C88 over NMOS 8088 parts is dramatically lower static current, but dynamic current still scales with clock frequency - at 8 MHz ensure the regulator margin accounts for simultaneous bus switching on AD0-AD7 and A8-A19. Estimated: dynamic current contribution is on the order of tens of mA at 8 MHz, far below NMOS-class devices; confirm against the manufacturer datasheet ICC table.
Latch AD0-AD7 with a 74LS373/74HC373 transparent latch clocked by ALE (pin 25) early in each bus cycle. Keep ALE-to-latch traces short to avoid metastable address capture at 8 MHz. Route the multiplexed AD bus and status lines away from the CLK (pin 19) net to prevent coupling glitches. Provide a pair of GND returns (pins 1 and 20) with low-impedance connections. For MAXimum mode, strap MN/MX (pin 33) low and connect S0-S2 to the 8288 bus controller; leave mode-strapping resistors documented on the silkscreen for serviceability.
Three frequent failure modes when substituting CPUs in 8088 boards: (1) clock phasing - use the 8284A, not a bare oscillator, so RESET and READY are synchronized to CLK; (2) READY timing - slow EPROM/EEPROM must assert READY through the 8284A wait-state logic, otherwise bus cycles fail only at 8 MHz (5 MHz-rated CP80C88Z may appear to work); (3) NMOS-to-CMOS substitution - original NMOS 8088 parts have different drive levels and AC edges; verify HOLD/HLDA arbitration and coprocessor (8087) synchronization when mixing technologies. Always validate with a full memory/interrupt stress test at maximum clock.
Compliance Information
RoHS Status: RoHS Compliant; Lead Free Status: Lead Free, per chipdig.com specification listing and the Z suffix convention. REACH, halogen-free, and conflict-minerals status not stated in provided data.
