DS90UR241IVS - 1.03Gbps 24-Bit FPD-Link II Serializer | TI
MPN: DS90UR241IVS ✓ ActiveDS90UR241IVS Overview
An FPD-Link II serializer is an interface IC within the LVDS serializer and deserializer chipset category. Its function is to convert a parallel source bus into a high-speed differential data stream while preserving timing through embedded clock information. This approach can reduce PCB routing width, connector pin count, cable size, and system cost compared with routing 24 individual data lines between a graphics source and its destination.
The DS90UR241's principal operating parameters are a 5 MHz to 43 MHz pixel-clock range, 24 parallel input bits, one LVDS output, and a maximum data rate of 1.03 Gbps. DC-balanced signaling reduces the cumulative DC offset associated with unbalanced data transfer and supports reliable point-to-point communication. The embedded clock allows the receiving device to recover timing from the serial stream without a separate source-synchronous clock.
The chipset architecture supports transparent transfer of pixel data and control information. Typical signal combinations include 18-bit RGB data with horizontal sync, vertical sync, data enable, and three additional general-purpose channels. The serializer therefore supports display-oriented transfers that combine video, synchronization, and control information into one serial link while maintaining a defined relationship between the parallel source and serialized output.
Typical uses include graphics controllers driving flat-panel displays, industrial human-machine interfaces, medical imaging consoles, automotive display systems, point-of-sale terminals, and compact control panels. In each case, the link must satisfy both the source timing requirements and the receiver's supported input and data-rate limits. The 43 MHz upper pixel-clock boundary is particularly important when selecting display modes, cable length, connector geometry, and receiver capabilities.
Layout is critical because the serializer contains high-speed differential outputs that require controlled impedance, short routing, and a continuous return path. Follow the manufacturer pin-description table and recommended layout guidance, place decoupling and interface-support components close to their associated pins, and verify eye quality at the intended pixel-clock rate. The LVDS cable or PCB channel should also be characterized when loss, skew, reflections, or EMI margin are significant.
This page combines the exact operating facts, package information, application guidance, comparison criteria, and practical interface-design considerations engineers need when qualifying the DS90UR241IVS for a new graphics link.
Drop-in alternatives for DS90UR241IVS — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
DS90UR241IVS/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
DS90UR241QVS
✅ Drop-In📋 Reference alternative (not in catalog)
DS90UR241QVS/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
DS90UR241IVSX/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
DS90UR241IVS Specifications
| Product Function | 24-bit FPD-Link II serializer |
| Parallel Data Width | 24 bits |
| Pixel Clock Frequency Range | 5 MHz to 43 MHz |
| Maximum Data Rate | 1.03 Gbps |
| Serializer Input Count | 24 inputs |
| Serializer Output Count | 1 output |
| Signaling Standard | FPD-Link II LVDS |
| DC Balance | DC-balanced serial signaling |
| Clocking Method | Embedded clock information |
| Supported Display Color Depth | 18-bit color |
| Control Signals | Horizontal sync, vertical sync, data enable, and 3 general-purpose channels |
| Package Type | 48-pin TQFP |
| Package Dimensions | 7 mm x 7 mm |
| Mounting Type | Surface mount |
| Temperature Grade | Industrial |
| Terminal Form | Gull wing |
| Lead-Free Finish | Lead-free ordering option indicated by /NOPB |
DS90UR241IVS 7 mm x 7 mm Pin Configuration Guide
Pin configuration for DS90UR241IVS (7 mm x 7 mm package). Pin numbering, functions, and connection diagrams are defined in the manufacturer datasheet. Refer to it for the exact footprint and soldering guidelines.
No detailed pinout data available for DS90UR241IVS.
Refer to the datasheet for full pin configuration.
Typical Applications
DS90UR241IVS is suitable for 6 applications: Industrial Human-Machine Interfaces, Flat-Panel Display Graphics, Medical Imaging Consoles, Automotive Display Interfaces, Point-of-Sale and Retail Terminals, Embedded Control and Monitoring Panels.
Industrial Human-Machine Interfaces
The DS90UR241IVS fits industrial HMI links that carry active display data and control signals between a graphics engine and a compatible receiver. Its 24-bit parallel input supports an 18-bit color stream with horizontal sync, vertical sync, data enable, and three general-purpose channels, while the 5 MHz to 43 MHz pixel-clock range covers many embedded display modes. The 1.03 Gbps serial rate and embedded clock reduce parallel routing width. During implementation, verify receiver timing, differential impedance, connector geometry, and EMI margins in the final enclosure.
Recommended
Flat-Panel Display Graphics
The DS90UR241IVS is suited to point-to-point graphics links between an LVDS-capable video controller and a compatible display receiver. A supported configuration can transport RGB666 color data together with horizontal synchronization, vertical synchronization, data enable, and three additional control channels over one DC-balanced serial stream. The serializer operates from 5 MHz to 43 MHz and provides up to 1.03 Gbps, allowing the design to use fewer PCB traces and connector pins than a wide parallel bus. Validate the target display timing and receiver protocol before selecting a display mode.
Recommended
Medical Imaging Consoles
The DS90UR241IVS can serve as the transmit-side device in a compact medical display console when the receiving equipment supports the corresponding FPD-Link II LVDS protocol. The 24-bit input consolidates pixel and control information into one differential channel, while the embedded clock recovers timing without requiring a separate clock route. This can simplify routing in dense equipment where connector space and PCB area are constrained. The design should maintain controlled differential impedance, use the manufacturer recommended reference layout, and verify image timing, link margin, and electrical isolation requirements for the finished medical system.
Recommended
Automotive Display Interfaces
The DS90UR241 family is applicable to automotive display links, and the DS90UR241QVS ordering option provides an automotive-qualified path where that qualification is required. The serializer accepts 24 parallel bits at pixel clocks from 5 MHz to 43 MHz and sends the data with clock information over one DC-balanced LVDS output. This allows a vehicle display controller to reduce wiring width and connector size. Automotive qualification does not replace system validation, so the interface must still pass EMC, temperature, ground-offset, cable, and receiver-compatibility requirements for the vehicle platform.
Recommended
Point-of-Sale and Retail Terminals
Retail terminals often combine a compact display with touch or control signals while placing strict limits on connector size and PCB routing area. The DS90UR241IVS combines a 24-bit source bus into one 1.03 Gbps-capable FPD-Link II LVDS stream and can carry display synchronization plus three general-purpose channels. Its embedded clock simplifies source-to-receiver connectivity and supports a compact point-to-point interface. Select a receiver with matching timing and protocol behavior, keep the differential pair short and impedance controlled, and verify the chosen display mode remains within the 5 MHz to 43 MHz clock range.
Recommended
Embedded Control and Monitoring Panels
The DS90UR241IVS can consolidate graphics and supervisory control data between an embedded controller and a remote monitoring panel. The 24-bit parallel input works with 18-bit color data plus synchronization, enable, and general-purpose channels, allowing one serial link to carry both display content and panel-control information. The 43 MHz maximum pixel clock supports higher-resolution timing within the device family limits, while the embedded clock removes a separate timing route. Ensure the remote receiver understands the transmitted protocol and test cable loss, skew, grounding, and enclosure effects under the expected temperature range.
Recommended
Recommended Products Summary
Engineering reference data for DS90UR241IVS — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DS90UR241IVS/NOPB | DS90UR241QVS | DS90UR241QVS/NOPB | DS90UR241IVSX/NOPB |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-pin TQFP (7 mm x 7 mm) | 48-pin TQFP (7 mm x 7 mm) | 48-pin TQFP (7 mm x 7 mm) | 48-pin TQFP (7 mm x 7 mm) | 48-pin TQFP (7 mm x 7 mm) |
| Product Function | 24-bit FPD-Link II serializer | 24-bit FPD-Link II serializer | 24-bit FPD-Link II serializer | 24-bit FPD-Link II serializer | 24-bit FPD-Link II serializer |
| Pixel Clock Frequency Range | 5 MHz to 43 MHz | 5 MHz to 43 MHz | 5 MHz to 43 MHz | 5 MHz to 43 MHz | 5 MHz to 43 MHz |
| Parallel Data Width | 24 bits | 24 bits | 24 bits | 24 bits | 24 bits |
| Signaling | DC-balanced FPD-Link II LVDS with embedded clock | DC-balanced FPD-Link II LVDS with embedded clock | DC-balanced FPD-Link II LVDS with embedded clock | DC-balanced FPD-Link II LVDS with embedded clock | DC-balanced FPD-Link II LVDS with embedded clock |
Key Differentiators
- Combines 24-bit source data into one high-speed serializer output (vs DS90UR241IVS/NOPB)
- Supports compact point-to-point display links (vs DS90UR241QVS)
- Preserves embedded-clock LVDS operation (vs DS90UR241QVS/NOPB)
Design Notes
Treat the FPD-Link II LVDS output as a controlled-impedance differential pair. Follow the manufacturer pinout and layout guidance, route the pair over a continuous reference plane, minimize vias and stubs, and maintain matched spacing and length. The family documentation notes that optimizing serializer output edge rate for the operating-frequency range reduces EMI. Validate the completed PCB or cable channel with eye measurements at the highest intended pixel clock rather than relying only on schematic connectivity.
Use the manufacturer reference layout for component placement, decoupling, and differential-output escape routing. Keep bypass connections short and use the package ground pins as intended by the pin-description table. A compact 48-pin TQFP can create routing congestion around the serializer output and parallel inputs, so establish the board-layer stack-up and controlled-impedance geometry before placement. Compare final signal-integrity results with the receiver requirements for the selected display timing.
Do not select the device from the 1.03 Gbps headline rate alone; the source pixel clock must remain between 5 MHz and 43 MHz, and the receiving device must support the corresponding 24-bit FPD-Link II protocol. Also distinguish the serializer from the companion deserializer when assigning PCB functions. Confirm the exact ordering suffix, qualification context, temperature grade, and shipment form to avoid mismatching a production requirement with a functionally similar family member.
Compliance Information
Lead-free ordering options are identified by the /NOPB suffix. RoHS, REACH, halogen-free, conflict-minerals, and exact AEC-Q100 status must be confirmed from the current manufacturer product documentation for the selected suffix.
