HCI-CPU-A9554 - EPYC 9554 64-Core 3.1GHz SP5 CPU | Cisco
MPN: HCI-CPU-A9554 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7934 | $7,934.00 |
| 10 | $7537 | $75,370.00 |
| 100 | $7140 | $714,000.00 |
| 500 | $6822 | $3,411,000.00 |
| 1,000 | $6506 | $6,506,000.00 |
HCI-CPU-A9554 Overview
A server processor, or CPU, is the central compute engine of a data center server, sitting at the top of the compute hierarchy (CPU -> compute node -> server -> rack -> data center). The AMD EPYC 9554 belongs to the 4th Generation EPYC 9004 "Genoa" family built on the Zen 4 architecture, launched in November 2022. Compared with prior generations, Genoa doubles core counts per socket and transitions to DDR5 and PCIe 5.0 I/O.
Key features of the HCI-CPU-A9554 include 64 physical Zen 4 cores with SMT for 128 threads, a large 256 MB L3 cache that keeps hot datasets on-chip, DDR5-4800 memory channels for bandwidth-hungry workloads, and PCIe 5.0 connectivity to NVMe storage and accelerators. The 360 W TDP enables sustained all-core throughput in thermally capable chassis.
Architecturally, the Zen 4 core uses an optimized pipeline with wider execution and AVX-512 support, while the chiplet-based design separates compute core-complex dies from the I/O die, improving manufacturing yield and scalability across the EPYC 9004 stack.
Typical applications include hyperconverged infrastructure (HCI) clusters running Nutanix or VMware, high-density virtualization, databases and analytics, and HPC workloads that exploit high multithreaded throughput and large L3 cache.
Design consideration: confirm your Cisco server chassis thermal solution and PSU budget support the 360 W TDP before upgrade, and match DDR5 DIMM speed to 4800 MT/s to avoid memory downclocking.
This page synthesizes distributor pricing, drop-in alternative PIDs, and practical upgrade guidance not found in a single datasheet.
Drop-in alternatives for HCI-CPU-A9554 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
UCS-CPU-A9554
✅ Drop-In📋 Reference alternative (not in catalog)
UCSX-CPU-A9554
✅ Drop-In📋 Reference alternative (not in catalog)
UCS-CPU-A9554P
✅ Drop-In📋 Reference alternative (not in catalog)
EPYC 9554
✅ Drop-In📋 Reference alternative (not in catalog)
EPYC 9554P
✅ Drop-In📋 Reference alternative (not in catalog)
HCI-CPU-A9554 Specifications (manufacturer-published)
| Cisco PID | HCI-CPU-A9554 |
| Underlying Processor | AMD EPYC 9554 |
| CPU Architecture | AMD Zen 4 (EPYC 9004 Genoa, 4th Generation) |
| Core Count | 64 cores |
| Thread Count | 128 threads (SMT) |
| Base Clock | 3.1 GHz |
| L3 Cache | 256 MB |
| TDP | 360 W |
| Socket | Socket SP5 (LGA-6096) |
| Memory Support | DDR5-4800 MT/s (ECC registered) |
| PCIe Support | PCIe 5.0 |
| Launch Date | November 2022 |
| Target Platform | Cisco UCS / Cisco Compute Hyperconverged (HCI) servers, e.g. UCSX 215C M8 |
| Packaging Condition | New in tray (processor upgrade kit) |
HCI-CPU-A9554 Interfaces & Connectors
HCI-CPU-A9554 exposes the following interfaces and connectors as published by the manufacturer: PCIe. Expansion header pinout, connector pin numbering, and electrical limits are defined in the manufacturer documentation.
| PCIe | PCIe 5.0 |
Refer to the manufacturer documentation for the full expansion header pinout and connector pin numbering.
Typical Applications
HCI-CPU-A9554 is suitable for 6 applications: Hyperconverged Infrastructure (HCI) Nodes, High-Density Virtualization and VDI, Databases and Analytics, AI Inference and Data Preprocessing, Enterprise Storage and Software-Defined Storage, Private Cloud and Server Consolidation.
Hyperconverged Infrastructure (HCI) Nodes
The HCI-CPU-A9554 is purpose-qualified for Cisco Compute Hyperconverged servers running platforms such as Nutanix. Its 64 Zen 4 cores and 128 threads provide the VM density that HCI clusters demand, while the 256 MB L3 cache keeps virtualization metadata and hot working sets on-die, reducing latency to memory. DDR5-4800 across 12 channels per socket supplies the bandwidth that storage-locality layers (vSAN, Nutanix DFS) consume when servicing both compute and I/O on the same node. The 360 W TDP rating requires the validated Cisco heatsink kit, but in exchange delivers sustained all-core throughput under mixed workload consolidation. In an HCI cluster, each node combines compute, storage, and networking, so CPU headroom directly determines cluster scaling; the EPYC 9554's core count allows administrators to consolidate more workloads per node, lowering total cost per VM.
Recommended
High-Density Virtualization and VDI
For virtual desktop infrastructure (VDI) and large multi-tenant virtualization, the HCI-CPU-A9554's 64 physical cores with SMT (128 threads) let administrators pack hundreds of vCPUs per socket. The Zen 4 architecture's wider execution engine and AVX-512 support accelerate both general VM workloads and modern encryption (AES, TLS) that VDI brokering demands. The 256 MB L3 cache reduces cross-VM cache thrashing in dense consolidation ratios, and DDR5-4800 with 12 channels prevents memory bandwidth from becoming the bottleneck at high VM counts. Per distributor specifications, the 360 W TDP budget permits sustained turbo operation under full-host load, which is common in morning logon storms in VDI environments. Deployed in a Cisco HCI node, the processor pairs with PCIe 5.0 NVMe tiers to keep desktop images responsive under random I/O.
Recommended
Databases and Analytics
Enterprise databases (PostgreSQL, Oracle, SQL Server) and analytics engines benefit directly from the EPYC 9554's large 256 MB L3 cache, which keeps index pages and query intermediates close to the cores and cuts memory-latency stalls. The 3.1 GHz base clock with sustained all-core operation provides consistent OLTP response times, while 128 threads accelerate parallel query execution, columnar scans, and data-warehouse aggregations. DDR5-4800 across 12 channels delivers the bandwidth that in-memory databases and large buffer pools require; on Cisco HCI nodes this CPU allows database and storage services to coexist without starving each other. The 360 W TDP must be matched with the validated thermal kit, but the payoff is stable throughput for 24/7 transactional workloads where clock consistency matters more than peak boost.
Recommended
AI Inference and Data Preprocessing
While GPU acceleration dominates AI training, CPU-side inference and data preprocessing pipelines benefit strongly from the HCI-CPU-A9554. Zen 4 introduces AVX-512 with double-pumped FP32/FP16 paths, enabling efficient CPU inference for smaller models and embedding workloads. The 64 cores ingest, tokenize, and augment training data fast enough to keep accelerators saturated, and PCIe 5.0 lanes provide doubled host-to-GPU bandwidth versus PCIe 4.0 platforms, reducing data-transfer bottlenecks. The 256 MB L3 cache and DDR5-4800 memory subsystem sustain feature-store lookups and batch shuffling in distributed dataloaders. In a Cisco HCI deployment, this processor allows AI services to run alongside virtualized business applications on converged infrastructure, and its 360 W envelope supports all-core AVX-512 bursts during preprocessing phases.
Recommended
Enterprise Storage and Software-Defined Storage
Software-defined storage (SDS) controllers, erasure-coded object stores, and distributed file systems are CPU-hungry because parity computation, deduplication, compression, and encryption all execute in software. The HCI-CPU-A9554's 64 Zen 4 cores handle these data-reduction algorithms at line rate, and hardware AES support secures data at rest without measurable CPU penalty. The large 256 MB L3 cache accelerates metadata hashing and block-map operations, while 12 channels of DDR5-4800 feed write-coalescing buffers. On Cisco HCI nodes, this CPU lets the same host serve both application VMs and the SDS layer, which is the core value proposition of hyperconvergence. The PCIe 5.0 interface connects modern NVMe drives at full Gen5 speed, ensuring the storage tier is never the constraint under random-write heavy workloads.
Recommended
Private Cloud and Server Consolidation
For enterprises building private cloud on OpenStack, VMware, or Nutanix, the HCI-CPU-A9554 maximizes consolidation ratio per rack unit. With 128 threads and 256 MB L3 per socket (doubled in 2P configurations), a single Cisco HCI node can host mixed production workloads that previously required multiple legacy servers, cutting power, licensing, and floor-space costs. The 3.1 GHz base clock preserves per-VM performance SLAs even at high consolidation, an important difference from lower-clocked high-core-count SKUs. DDR5-4800 ensures memory-intensive Java and .NET estates are not bandwidth starved, and PCIe 5.0 supports modern 200G networking and NVMe fabrics. Per distributor data the part launched in November 2022 and remains an active, in-stock option as of October 2026, making it a safe anchor for multi-year private cloud builds.
Recommended
Recommended Products Summary
Engineering reference data for HCI-CPU-A9554 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | UCS-CPU-A9554 | UCSX-CPU-A9554 | UCS-CPU-A9554P | EPYC 9554 |
|---|---|---|---|---|---|
| Package | Socket SP5 (LGA-6096) | Socket SP5 (LGA-6096) - same | Socket SP5 (LGA-6096) - same | Socket SP5 (LGA-6096) - same | Socket SP5 (LGA-6096) - same |
| Brand | Cisco Systems (AMD EPYC 9554 based) | Cisco Systems | Cisco Systems | Cisco Systems | AMD |
| Core / Thread Count | 64 cores / 128 threads | 64 / 128 | 64 / 128 | 64 / 128 | 64 / 128 |
| Base Clock | 3.1 GHz | 3.1 GHz | 3.1 GHz | 3.1 GHz | 3.1 GHz |
| L3 Cache | 256 MB | 256 MB | 256 MB | 256 MB | 256 MB |
| TDP | 360 W | 360 W | 360 W | 360 W | 360 W |
| Socket Support (1P/2P) | 1P and 2P | 1P and 2P | 1P and 2P | 1P only | 1P and 2P |
| Memory Support | DDR5-4800 MT/s | DDR5-4800 MT/s | DDR5-4800 MT/s | DDR5-4800 MT/s | DDR5-4800 MT/s |
| Target Platform Validation | Cisco Compute Hyperconverged (HCI) | Cisco UCS C-Series | Cisco UCS X-Series (215C M8) | Cisco UCS C-Series (1P nodes) | Open/whitebox SP5 platforms |
Key Differentiators
- 64 Zen 4 cores at a 3.1 GHz base clock (vs EPYC 9554P)
- Cisco factory validation for HCI platforms (vs EPYC 9554 (bare AMD))
- Large 256 MB L3 cache with DDR5-4800 (vs UCS-CPU-A9554P)
Design Notes
The 360 W TDP is near the top of the SP5 lineup, so thermal design is the first gating check in any upgrade. Confirm the Cisco server chassis uses the validated heatsink and airflow configuration for 360 W-class processors before ordering the PID; Cisco processor PIDs ship as kits that include the correct thermal solution for the target chassis. Reusing a heatsink rated for lower-TDP SKUs will cause rapid junction temperature rise, forced thermal throttling, and reduced all-core sustained clocks. Estimated: at 360 W with a typical server heatsink interface resistance of 0.15 C/W, junction temperature rise above inlet air alone approaches 54 C, leaving little margin in 35 C data center inlets.
Size the server power budget for worst-case dual-socket operation: Estimated two sockets at 360 W each gives 720 W of processor load alone, before memory (12 DIMMs per socket), NVMe drives, and fans. Verify PSU headroom and per-socket power cabling per the Cisco ordering guide. Also confirm the motherboard BIOS/firmware revision supports the EPYC 9554 PID; Cisco validates CPU support per server firmware train, and unlisted combinations may fail POST or support validation.
Memory speed is a frequent upgrade pitfall: the EPYC 9554 supports DDR5-4800, but mixing DIMM generations or populating fewer than 12 channels per socket reduces bandwidth well below platform capability. Populate all channels with matched, qualified Cisco DIMMs at 4800 MT/s. Second, in 2P configurations do not substitute the EPYC 9554P - it is single-socket only. Third, keep PIDs within their validated server family (HCI vs UCS C vs UCS X) to preserve Cisco support entitlements.
Compliance Information
Compliance data for the Cisco PID was not present in the provided web data. AMD EPYC server processors are generally RoHS compliant, but this must be confirmed from official Cisco/AMD documentation before use in compliance-sensitive designs.