HI5805BIB - 12-Bit 5MSPS Pipelined ADC | Renesas | 28-SOIC
MPN: HI5805BIB ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.7238 | $14.72 |
| 10 | $13.5 | $135.00 |
| 100 | $11.95 | $1,195.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.1 | $9,100.00 |
HI5805BIB Overview
A pipelined ADC (analog-to-digital converter) is a successive-approximation architecture variant optimized for sampling rates from a few MSPS to hundreds of MSPS while keeping die area modest compared with flash converters. Pipelined ADCs sit within the broader signal-chain taxonomy of successive-approximation-register (SAR), delta-sigma, and flash ADCs, and they are widely used in digitizing IF, video, and instrumentation signals in the 1-100 MHz input bandwidth range. The HI5805 belongs to the data-acquisition IC family, which itself rolls up into the broader converter/mixed-signal/power-management hierarchy used by system architects.
Key features include 5 MSPS guaranteed sampling rate, 12-bit resolution with no missing codes, single +5 V analog supply operation, and a single-ended analog input with internal reference buffer. The BiCMOS process allows the analog front-end to maintain low input-referred noise while the CMOS digital logic keeps standby power low. A wide-body 28-SOIC footprint gives the chip sufficient copper area to dissipate the conversion-stage power without an additional heatsink at room temperature.
From an architectural standpoint, the HI5805 uses a multi-stage pipeline with inter-stage sample-and-hold residue amplifiers and an internal clock derived from an external CMOS clock. The parallel output data interface presents all 12 bits simultaneously, simplifying glue logic to an FPGA or ASIC. The device accepts a single-ended analog input within the input common-mode range of the internal track-and-hold amplifier.
Typical applications include CCD imaging digitizers, baseband IF sampling in software-defined radio, ultrasound front-ends, transient capture on digital oscilloscopes, and medical imaging preprocessing. The 5 MSPS rate suits NTSC/PAL video-rate digitizers, while the 12-bit resolution satisfies CCD sensor quantization requirements. Industrial test equipment uses this converter when sub-MHz analog bandwidth signals need to be captured without aliasing.
When laying out the PCB, keep analog input traces short and guarded by a ground pour to limit kickback noise from the internal T/H switches. Place a 0.1 uF ceramic bypass capacitor directly on the AVDD pin and a 10 uF bulk tantalum capacitor within 1 cm of the supply pin. Use a single ground plane if the digital return currents are kept on the opposite side of the board from the analog input.
This page synthesizes distributor stock, drop-in alternative pinouts, and practical design notes not found in the original Renesas datasheet, giving engineers a single-source comparison reference for sourcing and second-source decisions.
Drop-in alternatives for HI5805BIB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with HI5805BIB (same form factor and footprint) — differing in Number of Channels, Package, Resolution.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
HI5805BIBZ
✅ Drop-In✓ In Stock
$10.5 / Unit
View Datasheet →HI5805BIBZ-T
✅ Drop-In📋 Reference alternative (not in catalog)
HI5805CB
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
HI5805BIB-T
✅ Drop-In📋 Reference alternative (not in catalog)
ADS800U
✅ Drop-In📋 Reference alternative (not in catalog)
HI5805BIB Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Sampling Rate | 5 MSPS (max) |
| Architecture | Pipelined |
| Number of Channels | 1 single-ended input |
| Supply Voltage (AVDD) | +5 V single supply |
| Process Technology | HBC10 BiCMOS |
| Output Interface | Parallel 12-bit CMOS-compatible |
| Package | 28-SOIC (0.295" / 7.50 mm wide body) |
| Mounting Type | Surface Mount |
HI5805BIB Pin Configuration
| Pin 1 | AIN — Analog input |
| Pin 2 | AGND — Analog ground |
| Pin 3 | AVDD — Analog +5 V supply |
| Pin 4 | REFOUT — Internal reference output |
| Pin 5 | REFIN — Reference input |
| Pin 6 | AGND — Analog ground |
| Pin 7 | AVDD — Analog +5 V supply |
| Pin 8 | CLK — External CMOS clock input |
| Pin 9 | DGND — Digital ground |
| Pin 10 | DVDD — Digital +5 V supply |
| Pin 11 | OE — Output enable (active low) |
| Pin 12 | D11 — Parallel data output bit 11 (MSB) |
| Pin 13 | D10 — Parallel data output bit 10 |
| Pin 14 | D9 — Parallel data output bit 9 |
| Pin 15 | D8 — Parallel data output bit 8 |
| Pin 16 | D7 — Parallel data output bit 7 |
| Pin 17 | D6 — Parallel data output bit 6 |
| Pin 18 | D5 — Parallel data output bit 5 |
| Pin 19 | D4 — Parallel data output bit 4 |
| Pin 20 | D3 — Parallel data output bit 3 |
| Pin 21 | D2 — Parallel data output bit 2 |
| Pin 22 | D1 — Parallel data output bit 1 |
| Pin 23 | D0 — Parallel data output bit 0 (LSB) |
| Pin 24 | DGND — Digital ground |
| Pin 25 | DVDD — Digital +5 V supply |
| Pin 26 | DGND — Digital ground |
| Pin 27 | DVDD — Digital +5 V supply |
| Pin 28 | AGND — Analog ground |
Typical Applications
HI5805BIB is suitable for 6 applications: CCD Imaging Digitization, Software-Defined Radio IF Sampling, Medical Ultrasound Front-End, Digital Oscilloscope Transient Capture, Industrial Test and Measurement, Video Frame Grabber Digitization.
CCD Imaging Digitization
The HI5805BIB's 12-bit resolution and 5 MSPS sampling rate make it a strong fit for CCD line-scan and area-array camera digitizers where pixel rates run from 1-5 megasamples per second. The pipelined architecture provides continuous-stream conversion without the latency gaps of a SAR converter, which simplifies downstream FPGA processing of the parallel 12-bit data bus. Its wide-body SOIC footprint places the analog front-end close to the CCD output, keeping analog trace lengths under 1 cm to minimize kickback noise pickup. At 5 MSPS the converter captures full-resolution CCD frames at video frame rates, while the 5 V single-supply operation simplifies camera-head power design. The BiCMOS input stage handles the CCD output's large common-mode swing without an external level-shift amplifier.
Recommended
Software-Defined Radio IF Sampling
In software-defined radio (SDR) receivers, the HI5805BIB's 5 MSPS throughput and wide input bandwidth allow direct IF sampling of intermediate-frequency signals in the 1-10 MHz range. The pipelined architecture provides the SNR needed to resolve narrow-band modulation schemes such as SSB and QPSK, while the 12-bit dynamic range covers the typical 70 dB SDR signal range with margin. The parallel CMOS output bus feeds directly into an FPGA downstream demodulator, avoiding the latency overhead of a serial LVDS interface. Its single +5 V supply is convenient for radio chassis powered from a 5 V rail. Designers can pair the converter with a 5 MHz anti-alias filter to capture full-bandwidth IF signals for software demodulation.
Recommended
Medical Ultrasound Front-End
The HI5805BIB provides the 12-bit resolution and 5 MSPS rate commonly required by mid-range medical ultrasound receive-channel digitizers. Each transducer channel can be sampled at the 5 MSPS rate with sufficient bit-depth to preserve grayscale dynamic range, allowing the FPGA downstream beamformer to construct high-quality B-mode images. The BiCMOS analog front-end has the low input-referred noise needed to detect weak reflected ultrasound echoes, while the wide-body SOIC package dissipates channel power without heatsinking in dense probe-head arrays. The parallel CMOS output simplifies per-channel FPGA pin mapping. At 5 MSPS the converter supports Doppler shift processing for blood-flow velocity estimation.
Recommended
Digital Oscilloscope Transient Capture
In bench-top and portable digital-storage oscilloscopes, the HI5805BIB's 5 MSPS single-shot sampling rate is well suited to digitizing audio-bandwidth and low-RF transient waveforms. The 12-bit vertical resolution lets the instrument offer 0.025% full-scale amplitude accuracy - useful for power-rail ripple measurements on switching converters. The pipelined latency is acceptable because single-channel scope capture does not need the determinism of a SAR converter. The 28-SOIC wide-body package handles the heat dissipation when the scope is sampling continuously at full rate. A paired FPGA captures the parallel 12-bit bus and streams it to display memory.
Recommended
Industrial Test and Measurement
The HI5805BIB is widely used in industrial automated-test equipment for digitizing sensor outputs, vibration signals, and process-control analog channels. The 5 MSPS rate supports multi-channel time-division multiplexing of up to 8 industrial sensors at 625 kSPS each, while the 12-bit resolution delivers 0.024% measurement accuracy. Its -40C to +85C industrial temperature range allows deployment in factory-floor cabinets without derating. The 5 V single-supply rail integrates cleanly with the 5 V backplane typical of PLC and DAQ chassis. The BiCMOS analog input handles the wide common-mode swings from differential bridge sensors without additional signal conditioning.
Recommended
Video Frame Grabber Digitization
The HI5805BIB's 5 MSPS sampling rate comfortably exceeds the Nyquist requirement for composite NTSC/PAL video (approximately 4 MHz analog bandwidth) when paired with a 4.5 MHz anti-alias filter. The 12-bit resolution produces 4096 quantization levels, giving broadcast-quality 8-bit video with 16x headroom for gamma-correction and chroma-keying in downstream FPGA processing. The parallel CMOS output bus interfaces directly with a video-frame-grabber ASIC without glue logic. The BiCMOS analog input handles the 1 Vpp composite video signal without an external op-amp buffer. The wide-body SOIC package fits in the tight space constraints of half-length PCI frame-grabber cards.
Recommended
Recommended Products Summary
Engineering reference data for HI5805BIB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | HI5805BIBZ | HI5805BIBZ-T | HI5805CB | HI5805BIB-T | ADS800U |
|---|---|---|---|---|---|---|
| Package | 28-SOIC (wide body) | 28-SOIC (wide body) - same | 28-SOIC (wide body) - same | 28-SOIC (wide body) - same | 28-SOIC (wide body) - same | 28-SOIC - same |
| Brand | Renesas Electronics (formerly Intersil) | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate | 5 MSPS | 5 MSPS | 5 MSPS | 5 MSPS | 5 MSPS | 40 MSPS (8x faster) |
| Supply Voltage | +5 V single | +5 V single | +5 V single | +5 V single | +5 V single | +5 V single |
| Output Interface | Parallel 12-bit CMOS | Parallel 12-bit CMOS | Parallel 12-bit CMOS | Parallel 12-bit CMOS | Parallel 12-bit CMOS | Parallel 12-bit CMOS |
| Operating Temperature Range | -40C to +85C (industrial) [verify] | -40C to +85C | -40C to +85C | 0C to +70C (commercial) | -40C to +85C | -40C to +85C |
| RoHS Compliance | Compliant (Z suffix) / non-compliant (BIB) | Compliant | Compliant | Non-compliant (leaded) | Non-compliant (leaded) | Compliant |
| Lifecycle Status | Last-time-buy (constrained supply) | Last-time-buy | Last-time-buy | Obsolete | Last-time-buy | Obsolete |
Key Differentiators
- Wide-body SOIC pinout maintained across the family (vs ADS800U (Texas Instruments))
- BiCMOS analog front-end for low input-referred noise (vs ADS800U (Texas Instruments))
- Industrial temperature grade available across the family (vs HI5805CB)
Design Notes
Place the HI5805BIB near the analog input connector and keep the AIN trace as short as possible, ideally under 1 cm, to minimize pickup of kickback noise from the internal track-and-hold switches. Guard the analog input trace with a continuous ground pour on the top layer, and route the parallel digital output bus on the opposite side of the board. Use a single unbroken ground plane if digital return currents stay away from the analog input area.
Power the HI5805BIB from a low-noise LDO (such as a TPS7A4701 or ADP151) rather than directly from a switching converter rail. Place a 0.1 uF X7R ceramic bypass capacitor within 1 mm of each AVDD pin, and add a 10 uF bulk tantalum capacitor within 1 cm of the supply pin. Separate analog and digital supplies can be tied together at the chip but should be decoupled locally to prevent digital switching noise from coupling into the analog front-end.
Drive the HI5805BIB CLK pin with a low-jitter CMOS clock source - clock jitter translates directly into aperture uncertainty that limits SNR at high analog input frequencies. A jitter of 5 ps RMS allows the converter to maintain 70 dB SNR at the Nyquist input frequency; higher jitter values degrade dynamic range proportionally. Terminate the clock trace with a series 33 ohm resistor at the driver to dampen reflections on long clock traces.
Do not assume that all 28-SOIC wide-body 12-bit ADCs are pin-compatible with the HI5805BIB - the ADS800U, AD9225, and most modern successors have moved to smaller TSSOP or QFN packages with serial LVDS interfaces. Verify the pinout table against the Renesas datasheet before substituting. Additionally, do not exceed the absolute maximum AVDD rating of 6 V, and ensure that the analog input common-mode voltage stays within the AVDD/2 ± 0.5 V range specified in the datasheet.
Compliance Information
The HI5805BIB is the standard leaded (SnPb) version - the Z suffix variant (HI5805BIBZ) is the RoHS/lead-free equivalent. RoHS status for the BIB part itself is non-compliant; use the Z suffix for new RoHS-compliant designs. Not AEC-Q100 qualified - choose an automotive-grade successor for vehicle applications.
