LTC2174IUKG-14 - 14-Bit 105Msps Quad ADC | Analog Devices
MPN: LTC2174IUKG-14 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $187.45 | $187.45 |
| 10 | $168.71 | $1,687.10 |
| 100 | $149.94 | $14,994.00 |
| 500 | $134.95 | $67,475.00 |
| 1,000 | $119.96 | $119,960.00 |
LTC2174IUKG-14 Overview
A pipelined ADC is an analog-to-digital converter that processes input samples through a cascade of low-resolution flash stages and a digital correction backend, allowing high sampling rates at moderate resolution. Quad ADC ICs package four matched converter channels into one die so that multi-antenna or multi-channel receiver systems can capture synchronized samples without skew between channels. This places the LTC2174 in the broader IC hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Such parts are essential building blocks in 4G LTE base-station digitizers, multi-channel software-defined radio receivers, medical ultrasound beamformers, and any application where four coherent high-speed data streams must be captured at once.
Key features of the LTC2174IUKG-14 include selectable internal 2.2 Vp-p or 1 Vp-p input ranges, an integrated clock duty-cycle stabilizer, and a programmable digital output test pattern generator that aids board-level bring-up. A low-latency LVDS mode reduces the number of output pairs per channel from five to two at higher output frequencies, simplifying board routing in dense multi-channel designs. The optional serial CMOS mode supports 14-bit offset-binary, two's-complement or Gray-coded outputs, easing interconnection to FPGAs and ASICs.
Architecturally the part uses four matched pipelined cores sharing a common reference and clock tree, plus a per-channel track-and-hold. The exposed die pad provides a low thermal-resistance path (theta_JA about 25 °C/W on a standard 4-layer JEDEC test board) so the converter can deliver full performance without forced-air cooling in most embedded designs. Power can be scaled down by clock gating unused channels via the serial configuration port.
Typical applications include cellular base-station receivers, multi-channel IF-sampling SDR cards, portable ultrasound front-ends, and multi-antenna spectrum-analysis acquisition boards. The combination of four matched channels, 14-bit resolution, and a low 410 mW typical power makes the part suitable for fan-out-limited enclosures. Designers should respect the 7x8 mm QFN land pattern and provide sufficient copper area beneath the exposed pad to keep junction temperatures within the industrial range, as well as follow the standard analog supply decoupling topology from the datasheet.
Drop-in alternatives for LTC2174IUKG-14 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2174IUKG-14 (same form factor and footprint) — differing in Package, Resolution, Input Type, Number of Channels, Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2173IUKG-14
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LTC2172IUKG-12
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View Datasheet →LTC2171IUKG-12
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View Datasheet →KAD2710C-10Q68
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View Datasheet →KAD2708L-35Q68
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View Datasheet →LTC2174IUKG-14 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 4 (simultaneously sampling) |
| Architecture | Pipelined |
| Sample Rate (max) | 105 Msps |
| Analog Input Range | 1 Vp-p or 2.2 Vp-p (selectable) |
| Input Type | Differential (typical), single-ended capable |
| SNR | 73.5 dBFS at 105 Msps |
| SFDR | 90 dBFS at 105 Msps |
| Power Dissipation (typical, all 4 ADCs active) | 410 mW |
| Digital Output Format | LVDS or serial CMOS, offset-binary / 2's complement / Gray |
| Clock Interface | DDR LVDS, 74.25 MHz typical |
| Supply Voltage (AVDD) | 1.8 V |
| Supply Voltage (DVDD/OVDD) | 1.8 V |
| Operating Temperature Range | -40 °C to +85 °C (industrial, I-suffix) |
| Package | 52-pin QFN (UKG) 7x8 mm with exposed pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (PBF suffix) |
LTC2174IUKG-14 52-pin qfn (ukg) 7x8 mm with exposed pad Pin Configuration Guide
Pin configuration for LTC2174IUKG-14 (52-pin qfn (ukg) 7x8 mm with exposed pad package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for LTC2174IUKG-14.
Refer to the datasheet for full pin configuration.
Typical Applications
LTC2174IUKG-14 is suitable for 7 applications: Cellular Base-Station Receiver (4G LTE / 5G NR small cell), Multi-Channel Software-Defined Radio (SDR) Receiver Card, Portable Medical Ultrasound Beamforming Front-End, Multi-Antenna Spectrum-Analyzer Acquisition Board, Phased-Array Radar Receive Sampler, High-Speed Multi-Channel Data-Acquisition Module, Multi-Antenna MIMO Wi-Fi 6E Test Receiver.
Cellular Base-Station Receiver (4G LTE / 5G NR small cell)
The LTC2174IUKG-14's four matched 14-bit 105 Msps channels deliver synchronized IF-band sampling at 73.5 dB SNR, ideal for 4x4 MIMO small-cell digitizers. Using differential 1 Vp-p inputs directly into the matched transformer footprint, the four cores share a single low-noise 1.8 V LDO. The exposed thermal pad keeps the junction within the industrial range at the 410 mW typical dissipation. Unlike a discrete quad of single-channel ADCs, the shared clock tree guarantees channel-to-channel skew below 50 ps - critical for pilot-symbol combining in 4G LTE receiver chains per the 21754314fa datasheet.
Recommended
Multi-Channel Software-Defined Radio (SDR) Receiver Card
Software-defined-radio digitizers targeting 50-200 MHz IF bandwidth benefit from the four simultaneously-sampling channels plus selectable 1 Vp-p or 2.2 Vp-p input ranges. Connecting one transformer-driven output per channel to a Virtex-7 or Kintex-7 FPGA via DDR LVDS at 74.25 MHz per lane keeps board trace count manageable. Compared with two dual-channel ADCs, the LTC2174IUKG-14 saves PCB area and removes one skew-matching loop. Power stays near 410 mW with all four channels active, well within fan-less embedded enclosure budgets per the 21754314fa datasheet.
Recommended
Portable Medical Ultrasound Beamforming Front-End
Portable ultrasound probes require 32+ synchronized receive channels; stacking eight LTC2174IUKG-14 ICs yields 32 matched ADC channels at 105 Msps / 14-bit with cross-channel skew well below 100 ps. The exposed QFN pad couples to the probe handle's aluminum heat-spreader, allowing continuous acquisition without throttling. Per the 21754314fa datasheet the I-suffix industrial temperature grade supports the warm handheld enclosure environment near 50 °C ambient. 410 mW per quad ADC contributes roughly 3.3 W for 32 channels, manageable in a battery-powered tablet-style scanner.
Recommended
Multi-Antenna Spectrum-Analyzer Acquisition Board
Wideband spectrum analyzers and electronic-warfare digitizers need simultaneous capture across multiple antennas. Four 105 Msps / 14-bit cores per IC let one LTC2174IUKG-14 feed a 4-antenna array, and stacking four ICs gives 16 channels at 105 Msps - enough for a 400 MHz instantaneous bandwidth IF at a 4-channel-per-antenna over-sampling ratio of 1.6x. The 90 dB SFDR at the rated sample rate guarantees clean tone capture in dense signal environments, while the selectable CMOS/LVDS output eases interfacing to Xilinx or Altera FPGAs per the 21754314fa datasheet.
Recommended
Phased-Array Radar Receive Sampler
Active electronically scanned array (AESA) radar bricks need one synchronized ADC per antenna element; a 16-element sub-array uses four LTC2174IUKG-14 ICs (16 channels at 105 Msps / 14-bit) feeding an FPGA that performs digital beamforming. The matched inter-channel latency is essential for coherent summation across the array face. Per the 21754314fa datasheet the four cores are designed with internal skew calibration, simplifying the beamformer firmware compared with discrete channel assemblies.
Recommended
High-Speed Multi-Channel Data-Acquisition Module
Industrial test-and-measurement platforms require simultaneous sampling across many sensors. Plug-in DAQ cards can populate 32 channels with eight LTC2174IUKG-14 ICs, achieving 105 Msps / 14-bit acquisition per channel. The shared 1.8 V AVDD/DVDD simplifies power-tree design, while the selectable internal reference removes the need for an external ADC reference per IC. The exposed pad meets the IPC-9701 thermal-cycling expectations typical of OEM instrumentation per the 21754314fa datasheet.
Recommended
Multi-Antenna MIMO Wi-Fi 6E Test Receiver
Wi-Fi 6E development testers use 4x4 capture paths; one LTC2174IUKG-14 per 4x4 radio stream delivers 14-bit 105 Msps samples at 73.5 dB SNR - enough dynamic range for the -30 to -10 dBm reference signals of the 802.11ax test suite. The 7x8 mm QFN allows dense integration of multiple radios on a single compliance-test fixture PCB, and the 1.8 V supply draws from a shared buck converter. Per the 21754314fa datasheet the LVDS-mode option reduces output pin count for FPGA-routing reasons when 8 lanes per IC would otherwise exhaust FPGA DFI pins.
Recommended
Recommended Products Summary
Engineering reference data for LTC2174IUKG-14 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2173IUKG-14 | LTC2175IUKG-14 | LTC2172IUKG-12 | LTC2171IUKG-12 | KAD2710C-10Q68 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Renesas Electronics |
| Package | 52-QFN (UKG) 7x8 mm | 52-QFN (UKG) 7x8 mm | 52-QFN (UKG) 7x8 mm | 52-QFN (UKG) 7x8 mm | 52-QFN (UKG) 7x8 mm | 52-QFN (UKG) 7x8 mm |
| Resolution | 14 bit | 14 bit | 14 bit | 12 bit | 12 bit | 10 bit |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 1 |
| Max Sample Rate | 105 Msps | 80 Msps | 125 Msps | 65 Msps | 40 Msps | 80 Msps |
| SNR | 73.5 dB | 73.5 dB | 73.5 dB | 70.5 dB | 70.5 dB | 60 dB |
| Output Format | LVDS or CMOS | LVDS or CMOS | LVDS or CMOS | LVDS or CMOS | LVDS or CMOS | LVDS |
Key Differentiators
- Highest sample-rate resolution-per-mW in the LTC217x family (vs LTC2173IUKG-14)
- Lower per-mW dissipation than 12-bit predecessors (vs LTC2172IUKG-12)
- Internal 2.2 Vp-p / 1 Vp-p selectable input range (vs KAD2710C-10Q68)
- Quad-matched channels with shared clock tree (vs LTC2156IUP-14)
Design Notes
Estimated: at 1.8 V AVDD + 1.8 V DVDD with all four channels converting at 105 Msps, total dissipation of 410 mW produces a junction rise of roughly 10 °C above ambient on a 4-layer JEDEC board per the 21754314fa datasheet thermal table (theta_JA = 25 °C/W). Keep the 7x8 mm QFN exposed pad soldered to a continuous copper plane of at least 1 cm² - interruption of this copper plane raises theta_JA past 60 °C/W and may force derating at higher temperature. Industrial -40 to +85 °C operation is typically achievable without forced air.
The 52-pin QFN UKG package requires a per-pin via-in-pad escape array and a flooded 7x8 mm exposed-pad land pattern. Per the 21754314fa datasheet, route the four ADC input traces as tightly-coupled 100 ohm differential pairs with a continuous ground reference on layer 2; allow at least 4 mm of trace length for the user-specific anti-alias filter. Keep CLK+/- and data LVDS lines away from noisy switching power paths.
Per the 21754314fa datasheet, decouple AVDD with a 1 uF X7R ceramic plus a 10 nF X7R ceramic in parallel, placed within 2 mm of each analog supply pin. Use a low-noise 1.8 V LDO (e.g. ADP1740 or ADP7102 family) rather than a switching converter for the analog rail - switching ripple couples directly into the sampled analog input path. Budget at least 1 A available current per IC to avoid droop during simultaneous-sample events.
Terminate the LVDS clock input with a 100 ohm differential resistor placed within 5 mm of the LVDS CLK+/- pins; transmission-line stubs longer than 3 mm will degrade setup timing. For long-board LVDS output lanes (toward the FPGA), source-terminate at the ADC end with 33 ohm series resistors, per the 21754314fa datasheet reference design. When operating in CMOS mode, add a 20 ohm damping resistor to limit overshoot at 105 Msps on parallel CMOS buses.
Compliance Information
RoHS/REACH compliance per Analog Devices product page (PBF suffix). AEC-Q100 not applicable for industrial-grade ADC. Halogen-free status not stated in the verified web data; marked unknown.
