LTC2195CUKG - 16-Bit 125Msps Dual ADC | Analog Devices
MPN: LTC2195CUKG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $165.77 | $165.77 |
| 10 | $152.45 | $1,524.50 |
| 100 | $138.2 | $13,820.00 |
| 500 | $124.9 | $62,450.00 |
| 1,000 | $110.85 | $110,850.00 |
LTC2195CUKG Overview
A pipelined ADC is a high-speed successive-approximation architecture in which the input sample passes through multiple low-resolution flash stages, each stage producing one or more output bits and a residual that is amplified into the next stage. By correcting digital errors across stages, pipelined ADCs reach 12-16 bit resolution at sample rates from 50 Msps to over 500 Msps, making them the workhorse for communications, radar, and instrumentation front-ends. The LTC2195 belongs to the broader class of low-power dual ADCs, which sit in the signal chain between analog conditioning (amplifiers, filters) and the FPGA or DSP that performs demodulation, FFT, or beamforming.
Key features include differential inputs with 650 MHz full-power bandwidth, LVDS digital outputs, a serial SPI port for configuration, and a typical power dissipation near 250 mW per channel at 125 Msps. Built-in digital gain and offset correction, dither, and a programmable output demultiplexer reduce downstream FPGA logic and simplify PCB routing. The 52-QFN exposed-pad package keeps thermal resistance low for reliable operation across the -40 C to +85 C commercial range.
Typical applications include multi-carrier 3G/4G LTE base-station receivers, diversity radio and MIMO front-ends, IF-sampling software-defined radio (SDR), high-speed oscilloscopes and digitizers, medical imaging ultrasound, and radar/EW digitizing channels. The simultaneous-sampling dual-channel architecture is especially valuable where two channels must be captured with deterministic inter-channel skew, such as I/Q demodulation or phased-array beamforming.
When designing with the LTC2195CUKG, the analog input network should be a bandwidth-limited differential transformer or fully-differential driver; the LVDS output traces must be length-matched to within 50 mil, and the exposed pad must be soldered to a continuous ground plane. Good decoupling of both AVDD and DVDD rails with 10 uF bulk and 0.1 uF ceramic capacitors is critical for meeting the 76.8 dB SNR spec.
This page synthesizes Analog Devices datasheet parameters, distributor pricing as of 2026-10-13, drop-in same-package alternatives, and practical design guidance not found on the manufacturer product page alone.
Drop-in alternatives for LTC2195CUKG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2195CUKG (same form factor and footprint) — differing in Package, Operating Temperature Range, Resolution, Input Type, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2194CUKG
✅ Drop-In✓ In Stock
$22.95 / Unit
View Datasheet →LTC2193CUKG
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2191CUKG
✅ Drop-In✓ In Stock
$22.4 / Unit
View Datasheet →LTC2175CUKG-14
✅ Drop-In✓ In Stock
$60.7 / Unit
View Datasheet →LTC2171CUKG-14
✅ Drop-In✓ In Stock
$26.75 / Unit
View Datasheet →LTC2170CUKG-12
✅ Drop-In✓ In Stock
$20.65 / Unit
View Datasheet →LTC2195CUKG Maximum Ratings & Electrical Characteristics
| Resolution | 16 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate (per channel) | 125 Msps |
| Architecture | Pipelined |
| Input Type | Differential |
| Input Bandwidth (Full Power) | 650 MHz |
| SNR | 76.8 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Analog Supply Voltage | 1.7 V to 1.9 V |
| Digital Supply Voltage | 1.7 V to 1.9 V |
| Digital Output Interface | LVDS |
| Configuration Interface | Serial SPI |
| Operating Temperature Range | 0 C to +70 C (C-grade) |
| Package | 52-QFN (7x8 mm) with exposed pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (PBF suffix) |
LTC2195CUKG 52-qfn (7x8 mm) with exposed pad Pin Configuration Guide
Pin configuration for LTC2195CUKG (52-qfn (7x8 mm) with exposed pad package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for LTC2195CUKG.
Refer to the datasheet for full pin configuration.
Typical Applications
LTC2195CUKG is suitable for 6 applications: Multi-Carrier LTE Base-Station Receiver, MIMO Diversity Radio Front-End, Software-Defined Radio (SDR) IF Sampling, High-Speed Oscilloscope / Digitizer Channel, Medical Ultrasound Beamformer, Phased-Array Radar / EW Digitizer.
Multi-Carrier LTE Base-Station Receiver
The LTC2195CUKG is ideally matched to multi-carrier LTE base-station receivers because its 76.8 dB SNR supports 64-QAM EVM budgets, and its 90 dB SFDR cleanly handles blocker signals without intermodulation spurs. The two simultaneous-sampling channels allow I and Q baseband digitization in a single IC, halving board area versus discrete dual-ADC solutions. Operating from a 1.8 V supply and 0.07 ps RMS jitter preserves constellation EVM when the upstream mixer output sits near 184 MHz, well within the 650 MHz input bandwidth. The LVDS output interface mates directly with Altera/Xilinx FPGAs that host the CPRI framer, eliminating external logic.
Recommended
MIMO Diversity Radio Front-End
Diversity and MIMO radios require two or more phase-coherent channels captured with deterministic inter-channel skew, which is exactly what the LTC2195CUKG delivers through its simultaneous-sampling dual pipeline architecture. At 125 Msps per channel the device supports LTE, 5G NR, and Wi-Fi 6E capture with 1.8 V AVDD/OVDD rails. Its 650 MHz analog input bandwidth allows direct IF sampling of second- and third-stage mixer outputs, removing an analog baseband stage and reducing BOM cost. The 90 dB SFDR cleanly resolves small desired signals in the presence of strong adjacent-channel blockers typical in dense urban MIMO deployments.
Recommended
Software-Defined Radio (SDR) IF Sampling
The LTC2195CUKG excels in IF-sampling software-defined radio platforms because its 0.07 ps RMS aperture jitter preserves SNR when undersampling intermediate frequencies up to 250 MHz. The 76.8 dB SNR across 100 MHz of input bandwidth satisfies the dynamic-range requirements of wideband HF/VHF/UHF receivers used in military and aerospace SDR. Two channels per IC allow the capture of I and Q baseband signals in a single device, simplifying FPGA timing closure. The 52-QFN exposed pad keeps junction temperature manageable in sealed SDR chassis where airflow is limited.
Recommended
High-Speed Oscilloscope / Digitizer Channel
Bench and modular oscilloscopes use 16-bit, 125 Msps dual ADCs like the LTC2195CUKG for moderate-bandwidth digitizer channels where 8-bit ECL ADCs lack the dynamic range for medical, vibration, and acoustic measurements. The 76.8 dB SNR is equivalent to approximately 12.7 effective bits, sufficient for capturing small ripple on a 200 V power-rail or transient response of a high-speed op-amp. Two simultaneous channels allow true-differential probing or a channel-plus-trigger capture in a single IC. The LVDS output bus simplifies timing closure to a Virtex-7 or Kintex-7 FPGA that hosts the timebase and trigger logic.
Recommended
Medical Ultrasound Beamformer
Medical ultrasound beamforming arrays demand 16-bit resolution at 40-80 Msps per channel with deterministic channel-to-channel skew, and the LTC2195CUKG is well-suited for mid-tier cart-based ultrasound systems operating at 125 Msps. The simultaneous-sampling dual channels reduce board area per channel, which is critical when 64 or 128 receive channels must fit behind the transducer. The 90 dB SFDR preserves harmonic content necessary for tissue harmonic imaging (THI) modes. The 1.8 V AVDD and OVDD rails ease FDA IEC 60601-1 power-supply compliance designs by keeping patient-applied voltages low.
Recommended
Phased-Array Radar / EW Digitizer
Phased-array radar and electronic-warfare receivers require 100+ Msps 16-bit ADCs with excellent spurious-free dynamic range, and the LTC2195CUKG delivers 90 dB SFDR and 76.8 dB SNR per channel for these applications. The 0.07 ps RMS aperture jitter is critical for maintaining radar range-Doppler ambiguity performance, since even small clock jitter smears the SNR of a 1 GHz IF signal. Two simultaneous channels simplify sub-array beamforming where pairs of antenna elements are processed by a single ADC. The 52-QFN (7x8 mm) footprint enables dense daughter-card layouts typical of AESA radar modules.
Recommended
Recommended Products Summary
Engineering reference data for LTC2195CUKG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2194CUKG | LTC2193CUKG | LTC2191CUKG | LTC2175CUKG-14 | LTC2170CUKG-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-QFN (7x8 mm) | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same | 52-QFN (7x8 mm) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 14 bit | 12 bit |
| Sample Rate | 125 Msps | 105 Msps | 80 Msps | 40 Msps | 125 Msps | 105 Msps |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| SNR | 76.8 dB | 76.8 dB | 77 dB | 77.5 dB | 73.4 dB | 68.5 dB |
| SFDR | 90 dB | 90 dB | 90 dB | 90 dB | 88 dB | 84 dB |
| Supply Voltage | 1.7-1.9 V | 1.7-1.9 V | 1.7-1.9 V | 1.7-1.9 V | 1.7-1.9 V | 1.7-1.9 V |
| Digital Output | LVDS | LVDS | LVDS | LVDS | CML/LVDS | CML/LVDS |
Key Differentiators
- Highest sample rate in the LTC2193/2194/2195 pin-compatible family (vs LTC2194CUKG)
- 16-bit SFDR matches lower-speed 80 Msps variant (vs LTC2193CUKG)
- Higher resolution than 14-bit pin-compatible LTC2175 (vs LTC2175CUKG-14)
Design Notes
Place 10 uF X7R bulk and 0.1 uF X7R ceramic decoupling capacitors within 5 mm of each AVDD and OVDD pin, with vias connecting the pad to a solid ground plane. The exposed thermal pad of the 52-QFN must be soldered to a continuous ground plane stitched with a 4x4 via array (0.3 mm vias, 1 mm pitch) to keep junction-to-ambient thermal resistance low and to provide a low-impedance return for the LVDS currents. Input traces must be length-matched within 50 mil, 100 ohm differential, and routed over a continuous ground reference to maintain 76.8 dB SNR.
The LTC2195CUKG's 0.07 ps RMS aperture jitter is its defining low-noise advantage; preserving it requires the ADC clock to come from a low-noise jitter-cleaning PLL such as the LTC6946 or HMC7044, and never from a general-purpose FPGA PLL. CLK+/CLK- must be AC-coupled or DC-coupled with 100 ohm differential termination, and the clock trace must be length-matched to the input trace within 50 mil. Use a transformer (e.g., ADT1-1WT) or a fully-differential driver (e.g., ADL5561) for the analog input; never drive single-ended.
AVDD and OVDD must be generated from separate low-noise LDOs (e.g., LT3042 or LT3045) because sharing a regulator couples digital switching noise into the analog rail. Enable the on-chip dither and digital gain correction via SPI to maximize SFDR at high input frequencies. The total supply current at 125 Msps is approximately 290 mA across AVDD plus OVDD; ensure the LDO dropout budget includes 100 mV of margin across temperature.
Compliance Information
Lead-free PBF suffix indicates RoHS/REACH compliance. AEC-Q100 not applicable for this commercial-grade 16-bit ADC; for automotive applications refer to the ADI automotive-grade portfolio.
