MAX19192ETI/V+ - 10Msps Dual 8-Bit Ultra-Low-Power ADC | Maxim
MPN: MAX19192ETI/V+ ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.42 | $11.42 |
| 10 | $10.27 | $102.70 |
| 100 | $9.12 | $912.00 |
| 500 | $8.18 | $4,090.00 |
| 1,000 | $7.05 | $7,050.00 |
MAX19192ETI/V+ Overview
An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that samples continuous analog voltage levels and converts them into discrete digital codes. Within the broader semiconductor taxonomy, ADCs belong to the data converter family, which sits under signal chain ICs and ultimately under power management and analog mixed-signal semiconductors. The MAX19192's dual-channel, low-power architecture positions it in the pipeline/flash converter category, optimized for simultaneous sampling of two correlated signals without channel-to-channel skew penalty beyond the T/H aperture.
Key features include 10 Msps sampling per channel, dual differential T/H inputs, 48.6 dB SINAD at fIN = 1 MHz, ultra-low power consumption (well below 30 mW total at full speed), and a parallel digital output interface. The 440 MHz T/H bandwidth supports undersampling of IF signals, while the extended industrial -40C to +85C operating temperature range allows deployment in harsh environments without derating. The 28-pin TQFN package provides a compact footprint suitable for portable, space-constrained designs.
The MAX19192 architecture combines a flash-style quantization core with high-bandwidth T/H input stages, enabling low-latency conversion with deterministic aperture delay. The differential input structure rejects common-mode noise, which is critical when digitizing small signals in the presence of digital switching noise on the same PCB. Internal reference and clock buffering simplify external BOM.
Typical applications include portable ultrasound imaging front ends, low-power communication baseband digitizers, handheld oscilloscope input stages, I/Q demodulator outputs in software-defined radio, dual-antenna diversity receivers, and industrial data acquisition modules where two correlated analog signals must be captured simultaneously. When designing with this device, allocate adequate PCB area for the exposed thermal pad to maintain theta_JA performance, and keep analog and digital ground returns separated until they join at the IC's GND pin to avoid coupling digital switching noise into the analog input path.
Drop-in alternatives for MAX19192ETI/V+ — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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MAX19192ETI+T
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MAX19192ETI+
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MAX19192ETI/V+T
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MAX19192ETI/V-T
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MAX19192ETI/V+ Maximum Ratings & Electrical Characteristics
| Part Number | MAX19192ETI/V+ |
| Manufacturer | Maxim Integrated (Analog Devices) |
| Description | Ultra-Low-Power, 10Msps, Dual 8-Bit ADC |
| Resolution | 8 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate | 10 Msps per channel |
| Input Bandwidth (T/H) | 440 MHz |
| Input Type | Fully differential or single-ended |
| SINAD (fIN = 1 MHz) | 48.6 dB (typical) |
| Data Interface | Parallel digital output |
| Operating Temperature | -40C to +85C (extended industrial) |
| Package | 28-pin TQFN (5 mm x 5 mm), exposed thermal pad |
| Package Code (JEDEC) | HVQCCN |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
MAX19192ETI/V+ Pin Configuration
| Pin 1 | INA+ — Channel A positive differential input |
| Pin 2 | INA- — Channel A negative differential input |
| Pin 3 | INB+ — Channel B positive differential input |
| Pin 4 | INB- — Channel B negative differential input |
| Pin 5 | REFOUT — Internal reference output (bypass with cap) |
| Pin 6 | REFIN — External reference input |
| Pin 7 | AVDD — Analog supply voltage |
| Pin 8 | AGND — Analog ground |
| Pin 9 | CLK — Conversion clock input |
| Pin 10 | CLKDUTY — Clock duty-cycle control (tie/decouple per datasheet) |
| Pin 11 | OEB — Output enable bar (active-low) |
| Pin 12 | D0A — Channel A digital output bit 0 (LSB) |
| Pin 13 | D1A — Channel A digital output bit 1 |
| Pin 14 | D2A — Channel A digital output bit 2 |
| Pin 15 | D3A — Channel A digital output bit 3 |
| Pin 16 | D4A — Channel A digital output bit 4 |
| Pin 17 | D5A — Channel A digital output bit 5 |
| Pin 18 | D6A — Channel A digital output bit 6 |
| Pin 19 | D7A — Channel A digital output bit 7 (MSB) |
| Pin 20 | D0B — Channel B digital output bit 0 (LSB) |
| Pin 21 | D1B — Channel B digital output bit 1 |
| Pin 22 | D2B — Channel B digital output bit 2 |
| Pin 23 | D3B — Channel B digital output bit 3 |
| Pin 24 | D4B — Channel B digital output bit 4 |
| Pin 25 | D5B — Channel B digital output bit 5 |
| Pin 26 | D6B — Channel B digital output bit 6 |
| Pin 27 | D7B — Channel B digital output bit 7 (MSB) |
| Pin 28 | DVDD — Digital supply voltage |
| Pin 29 (EP) | EP — Exposed thermal pad - connect to AGND/DGND pour |
Typical Applications
MAX19192ETI/V+ is suitable for 6 applications: Portable Ultrasound Imaging Front End, Low-Power Communication Baseband Digitizer, Handheld Oscilloscope Input Stage, I/Q Demodulator Output Digitizer (SDR), Dual-Antenna Diversity Receiver, Industrial Data Acquisition Module.
Portable Ultrasound Imaging Front End
The MAX19192ETI/V+ suits portable ultrasound front ends that need two correlated analog channels sampled simultaneously at low milliwatt budgets. The dual 8-bit ADC with 440 MHz T/H bandwidth captures RF echoes from a transducer pair without channel-to-channel skew, while the sub-30 mW typical power consumption lets battery-powered handheld scanners run for hours on a single charge. Place the IC adjacent to the LNA outputs; route analog and digital grounds separately and join them only at the exposed thermal pad (EP) of the 28-pin TQFN. Its 8-bit resolution is adequate for B-mode grayscale imaging where dynamic range is typically 40-48 dB; for color Doppler consider pairing it with a separate 10/12-bit ADC downstream.
Recommended
Low-Power Communication Baseband Digitizer
Use the MAX19192ETI/V+ to digitize I and Q baseband signals in low-power software-defined radio receivers. The dual-channel simultaneous sampling removes I/Q skew, while the 10 Msps per-channel rate covers narrowband communications standards up to roughly 5 MHz of usable baseband bandwidth. The differential T/H inputs reject common-mode noise from switching power converters on the same board. Connect the differential I and Q outputs of the demodulator to the two ADC channels; clock both channels from the same CMOS/TTL oscillator to maintain timing alignment. Power consumption typically stays below 30 mW at full speed, making this part suitable for handheld and field-portable radios.
Recommended
Handheld Oscilloscope Input Stage
The MAX19192ETI/V+ is well suited to dual-channel handheld oscilloscope input stages where power, size, and cost are tightly constrained. Two ADCs simultaneously capture CH1 and CH2 waveforms at 10 Msps, sufficient for audio-band, sensor, and low-frequency analog signal analysis up to roughly 4 MHz of useful bandwidth. Its 8-bit vertical resolution provides 256 quantization levels, adequate for general-purpose service diagnostics and educational lab instruments. Place input attenuator/buffer op-amps immediately ahead of each T/H input; keep the parallel digital output bus routed away from analog input traces to avoid digital noise coupling into the measurement path.
Recommended
I/Q Demodulator Output Digitizer (SDR)
For software-defined radio receivers, the MAX19192ETI/V+ digitizes the differential I and Q outputs of an analog demodulator into the FPGA or DSP baseband processor. The dual-channel architecture eliminates the I/Q amplitude and phase imbalance caused by time-interleaved sampling. With 440 MHz T/H bandwidth the ADC can undersample IF signals above the Nyquist limit, simplifying the analog front-end filter chain. Decouple AVDD and DVDD with separate 0.1 uF and 10 uF ceramic capacitors placed within 3 mm of the supply pins; connect the EP to a low-impedance ground pour to maintain thermal performance at full 10 Msps operation.
Recommended
Dual-Antenna Diversity Receiver
The MAX19192ETI/V+ fits diversity receivers that digitize two antenna paths simultaneously for maximum-ratio combining in the baseband processor. Simultaneous dual-channel sampling preserves the phase relationship between antennas, enabling accurate MRC weighting across the two paths. The 8-bit resolution is sufficient for signal-strength monitoring and moderate-throughput data demodulation in sub-6 GHz receiver chains. Route each antenna's LNA output through a separate anti-alias filter into the two T/H inputs; maintain matched trace lengths to preserve channel-to-channel gain and phase balance. Power dissipation below 30 mW keeps thermal management simple in compact handheld terminals.
Recommended
Industrial Data Acquisition Module
For multi-channel industrial data acquisition modules, the MAX19192ETI/V+ serves as a compact dual-channel ADC for sensor signal digitization in PLCs, vibration monitors, and condition-monitoring systems. Two correlated analog channels (e.g. accelerometer X/Y axes) can be sampled simultaneously with deterministic aperture delay, enabling accurate phase-coherent signal analysis. The extended industrial -40C to +85C operating range supports deployment in factory-floor enclosures and outdoor cabinets. The 28-pin TQFN package footprint fits standard 0.5 mm-pitch PCB designs. Use the MAX19192ETI/V+ when two channels at 10 Msps suffice; scale to MAX1300-series parts for higher channel counts and resolution.
Recommended
Recommended Products Summary
Engineering reference data for MAX19192ETI/V+ — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MAX19192ETI+T | MAX19192ETI+ | MAX19192ETI/V+T |
|---|---|---|---|---|
| Brand | Maxim Integrated | Maxim Integrated - same | Maxim Integrated - same | Maxim Integrated - same |
| Package | TQFN-28 (5x5 mm) | TQFN-28 (5x5 mm) - same | TQFN-28 (5x5 mm) - same | TQFN-28 (5x5 mm) - same |
| Resolution | 8 bits | 8 bits | 8 bits | 8 bits |
| Channels | 2 (dual, simultaneous) | 2 (dual, simultaneous) | 2 (dual, simultaneous) | 2 (dual, simultaneous) |
| Sampling Rate | 10 Msps | 10 Msps | 10 Msps | 10 Msps |
| T/H Bandwidth | 440 MHz | 440 MHz | 440 MHz | 440 MHz |
| SINAD at 1 MHz | 48.6 dB | 48.6 dB | 48.6 dB | 48.6 dB |
| Automotive Grade | Yes (V+ suffix) | Yes (V+ suffix) | No (industrial only) | Yes (V+ suffix) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Dual simultaneous-sampling channels in a single 28-pin TQFN (vs MAX19192ETI+ (single-piece qty))
- Ultra-low power consumption at 10 Msps (vs MAX19527 (12-bit, higher sample rate))
- 440 MHz T/H bandwidth enables IF undersampling (vs MAX1300-series SAR ADCs)
Design Notes
Decouple AVDD and DVDD with separate 0.1 uF and 10 uF ceramic capacitors placed within 3 mm of the respective supply pins; route analog and digital ground returns separately and join them only at the IC's exposed thermal pad (EP) ground pour. The 28-pin TQFN package has a small lead pitch; use a 4-layer PCB with continuous ground planes beneath the IC to control return-path impedance at 10 Msps switching rates.
Solder the exposed thermal pad (EP) of the 28-pin TQFN to a continuous ground copper pour of at least 1 square inch to maintain the package's rated thermal resistance. At full 10 Msps simultaneous dual-channel operation, power dissipation can approach 30 mW which alone does not require a heatsink, but thermal relief on the EP is still required for the part to meet AC electrical specifications over the full -40C to +85C industrial range.
Drive the differential analog inputs INA+/INA- and INB+/INB- with matched impedance traces; use 100 ohm differential routing and keep trace length matching to within 0.5 mm to preserve common-mode rejection. The 440 MHz T/H bandwidth can pick up spurious signals above 200 MHz, so place a passive anti-alias filter immediately ahead of each input pair with -3 dB corner set to roughly 0.45 times the maximum analog input frequency of interest.
Do not leave the REFOUT pin unbypassed - connect a 0.1 uF and a 10 uF capacitor in parallel from REFOUT to AGND per the datasheet reference circuit. Ensure OEB is tied low (active) for normal operation; if OEB floats high, all digital outputs enter high-impedance and the ADC appears unresponsive. The clock duty cycle affects SINAD performance - drive CLK with a 50 percent duty cycle source, not a divided-down clock with poor edge symmetry.
Compliance Information
RoHS and lead-free compliance confirmed by Maxim datasheet Rev 0 (2-11-10). The V+ suffix denotes automotive screening per Maxim's part-numbering convention but the part is not formally AEC-Q100 qualified; consult Analog Devices for AEC-Q100 status. Halogen-free status not explicitly documented in available data sources.
