MAX9150EUI+ - 10-Port LVDS Repeater 400Mbps TSSOP-28 | Analog Devices
MPN: MAX9150EUI+ ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.78 | $5.78 |
| 10 | $5.2 | $52.00 |
| 100 | $4.62 | $462.00 |
| 500 | $4.04 | $2,020.00 |
| 1,000 | $3.47 | $3,470.00 |
MAX9150EUI+ Overview
An LVDS repeater is a signal buffer and redriver that accepts a single high-speed differential input and regenerates multiple identical differential outputs. In the signal-integrity hierarchy, it sits between an LVDS driver and its receivers, restoring degraded edge rates and isolating downstream loading from the source. Repeaters are essential in high-speed clock and data distribution trees where fan-out, trace length, or connector discontinuities would otherwise corrupt a direct LVDS link.
Key features of the MAX9150EUI+ include ultra-low 120ps p-p maximum total jitter, guaranteed 100ps maximum skew between channels, and a 400Mbps guaranteed data rate that comfortably supports clock distribution up to 200MHz. A shutdown mode draws only 60uA of supply current, enabling aggressive power management in battery-operated and power-sensitive systems. The device conforms to the EIA/TIA-644 LVDS standard, ensuring interoperability with standard LVDS transmitters and receivers.
Technically, the device accepts a single LVDS input pair and fans it out to ten LVDS output pairs. Low-voltage differential signaling uses a ~350mV current-mode differential swing across a 100-ohm terminated line, which inherently minimizes EMI, crosstalk, and power compared with single-ended signaling such as LVTTL. The repeater's low deterministic and random jitter budget preserves timing margin across the full 10-way fan-out, which is critical in clock-tree design where each output contributes skew to the timing budget.
Typical applications include backplane clock and data distribution, point-to-point LVDS link extension with 100-ohm terminated lines, high-speed data fan-out in industrial automation, medical imaging receivers, and telecommunications line cards where a single source must drive many loads without signal degradation.
A key design consideration: terminate each LVDS output line with a 100-ohm resistor at the far end, and keep the total capacitive loading balanced across outputs to preserve the 100ps inter-channel skew specification.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for MAX9150EUI+ — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MAX9150CUI+
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MAX9150EUI
✅ Drop-In📋 Reference alternative (not in catalog)
MAX9150EUI+T
✅ Drop-In📋 Reference alternative (not in catalog)
MAX9150EUI+ Specifications
| Function | 10-Port LVDS Repeater (Buffer/ReDriver) |
| Input Channels | 1 LVDS differential input |
| Output Channels | 10 LVDS differential outputs |
| Guaranteed Data Rate | 400 Mbps |
| Total Jitter | 120 ps p-p max (deterministic and random) |
| Inter-Channel Skew | 100 ps max |
| Shutdown Supply Current | 60 uA |
| Supply Current (Active) | 160 mA |
| Supply Voltage | 3 V (3.0 V to 3.6 V class) |
| LVDS Standard | Conforms to EIA/TIA-644 |
| Operating Temperature | -40C to +85C |
| Package | 28-pin TSSOP |
| Mounting Type | Surface Mount (gull-wing) |
| Termination | 100 ohm external termination per LVDS line |
| Category | Interface - Signal Buffers, Repeaters, Splitters |
MAX9150EUI+ 28-pin tssop Pin Configuration Guide
Pin configuration for MAX9150EUI+ (28-pin tssop package). Pin numbering, functions, and connection diagrams are defined in the manufacturer datasheet. Refer to it for the exact footprint and soldering guidelines.
No detailed pinout data available for MAX9150EUI+.
Refer to the datasheet for full pin configuration.
Typical Applications
MAX9150EUI+ is suitable for 6 applications: Backplane Clock Distribution, Point-to-Point LVDS Link Extension, Industrial Automation Fan-Out, Medical Imaging Signal Distribution, Telecommunications Line Cards, High-Speed Data Fan-Out in Test Equipment.
Backplane Clock Distribution
In modular industrial and telecom backplanes, a single central clock must reach every slot without degradation. The MAX9150EUI+ accepts one LVDS clock input and regenerates ten LVDS output pairs with a guaranteed 400Mbps rate, 120ps p-p total jitter, and only 100ps maximum inter-channel skew, so all ten slots receive essentially simultaneous clock edges. Its EIA/TIA-644 compliance guarantees interoperability with standard LVDS PLLs and FPGA clock inputs, and its low-power differential signaling minimizes EMI across the backplane. Length-match output traces and terminate each pair with 100 ohms at the receiving end to preserve the skew budget.
Recommended
Point-to-Point LVDS Link Extension
Long LVDS runs across cables, connectors, and backplanes accumulate jitter and attenuate edges beyond what a receiver can tolerate. Placing the MAX9150EUI+ mid-link redrivers the signal: the input stage re-slices the degraded waveform and the output stage launches a fresh ~350mV LVDS swing into the next 100-ohm terminated segment. With 120ps p-p maximum total jitter and 400Mbps guaranteed throughput, each repeater stage adds well-understood timing cost, letting designers cascade segments with calculable margin. The 60uA shutdown current also lets unused links be power-gated via system firmware.
Recommended
Industrial Automation Fan-Out
PLCs, motion controllers, and vision systems distribute encoder counts, trigger pulses, and reference clocks to many axes simultaneously. The MAX9150EUI+ fans a single LVDS trigger or clock to ten axis modules with 100ps maximum inter-channel skew, which directly reduces the uncertainty between synchronized motion axes. Its -40C to +85C industrial temperature rating matches factory floor ambient conditions, and differential signaling rejects the high motor-drive noise typical of these cabinets. The 28-pin TSSOP conserves PCB area inside dense I/O cards compared with discrete fan-out buffers.
Recommended
Medical Imaging Signal Distribution
Ultrasound, CT, and digital X-ray front ends distribute sampling clocks from one low-phase-noise source to many analog-front-end chips. The MAX9150EUI+'s 120ps p-p total jitter limit keeps clock tree noise from converting into aperture jitter at the ADCs, protecting spurious-free dynamic range, while 100ps channel skew preserves simultaneous sampling alignment across channels. Operating at 3.0V to 3.6V from a clean analog rail with 0.1uF local decoupling, the device integrates into noise-sensitive imaging boards without adding switching noise, unlike a clock-multiplying PLL solution.
Recommended
Telecommunications Line Cards
Telecom shelf architectures distribute a system reference clock from a central timing card to every line card. The MAX9150EUI+ repeats the incoming LVDS reference and delivers ten disciplined outputs with 100ps maximum skew, supporting SONET/SDH-style timing distribution where skew between cards must stay inside synchronizer capture windows. Conformance to EIA/TIA-644 ensures clean integration with standard LVDS PHYs and FPGAs on the line card. The 160mA active supply current is acceptable on line-card power budgets, and 60uA shutdown supports standby power compliance.
Recommended
High-Speed Data Fan-Out in Test Equipment
Bench instruments, logic analyzers, and automated test equipment often need one fast trigger or sample clock routed to many measurement channels without skew-induced timing error. The MAX9150EUI+ provides a deterministic 100ps maximum inter-channel skew at 400Mbps, so channel-to-channel timing alignment is known and calibratable. Its 28-pin TSSOP footprint fits dense probe-front-end boards, and the EIA/TIA-644-compliant outputs drive 100-ohm terminated coax-to-board transitions cleanly. Length-match the ten output pairs and keep stubs under 5mm to hold the datasheet skew figure at the connectors.
Recommended
Recommended Products Summary
Engineering reference data for MAX9150EUI+ — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MAX9150CUI+ | MAX9150EUI | MAX9150EUI+T |
|---|---|---|---|---|
| Package | 28-pin TSSOP | 28-pin TSSOP - same | 28-pin TSSOP - same | 28-pin TSSOP - same |
| Brand | Analog Devices (Maxim Integrated) | Analog Devices | Analog Devices (Maxim) | Analog Devices |
| Data Rate | 400 Mbps guaranteed | 400 Mbps | 400 Mbps | 400 Mbps |
| Total Jitter | 120 ps p-p max | 120 ps p-p max | 120 ps p-p max | 120 ps p-p max |
| Inter-Channel Skew | 100 ps max | 100 ps max | 100 ps max | 100 ps max |
| Output Ports | 10 LVDS outputs | 10 LVDS outputs | 10 LVDS outputs | 10 LVDS outputs |
| Operating Temperature | -40C to +85C | 0C to +70C | -40C to +85C | -40C to +85C |
| Shutdown Current | 60 uA | 60 uA | 60 uA | 60 uA |
| Supply Current (Active) | 160 mA | 160 mA | 160 mA | 160 mA |
Key Differentiators
- Ten integrated output ports in one package (vs MAX9157)
- Guaranteed 100ps inter-channel skew (vs MAX9157)
- Ultra-low 120ps p-p total jitter with industrial temperature rating (vs MAX9150CUI+)
- Trade-off: 160mA active supply current (vs MAX9157)
Design Notes
Terminate every LVDS output transmission line with a 100-ohm resistor at the far (receiver) end, as required by the EIA/TIA-644 standard. Unguarded stubs longer than about 5mm cause reflections that consume the 120ps jitter budget. Length-match the ten output pairs to each other (target skew < 25ps from PCB) so that the device's guaranteed 100ps inter-channel skew dominates the total, and route pairs over a continuous reference plane with a solid ground under the 28-pin TSSOP.
The MAX9150EUI+ draws up to 160mA active supply current from a 3.0V to 3.6V rail, so worst-case dissipation is about 0.58W (Estimated: 3.6V x 160mA). No heatsink is needed, but provide a low-impedance supply: a 10uF bulk capacitor plus a 0.1uF ceramic capacitor within 5mm of the VCC pin. The 60uA shutdown mode lets firmware power-gate idle links - hold the shutdown pin asserted during standby and allow one output-edge-time for wake before the first clock.
Do not leave unused output pairs unterminated on long traces - tie them off or leave short and unterminated near the device to avoid radiating reflections. Do not substitute the commercial-grade MAX9150CUI in designs that must operate below 0C; the E suffix (-40C) is required for industrial ambient. Finally, confirm the exact pinout order of the LVDS input pair and ten output pairs from the current Analog Devices datasheet revision before finalizing the footprint - never copy footprints from legacy Maxim-era documents.
Place the MAX9150EUI+ close to the LVDS source entry connector to minimize input-pair degradation, and fan the ten outputs out symmetrically on opposite sides of the TSSOP-28 to balance trace lengths. Keep clock pairs away from switching-regulator inductors and motor-drive wiring; although LVDS is differential and noise-tolerant, the 120ps jitter specification is measured under clean conditions and additive crosstalk is not covered by the datasheet guarantee.
Compliance Information
The + suffix in Analog Devices ordering codes conventionally denotes lead-free/RoHS-compliant packaging, but explicit RoHS/REACH certification statements were not present in the retrieved web data; confirm on the Analog Devices product page before export-controlled production.
