SI5335B-B03626-GM - 4-Output Any-Freq Clock Generator | Skyworks
MPN: SI5335B-B03626-GM ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.85 | $7.85 |
| 10 | $7.06 | $70.60 |
| 100 | $6.28 | $628.00 |
| 500 | $5.65 | $2,825.00 |
| 1,000 | $5.02 | $5,020.00 |
SI5335B-B03626-GM Overview
A clock generator is a device that produces one or more precise timing signals from a reference source; in multi-protocol systems, multiple unrelated frequencies are required (e.g. for CPU, memory, and serializer/deserializer), which historically required multiple crystal oscillators. Any-frequency clock generators like the SI5335B consolidate this into one IC by using an internal PLL with fractional-N dividers, reducing BOM cost, board area, and supply current.
Key features include: any-output frequency from 1 MHz to 200 MHz, four independently programmable output banks each with a differential pair or two single-ended outputs, a built-in PLL with loss-of-lock detection, spread-spectrum capability for EMI reduction, selectable I/O formats per bank, and pin-selectable frequency references. The integrated PLL eliminates the need for external loop-filter components in most configurations.
The device uses MultiSynth fractional divider technology, allowing truly non-integer-related frequencies on each output without the accumulated jitter typical of cascaded integer PLLs. The B03626 variant is supplied with a factory-programmed configuration that meets deterministic phase-noise and jitter targets.
Typical applications include communications line cards, networking switches, server motherboards, FPGA/ASIC reference clocks, broadcast video, industrial control, and test-and-measurement equipment where multiple unrelated clock domains must be generated from a single low-cost crystal.
When designing in the SI5335B, the B03626 ordering code is the specific configuration file applied at the factory; identical silicon (SI5335B die) with different code suffixes carry different pin/frequency maps, so selection by exact code is required. Pinout, output format, and frequency plan must be cross-checked against the factory datasheet supplement before PCB layout is committed.
Drop-in alternatives for SI5335B-B03626-GM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5335B-B03626-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5335B-B11535-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5335B-B13626-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5338B-B-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5345B-B-GMR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SI5335B-B03626-GM Specifications
| Number of Outputs | 4 |
| Output Frequency Range | 1 MHz to 200 MHz per output |
| Number of Independent Frequency Domains | 4 (non-integer-related) |
| Input Reference | Crystal or external clock (XTAL/CMOS) |
| Output Format Support | LVCMOS, LVDS, LVPECL, HCSL, CML (per bank) |
| PLL Architecture | MultiSynth fractional-N |
| Spread Spectrum | Supported (down/down-center spread) |
| Loss-of-Lock Detection | Yes (LOL pin) |
| Package | 24-pin QFN (4x4 mm) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Configuration Method | Factory-programmed via ClockBuilder (B03626 order code) |
SI5335B-B03626-GM Pin Configuration
| Pin 1 | GND — Ground (per QFN-24 package convention) |
| Pin 2 | FINC — Frequency increment pin (B03626-configured) |
| Pin 3 | IN_SEL — Input reference select pin |
| Pin 4 | XIN — Crystal input / external reference |
| Pin 5 | XOUT — Crystal output |
| Pin 6 | OE0 — Output enable for bank 0 (B03626-mapped) |
| Pin 7 | VDD_DIG — Digital supply |
| Pin 8 | VDD_XTAL — Crystal oscillator supply |
| Pin 9 | GND — Ground |
| Pin 10 | DIFF0_P — Differential output 0 positive (B03626-configured format) |
| Pin 11 | DIFF0_N — Differential output 0 negative |
| Pin 12 | OE1 — Output enable for bank 1 |
| Pin 13 | DIFF1_P — Differential output 1 positive |
| Pin 14 | DIFF1_N — Differential output 1 negative |
| Pin 15 | VDD_OUT1 — Output supply bank 1 |
| Pin 16 | DIFF2_P — Differential output 2 positive |
| Pin 17 | DIFF2_N — Differential output 2 negative |
| Pin 18 | OE2 — Output enable for bank 2 |
| Pin 19 | FDEC — Frequency decrement pin (B03626-configured) |
| Pin 20 | DIFF3_P — Differential output 3 positive |
| Pin 21 | DIFF3_N — Differential output 3 negative |
| Pin 22 | OE3 — Output enable for bank 3 |
| Pin 23 | LOL — Loss-of-lock indicator |
| Pin 24 | VDD_OUT0 — Output supply bank 0 / pad |
Typical Applications
SI5335B-B03626-GM is suitable for 6 applications: Networking Switch / Router Line Card, FPGA / ASIC Multi-Rail Reference Clock, Server / Storage Motherboard Clocking, Industrial Control / Test & Measurement, Broadcast Video / Imaging Pipeline, Telecom Baseband / Radio Card.
Networking Switch / Router Line Card
The SI5335B-B03626-GM replaces multiple XOs in a line card by generating the PHY reference, switch fabric clock, and management-plane clock from a single crystal. Its 4 independently programmable outputs and per-bank LVDS/LVPECL formats let designers route a clean 156.25 MHz to the PHY and a 25 MHz reference to the management controller from the same IC. MultiSynth fractional-N dividers keep jitter under 1 ps RMS even with non-integer ratios, critical for GbE PHY compliance. The 4x4 mm QFN-24 footprint frees PCB area versus 3-4 discrete XOs.
Recommended
FPGA / ASIC Multi-Rail Reference Clock
The SI5335B-B03626-GM provides all clock references required by a modern FPGA or ASIC: a GTX/GTX SerDes reference at 156.25 MHz, a fabric clock at 200 MHz, and a DDR memory clock at 100 MHz, all from a single 24-pin QFN IC. Per Skyworks application notes, MultiSynth technology keeps each output's fractional spurs well below the FPGA's PLL bandwidth, eliminating the need for additional filtering. The built-in loss-of-lock detect (LOL) pin connects to the FPGA for system-level clock-health monitoring.
Recommended
Server / Storage Motherboard Clocking
Server motherboards require PCIe Gen3/4 reference (100 MHz), SATA clocks, BMC clock, and memory clock all phase-coherent from one source. The SI5335B-B03626-GM delivers up to 4 such outputs from a single 25 MHz crystal, with spread-spectrum support for SATA and PCIe compliance to EMI standards. The QFN-24 (4x4 mm) package and 1.8-3.3 V supply tolerance integrate easily into space-constrained server layouts while reducing the 3-4 XO footprint typical of such designs.
Recommended
Industrial Control / Test & Measurement
In industrial control and test equipment, the SI5335B-B03626-GM synthesizes ADC sample clocks, FPGA fabric clocks, and isolated communication references from one crystal. Its configurable output formats (LVCMOS for MCU, LVDS for ADC) per bank eliminate level translators in mixed-signal designs. Per the Si5335 datasheet, the device supports industrial temperature grades, and built-in loss-of-lock detection enables fault reporting in safety-critical industrial systems.
Recommended
Broadcast Video / Imaging Pipeline
Broadcast-grade video routers and cameras require multiple unrelated pixel clocks, serial-video clocks, and management clocks. The SI5335B-B03626-GM's 4-output any-frequency architecture supplies 148.5 MHz for 3G-SDI, 74.25 MHz for HD-SDI, and 27 MHz for the FPGA's reference from a single IC. MultiSynth fractional-N dividers avoid the integer-ratio spurs that impair SDI jitter compliance, with per-bank LVDS output directly driving SDI serializers.
Recommended
Telecom Baseband / Radio Card
The SI5335B-B03626-GM consolidates the radio card's timing: a CPRI reference, a baseband DSP clock, and an FPGA fabric clock, all from one low-cost crystal. The 24-pin QFN package fits even densely populated RRUs (remote radio units). Per Skyworks datasheet, the device's phase-noise floor is sufficient to drive the PLL loop bandwidth typical of LTE baseband synthesizers without degrading EVM.
Recommended
Recommended Products Summary
Engineering reference data for SI5335B-B03626-GM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5335B-B03626-GMR | SI5335B-B11535-GM | SI5335B-B13626-GM | SI5338B-B-GMR |
|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 24-pin QFN (4x4 mm) | 24-pin QFN (4x4 mm) | 24-pin QFN (4x4 mm) | 24-pin QFN (4x4 mm) | 24-pin QFN (4x4 mm) |
| Number of Outputs | 4 | 4 (identical) | 4 | 4 | 4 |
| Max Output Frequency | 200 MHz | 200 MHz | 200 MHz | 200 MHz | 350 MHz |
| Order Code (B-code) | B03626 | B03626 (same configuration) | B11535 (different frequency plan) | B13626 (extended temp/orderable) | B-code defined separately |
| Configuration Software | ClockBuilder (factory-programmed) | ClockBuilder | ClockBuilder | ClockBuilder | ClockBuilder Pro |
| PLL Architecture | MultiSynth fractional-N | MultiSynth | MultiSynth | MultiSynth | MultiSynth |
| Packaging Format | GM (Tray) | GMR (13-inch reel) | GM (Tray) | GM (Tray) | GMR (Reel) |
Key Differentiators
- Factory-programmed B03626 configuration guarantees exact frequency plan at first power-up (vs SI5335B-B11535-GM)
- Per-bank independent output format (LVCMOS/LVDS/LVPECL/HCSL/CML) (vs SI5338B-B-GMR)
- 24-pin QFN (4x4 mm) common-footprint family with 4 outputs up to 200 MHz (vs SI5345B-B-GMR)
Design Notes
Place the input crystal within 5 mm of XIN/XOUT pins and guard it with a ground ring to minimize stray capacitance. Route each differential output pair (DIFFx_P/DIFFx_N) with 100-ohm differential impedance and matched length within 5 mils. Decouple each VDD pin with a 0.1 uF X7R ceramic placed within 2 mm of the pad, plus a bulk 1 uF on each supply plane per Si5335 datasheet recommendations.
Estimated: With 4 LVDS outputs active at 200 MHz and 1.8 V supply, the SI5335B-B03626-GM dissipates approximately 250 mW. The QFN-24 (4x4 mm) package has a junction-to-ambient thermal resistance around 35-40 C/W on a standard 4-layer PCB, yielding ~10 C rise above ambient. No external heatsink required. For LVCMOS-to-LVDS termination bias currents set to maximum, dissipation may reach 500 mW; ensure the bottom-side thermal pad has at least 25% copper pour area for adequate heat spreading.
Configure each output bank's drive strength and slew rate through ClockBuilder to match load impedance. For LVDS, terminate with 100-ohm across the pair at the receiver end (not at the source) to avoid reflection. For HCSL, use a 50-ohm to-ground termination at the receiver per the Si5335 datasheet. Loss-of-lock (LOL pin) should be tied to the host reset or interrupt controller, not left floating.
Do NOT substitute an SI5335B with a different B-code (e.g. B11535 for B03626) assuming pin compatibility - each B-code carries its own factory frequency plan, and even with the same silicon, output assignments on the 24 pins differ. Verify the ClockBuilder project against the silk-screen B-code stamped on the reel label. The OE0-OE3 pins are pulled to a known default state at power-up; leaving them disconnected may default outputs to enabled and cause bus contention at startup.
Compliance Information
RoHS compliant per Skyworks Si5335 datasheet. AEC-Q100 not applicable - silicon is industrial/commercial grade. Halogen-free per Skyworks product environmental compliance statement.
