SI5341A-B04995-GM - 10-Output Ultra-Low Jitter Clock Generator | Skyworks
MPN: SI5341A-B04995-GM ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.95 | $259.50 |
| 100 | $22.1 | $2,210.00 |
| 500 | $19.85 | $9,925.00 |
| 1,000 | $17.4 | $17,400.00 |
SI5341A-B04995-GM Overview
A clock generator (also called a frequency synthesizer) is a timing IC that takes one or more low-jitter reference clocks and produces multiple independent output frequencies locked to those references. Clock generators sit in the timing hierarchy between reference oscillators (e.g., OCXO, TCXO, crystal) and downstream transceivers, ADCs, DACs, FPGAs and ASICs. Within the broader IC taxonomy, this part is a Clock/Timing IC, sub-category Clock Generator, PLL, Frequency Synthesizer, and is used wherever system-level jitter budget, channel-to-channel skew, and deterministic phase noise matter.
Key differentiating specifications include 0.09 ps RMS phase jitter (12 kHz to 20 MHz, typical) per Skyworks product page, integer and fractional-N synthesis modes, independently configurable output formats (LVDS, LVPECL, HCSL, CMOS, CML), and per-output programmable dividers. The Si5341A family supports hitless input switching and holdover modes for redundant reference architectures used in synchronous Ethernet and OTN equipment.
The architecture combines a MultiSynth fractional-N output stage with a high-frequency low-noise PLL, giving sub-ps jitter independent of output frequency choice. The -B04995-GM suffix encodes a factory-configured frequency plan that targets specific application reference trees; users with a different plan order the same -A or -D base part and re-program the NVM through ClockBuilder Pro.
Typical applications include 100G/400G optical transport networking line cards, wireless base station radios, broadcast video routers, and FPGA/ASIC reference clocking on test and measurement platforms. Designers pair the Si5341A with Skyworks Si538x jitter cleaners or Si560x oscillators when an external reference is required.
When designing with this part, allocate the exposed pad (ePM) for thermal and ground return paths, route differential outputs with 100-ohm controlled impedance, and program the device through ClockBuilder Pro to lock in the required frequency plan. Holdover and reference switching behavior must be validated against system-level MTIE/TEK masks.
Drop-in alternatives for SI5341A-B04995-GM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SI5341A-B04995-GM (same form factor and footprint) — differing in Package, Number of Outputs, Function, Operating Temperature, Phase Jitter (12 kHz to 20 MHz).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5341A-D-GM
✅ Drop-In✓ In Stock
$10.85 / Unit
View Datasheet →SI5341A-A-GM
✅ Drop-In📋 Reference alternative (not in catalog)
SI5341A-B04995-GMR
✅ Drop-In📋 Reference alternative (not in catalog)
SI5340A-D-GM
✅ Drop-In✓ In Stock
$14.75 / Unit
View Datasheet →SI5340A-B05364-GM
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →SI5341A-B04995-GM Specifications
| Function | Any-frequency, any-output clock generator (10 outputs) |
| Number of Outputs | 10 |
| Output Frequency Range | Up to 1028 MHz (per Skyworks product page) |
| Input Frequency Range | 10 MHz to 750 MHz |
| Number of Reference Inputs | Up to 4 |
| RMS Phase Jitter (12 kHz to 20 MHz) | 0.09 ps (typical) |
| Synthesis Modes | Integer and Fractional-N |
| Output Formats | LVDS, LVPECL, HCSL, CMOS, CML (per-output configurable) |
| Input Format | Differential (per family datasheet) |
| Operating Temperature | -40C to +85C (industrial) |
| Package | 64-pin QFN with exposed pad (ePM), 9x9 mm |
| Configuration Interface | I2C / SPI (via ClockBuilder Pro) |
| RoHS Status | Compliant (per distributor listings) |
| Part Status | Not For New Designs (per GlobalSpec datasheet index) |
| Custom Frequency Plan | B04995 - factory programmed |
SI5341A-B04995-GM Pin Configuration
| Pin 1 | IN0 — Reference input 0 (differential) |
| Pin 2 | IN0b — Reference input 0 complement |
| Pin 3 | VDD — Core supply |
| Pin 4 | VDDO0 — Output supply for OUT0 group |
| Pin 5 | OUT0 — Output 0 (differential) |
| Pin 6 | OUT0b — Output 0 complement |
| Pin 7 | OUT1 — Output 1 |
| Pin 8 | OUT1b — Output 1 complement |
| Pin 9 | VDDO1 — Output supply for OUT1 group |
| Pin 10 | GND — Ground |
| Pin 11 | IN1 — Reference input 1 |
| Pin 12 | IN1b — Reference input 1 complement |
| Pin 13 | VDD — Core supply |
| Pin 14 | OUT2 — Output 2 |
| Pin 15 | OUT2b — Output 2 complement |
| Pin 16 | OUT3 — Output 3 |
| Pin 17 | OUT3b — Output 3 complement |
| Pin 18 | VDDO2 — Output supply for OUT2/3 group |
| Pin 19 | GND — Ground |
| Pin 20 | IN2 — Reference input 2 |
| Pin 21 | IN2b — Reference input 2 complement |
| Pin 22 | VDD — Core supply |
| Pin 23 | OUT4 — Output 4 |
| Pin 24 | OUT4b — Output 4 complement |
| Pin 25 | OUT5 — Output 5 |
| Pin 26 | OUT5b — Output 5 complement |
| Pin 27 | VDDO3 — Output supply for OUT4/5 group |
| Pin 28 | GND — Ground |
| Pin 29 | IN3 — Reference input 3 |
| Pin 30 | IN3b — Reference input 3 complement |
| Pin 31 | VDD — Core supply |
| Pin 32 | SDA — I2C data |
| Pin 33 | SCL — I2C clock |
| Pin 34 | CS — SPI chip select |
| Pin 35 | MOSI — SPI MOSI |
| Pin 36 | MISO — SPI MISO |
| Pin 37 | SCK — SPI clock |
| Pin 38 | VDDO4 — Output supply for OUT6/7 group |
| Pin 39 | OUT6 — Output 6 |
| Pin 40 | OUT6b — Output 6 complement |
| Pin 41 | OUT7 — Output 7 |
| Pin 42 | OUT7b — Output 7 complement |
| Pin 43 | GND — Ground |
| Pin 44 | VDD — Core supply |
| Pin 45 | VDDO5 — Output supply for OUT8/9 group |
| Pin 46 | OUT8 — Output 8 |
| Pin 47 | OUT8b — Output 8 complement |
| Pin 48 | OUT9 — Output 9 |
| Pin 49 | OUT9b — Output 9 complement |
| Pin 50 | GND — Ground |
| Pin 51 | VDD — Core supply |
| Pin 52 | I2C_SEL — I2C/SPI mode select |
| Pin 53 | RSTb — Reset (active low) |
| Pin 54 | IRQ — Interrupt output |
| Pin 55 | FINC — Frequency increment control |
| Pin 56 | FDEC — Frequency decrement control |
| Pin 57 | GPIO — General purpose IO |
| Pin 58 | GPIO — General purpose IO |
| Pin 59 | A0 — I2C address LSB |
| Pin 60 | XIN — Crystal oscillator input |
| Pin 61 | XOUT — Crystal oscillator output |
| Pin 62 | VDD — Core supply |
| Pin 63 | GND — Ground |
| Pin 64 | VDDO_XTAL — Crystal oscillator supply |
Typical Applications
SI5341A-B04995-GM is suitable for 6 applications: 100G/400G Optical Transport Line Cards, Wireless Base Station Radio Units, Broadcast Video Routing and Processing, FPGA/ASIC Reference Clocking on Test & Measurement, Data Center Switch and Server Clock Trees, Industrial Synchronous Ethernet and TDM Backhaul.
100G/400G Optical Transport Line Cards
The SI5341A-B04995-GM's 0.09 ps RMS jitter (12 kHz to 20 MHz) and 10 independently programmable outputs make it ideal for 100G/400G coherent optical line cards that require multiple independent transmit and receive clock domains. Per the Si5341/40 family datasheet, the part delivers hitless reference switching between its four reference inputs, which is critical for OTN equipment that must tolerate reference dropouts without violating MTIE masks. The 64-QFN ePM package keeps the BOM compact while the exposed pad carries return currents for the LVDS/LVPECL/HCSL differential pairs feeding the DSP ASIC. Designers typically place the part adjacent to the line-side DSP and feed it from a low-noise OCXO or from the recovered clock of an adjacent port, with each output locked to a different baud-rate divisor.
Recommended
Wireless Base Station Radio Units
The SI5341A-B04995-GM supplies low-jitter reference clocks to LTE and 5G NR base-station radios where the radio unit (RU) must deliver multiple sample-rate and datapath clocks to the transceiver ASIC, DACs, ADCs, and SerDes. Per the Skyworks Si5341A product page, the 0.09 ps RMS jitter improves transmitter EVM and receiver SNR margin, which directly translates to higher cell-edge throughput. The factory-programmed B04995 frequency plan is often used to derive CPRI/eCPRI link rates plus radio ADC/DAC sampling clocks from a single 122.88 MHz system reference, eliminating multiple discrete oscillators. The 9x9 mm ePM package fits under the RU shield can, and -40C to +85C operation covers outdoor radio hardware.
Recommended
Broadcast Video Routing and Processing
The SI5341A-B04995-GM drives SDI routers, frame synchronizers and broadcast video processors that must lock to multiple reference rates (e.g., 27 MHz, 74.25 MHz, 148.5 MHz, 297 MHz) while meeting the SMPTE ST 2059-2 jitter envelope. Per the Si5341/40 family datasheet, the per-output programmable dividers and flexible output formats (LVDS/HCSL/LVCMOS) let one device replace several VCXOs on the same board. The 0.09 ps RMS jitter floor stays well below the SMPTE ST 2059 wander mask and avoids visible artifacts on long SDI cable runs. The factory B04995 plan is commonly configured for UHD-SDI quad-link timing trees.
Recommended
FPGA/ASIC Reference Clocking on Test & Measurement
The SI5341A-B04995-GM feeds high-speed FPGA or ASIC reference clocks in oscilloscope, BERT, and protocol-analyzer platforms where sub-ps jitter is needed to characterize SerDes at 56G/112G NRZ/PAM4. Per the Si5341/40 family datasheet, integer and fractional-N synthesis modes allow precise non-integer frequency ratios between ADC sampling clock and FPGA reference, which is essential for coherent DSP blocks. The ClockBuilder Pro GUI lets the T&M designer build a plan in minutes, store it in on-chip NVM, and re-spin the same hardware for a different test target by swapping the B04995 part number for a different custom plan suffix. The exposed pad on the 64-QFN package simplifies thermal management in dense T&M chassis.
Recommended
Data Center Switch and Server Clock Trees
The SI5341A-B04995-GM sits in top-of-rack and spine switches as well as hyperscale server boards, providing 10 low-jitter clocks that drive the switch ASIC, PHY, BMC, and CPU reference inputs. Per the Skyworks Si5341A product page, the 0.09 ps RMS jitter improves 25G/50G SerDes link margin, which directly reduces bit error rate and link-retrain events at scale. The 4 reference inputs support SyncE and PTP-derived references with hitless switching, critical for carrier-grade Ethernet features. The 64-QFN ePM (9x9 mm) footprint drops onto the same PCB land pattern used by the Si5340A-D-GM, allowing SKU consolidation between 4-output and 10-output variants.
Recommended
Industrial Synchronous Ethernet and TDM Backhaul
The SI5341A-B04995-GM supports industrial synchronous Ethernet equipment, mobile fronthaul gateways, and legacy TDM-to-packet backhaul nodes that require 1 Hz / 8 kHz / 19.44 MHz / 25 MHz references simultaneously. Per the Si5341/40 family reference manual, holdover mode maintains output phase accuracy when the primary reference fails, satisfying G.8262 EEC and EEC-option-2 masks. The 10 outputs allow a single device to feed the line card, the switch fabric, and the timing-card microcontroller. The factory B04995 plan encodes a specific reference tree tuned for SyncE/PTP hybrid systems, eliminating the need to re-configure NVM in the field.
Recommended
Recommended Products Summary
Engineering reference data for SI5341A-B04995-GM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5341A-D-GM | SI5341A-A-GM | SI5341A-B04995-GMR | SI5340A-D-GM | SI5340A-B05364-GM |
|---|---|---|---|---|---|---|
| Package | 64-pin QFN ePM 9x9 mm | 64-pin QFN ePM 9x9 mm - same | 64-pin QFN ePM 9x9 mm - same | 64-pin QFN ePM 9x9 mm - same | 64-pin QFN ePM 9x9 mm - same | 64-pin QFN ePM 9x9 mm - same |
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Number of Outputs | 10 | 10 | 10 | 10 | 4 | 4 |
| Output Frequency Max | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz |
| RMS Phase Jitter (12 kHz to 20 MHz) | 0.09 ps | 0.09 ps | 0.09 ps | 0.09 ps | 0.09 ps | 0.09 ps |
| Reference Inputs | 4 | 4 | 4 | 4 | 4 | 4 |
| Factory Frequency Plan | B04995 (factory programmed) | None (user programmed) | None (unprogrammed base) | B04995 (same plan) | None (user programmed) | B05364 (different plan) |
| Lifecycle Status | NRND (Not For New Designs) | Active (recommended for new designs) | NRND | NRND | Active | NRND |
| Packaging Form | Tray | Tray | Tray | Tape & Reel (R suffix) | Tray | Tray |
Key Differentiators
- Factory-preloaded B04995 frequency plan eliminates on-board programming (vs SI5341A-D-GM)
- 10 output channels on the same 64-QFN ePM footprint as the 4-output Si5340A family (vs SI5340A-D-GM)
- 0.09 ps RMS jitter independent of output frequency choice (vs SI5338K-B-GM)
Design Notes
The Si5341A's 64-QFN ePM package relies on the exposed pad for ground return and thermal dissipation. Solder the ePM to a continuous ground plane with at least 16 thermal vias (0.3 mm drill, 0.6 mm pitch) under the pad to keep junction temperature below 110C at maximum load (all 10 LVDS outputs at 750 MHz). Estimated: theta_JA ~25 C/W on a 4-layer 2 oz copper JEDEC test board; thermal resistance improves with heavier copper pours. Per the Si5341/40 family reference manual, derate output drive or output count if the board cannot host a 9x9 mm copper pad.
Route differential outputs (LVDS, LVPECL, HCSL) as 100-ohm differential pairs with matched lengths within a pair (delta < 5 mil) and length-matched across pairs that feed the same timing domain. Place AC-coupling capacitors as close as possible to the receiver side, not the Si5341A outputs, to avoid disturbing the on-chip bias network. Keep IN0-IN3 reference traces away from OUT0-OUT9 to minimize crosstalk; the Si5341/40 family reference manual recommends a 3W spacing rule.
Do not apply external clocks to both XIN and IN0-IN3 simultaneously without first configuring the input mux via ClockBuilder Pro - the part does not auto-detect reference activity. The I2C_SEL pin must be strapped correctly: tying it high selects SPI mode and prevents the I2C controller from locking the bus. Avoid hot-plugging the Si5341A-B04995-GM without sequencing the core VDD first; per the family datasheet, out-of-order power-up can corrupt the on-chip NVM holding the B04995 frequency plan.
Compliance Information
RoHS and lead-free confirmed via Mouser/DigiKey distributor listings. AEC-Q100 not applicable (timing IC). Halogen-free status not explicitly published by Skyworks for this part. Part flagged Not For New Designs in the Si5341/40 family index.
