SI5345A-D-GM - 10-Output Jitter Attenuator, <1028 MHz | Skyworks
MPN: SI5345A-D-GM ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.31 | $42.31 |
| 10 | $38.07 | $380.70 |
| 100 | $33.85 | $3,385.00 |
| 500 | $30.46 | $15,230.00 |
| 1,000 | $27.5 | $27,500.00 |
SI5345A-D-GM Overview
A jitter attenuator is a clock IC that cleans up timing noise from an upstream reference or recovered clock and re-generates a low-jitter output clock for downstream serializers, ADCs, DACs, FPGAs, ASICs, and network PHYs. In the clock-tree hierarchy it sits between a primary reference (XO, OCXO, or recovered clock) and the fan-out clock generators/buffers that feed individual MAC, framer, or transceiver blocks, falling under the broader categories of clock synthesis IC, timing IC, and PLL frequency synthesizer.
The SI5345 family includes Si5345A, Si5345B, Si5345C, and Si5345D variants, all pin-compatible and supported by the ClockBuilder Pro configuration software. The '-D' order code suffix indicates an unprogrammed (blank/prototype) device that ships with default registers and is configured in-circuit via I2C/SPI, while the 'A' revision defines which PLL and synthesizer block layout is used. The 64-QFN exposed-pad package and integrated LDOs simplify board layout, while digital holdover with external crystal support (25 to 54 MHz on XA/XB) maintains frequency accuracy when the input reference is lost.
Typical applications include 100G/400G Ethernet line cards, OTN/optical transport framer clocks, OTU/OTN timing, Synchronous Ethernet (SyncE) and IEEE 1588 PTP node clocks, wireless base-station JESD204B/C clocking, FPGA/ASIC transceivers, and broadcast video reference timing. The 90 fs RMS jitter floor is more than adequate for 56G/112G SerDes, 25G/50G Ethernet PHYs, and high-speed ADC/DAC sampling clocks.
When designing with this part, place the 64-QFN exposed pad over a continuous ground plane with at least four thermal vias to the inner ground layer for lowest theta-JA. Decouple each supply pin (VDD, VDDA, VDDO) with a 100 nF X7R placed within 2 mm of the pad, and follow the ClockBuilder Pro project for register defaults. Holdover stability depends on the external XA/XB crystal; an OCXO reference is preferred for telecom-grade holdover performance.
This page synthesizes distributor pricing, pin-compatible same-family drop-ins, and PCB-layout design notes that complement the manufacturer datasheet and ClockBuilder Pro reference manual, giving engineers an at-a-glance comparison set not found on a single source page.
Drop-in alternatives for SI5345A-D-GM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SI5345A-D-GM (same form factor and footprint) — differing in Package, Output Frequency Range, Function, Configuration Interface, Control Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SI5345A-D-GMR
✅ Drop-In✓ In Stock
$8.75 / Unit
View Datasheet →SI5345A-D04594-GM
✅ Drop-In✓ In Stock
$25.9 / Unit
View Datasheet →SI5345A-D04594-GMR
✅ Drop-In✓ In Stock
$18.1 / Unit
View Datasheet →SI5345A-D10713-GM
✅ Drop-In✓ In Stock
$19.95 / Unit
View Datasheet →SI5344B-D-GM
✅ Drop-In✓ In Stock
$11.05 / Unit
View Datasheet →SI5341B-D-GM
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SI5345A-D-GM Specifications
| Product Type | 10-Channel Any-Frequency Any-Output Jitter Attenuator / Clock Multiplier |
| Series | Si5345 (Si5345A/B/C/D variants) |
| Number of Outputs | 10 |
| Differential Input Frequency Range | 8 kHz to 750 MHz |
| LVCMOS Input Frequency Range | 8 kHz to 250 MHz |
| Differential Output Frequency Range | 100 Hz to 1028 MHz |
| Output RMS Jitter | 90 fs typical (12 kHz to 20 MHz) |
| External Crystal Reference | 25 to 54 MHz (XA/XB pins) |
| Jitter Attenuation Bandwidth | Digitally programmable |
| Architecture | DSPLL with digital holdover |
| Configuration Interface | I2C / SPI (ClockBuilder Pro software) |
| Package | 64-VFQFN Exposed Pad (QFN-64 EP, 9x9 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature Range | -40C to +85C (industrial) |
| Supply Voltage | 1.8 V / 2.5 V / 3.3 V core and I/O (per register config) |
| RoHS Status | Compliant |
| Lead-Free / Halogen-Free | Lead-free per Skyworks product page |
SI5345A-D-GM Pin Configuration
| Pin 1 | IN0 — Differential/LVCMOS clock input 0 |
| Pin 2 | IN0b — Complementary input 0 |
| Pin 3 | IN1 — Differential/LVCMOS clock input 1 |
| Pin 4 | IN1b — Complementary input 1 |
| Pin 5 | IN2 — Differential/LVCMOS clock input 2 |
| Pin 6 | IN2b — Complementary input 2 |
| Pin 7 |
Typical Applications
SI5345A-D-GM is suitable for 7 applications: 100G/400G Ethernet Line Card Clocking, OTN/Optical Transport Network Framer Timing, JESD204B/C ADC and DAC Sampling Clock Generation, Wireless Base Station and Remote Radio Head (RRH), FPGA/ASIC Transceiver Reference Clocking, Broadcast Video and Studio Reference Timing, Industrial Test and Measurement Instrumentation.
100G/400G Ethernet Line Card Clocking
The SI5345A-D-GM is widely used on 100G and 400G Ethernet line cards to generate the multiple low-jitter reference clocks required by switch ASICs, retimers, and 56G/112G SerDes PHYs. Its 90 fs RMS jitter floor is comfortably below the IEEE 802.3bs reference-clock jitter budget, while the 10 independently programmable outputs let one device replace four or five narrower-range clock ICs. The 1.028 GHz output ceiling covers 156.25 MHz, 161.13 MHz, 312.5 MHz, and 644.53 MHz Ethernet reference frequencies in a single silicon, and the digitally programmable jitter attenuation bandwidth lets designers trade off jitter transfer against reference tracking per PHY.
Recommended
OTN/Optical Transport Network Framer Timing
Optical transport network (OTN) framers and OTU cross-connects demand precise OTU1/OTU2/OTU3/OTU4 clock grids that are extremely intolerant of jitter. The SI5345A-D-GM's 90 fs RMS output jitter and digital holdover with external OCXO support on the XA/XB pins preserve framing integrity during primary reference failures, which is mandatory for telecom-grade SyncE and ITU-T G.8273.2 compliance. Ten independently settable outputs let one SI5345A replace a fan-out of narrower PLLs feeding the framer's transmit and receive paths simultaneously.
Recommended
JESD204B/C ADC and DAC Sampling Clock Generation
High-speed JESD204B/C ADCs and DACs require ultra-low-jitter device clocks and SYSREF pulses to meet signal-to-noise ratio targets at multi-GS/s sample rates. The SI5345A-D-GM supplies up to 10 phase-aligned, deterministic outputs whose edge-to-edge skew is tightly controlled, allowing a single IC to fan out to multiple JESD204B subclasses 1/2/3 channels simultaneously. With 90 fs RMS jitter the device contributes negligibly to aperture jitter of the converter, and the programmable jitter bandwidth allows optimization for SYSREF phase-noise requirements.
Recommended
Wireless Base Station and Remote Radio Head (RRH)
4G LTE and 5G NR base stations and remote radio heads require multiple LO and reference clocks across the transceiver chain, including radio carrier frequencies, baseband clocks, and IEEE 1588 PTP timestamps. The SI5345A-D-GM provides the 10 outputs needed for a multi-band RRH design, with differential input support up to 750 MHz accepting recovered clocks from a GPS-disciplined OCXO. Its -40C to +85C industrial temperature range and holdover mode meet the telecom outdoor cabinet specification.
Recommended
FPGA/ASIC Transceiver Reference Clocking
High-end FPGAs and ASICs with embedded multi-gigabit transceivers need reference clocks that meet the strictest phase-noise masks of protocols such as PCIe Gen5, CEI-25G/28G, and 56G/112G PAM4. The SI5345A-D-GM's 10 programmable outputs let one device feed a large FPGA's multiple transceiver banks plus its PLL reference from a single low-jitter source, reducing BOM cost and PCB area. ClockBuilder Pro integration with the FPGA vendor reference designs shortens bring-up time considerably.
Recommended
Broadcast Video and Studio Reference Timing
SDI video routers, broadcast studio timing generators, and audio/video reference distribution require multiple black-burst, word-clock, and AES11 reference outputs with deterministic phase. The SI5345A-D-GM's any-frequency, any-output flexibility supports both NTSC/PAL black-burst frequencies and AES11/Word-Clock audio rates from one IC, while the 90 fs jitter floor meets SMPTE 2059-2 PTP grandmaster timing requirements. Ten outputs cover an entire mid-size studio router with spare channels for future expansion.
Recommended
Industrial Test and Measurement Instrumentation
High-end oscilloscopes, signal analyzers, and arbitrary waveform generators require low-jitter sampling clocks and reference frequencies across multiple internal ADC and DAC channels. The SI5345A-D-GM provides 10 ultra-low-jitter outputs that can be phase-aligned to a common reference, enabling multi-channel phase-coherent acquisition in test equipment. Its industrial -40C to +85C temperature range and digital holdover ensure measurement integrity across environmental variations in production test cells.
Recommended
Recommended Products Summary
Engineering reference data for SI5345A-D-GM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SI5345A-D-GMR | SI5345A-D04594-GM | SI5345A-D04594-GMR | SI5345A-D10713-GM | SI5344B-D-GM |
|---|---|---|---|---|---|---|
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Package | 64-VFQFN EP (QFN-64 EP, 9x9 mm) | 64-VFQFN EP (QFN-64 EP, 9x9 mm) - same | 64-VFQFN EP (QFN-64 EP, 9x9 mm) - same | 64-VFQFN EP (QFN-64 EP, 9x9 mm) - same | 64-VFQFN EP (QFN-64 EP, 9x9 mm) - same | 64-VFQFN EP (QFN-64 EP, 9x9 mm) - same |
| Output Count | 10 | 10 | 10 | 10 | 10 | 4 |
| RMS Jitter (12 kHz-20 MHz) | 90 fs typical | 90 fs typical | 90 fs typical | 90 fs typical | 90 fs typical | 90 fs typical |
| Max Output Frequency | 1028 MHz | 1028 MHz | 1028 MHz (factory-programmed plan) | 1028 MHz (factory-programmed plan) | 1028 MHz (factory-programmed plan) | 1028 MHz |
| Programming | Blank (configured via ClockBuilder Pro) | Blank (configured via ClockBuilder Pro) | Factory pre-programmed plan D04594 | Factory pre-programmed plan D04594 | Factory pre-programmed plan D10713 | Blank (B revision, 4 outputs) |
| Differential Input Range | 8 kHz to 750 MHz | 8 kHz to 750 MHz | 8 kHz to 750 MHz | 8 kHz to 750 MHz | 8 kHz to 750 MHz | 8 kHz to 750 MHz |
| Packaging | Tray (M suffix) | Tape & Reel (R suffix) | Tray (M suffix) | Tape & Reel (R suffix) | Tray (M suffix) | Tray (M suffix) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- 10 independently programmable outputs in a single 64-QFN EP device (vs SI5344B-D-GM)
- 90 fs RMS jitter floor across all 10 outputs (vs Generic any-frequency clock ICs)
- Pin-compatible Si5345/44/42 family for design reuse (vs Si5344 / Si5342 family members)
Design Notes
Estimated: with theta-JA around 28 C/W for the 64-VFQFN-EP package on a 4-layer JEDEC test board (per Skyworks datasheet thermal table), the SI5345A-D-GM dissipates approximately 1.5 W at full load. Total package rise above ambient is therefore about 42 C, so for ambient temperatures above 70 C the exposed pad must be soldered to a ground plane with at least 4 thermal vias (0.3 mm drill, 1 oz copper plating) to keep the junction below 125 C.
Place a 100 nF X7R 0402 decoupling capacitor within 2 mm of each VDD/VDDA/VDDO pin, plus a 10 uF bulk capacitor per supply rail near the package. Route each differential clock output with 100 ohm differential impedance and keep total length below 25 mm to preserve the 90 fs RMS jitter performance; longer runs should be re-characterized with the Si5345-EVB evaluation board.
Solder the central exposed pad to a continuous ground island with at least 4 thermal vias (8 vias for high-output-power plans). Keep all input traces on one side of the package and outputs on the opposite side to minimize crosstalk. Reference the ClockBuilder Pro PCB checklist for the Si5345-EVB evaluation board before committing to a layout, since the recommended stack-up and ground stitching directly impact jitter performance.
Do not assume a generic ClockBuilder Pro project for the Si5345A-D-GM works for the SI5345B or SI5345C/D variants - register maps differ across revisions even though the pinout is shared. Always generate a fresh CBPro project for your specific order code. For holdover applications the XA/XB crystal must be a low-phase-noise 25 to 54 MHz part; a standard AT-cut crystal degrades holdover stability.
Differential outputs should be DC-coupled into a 100 ohm termination network at the receiver; AC-coupling with 0.1 uF capacitors is acceptable for long traces but requires a driver-side bias network. If the receiver input is common-mode sensitive, use the Si5345 receiver-side bias circuit from the Skyworks reference manual to prevent duty-cycle distortion.
Compliance Information
RoHS and REACH compliance confirmed via Skyworks product page and DigiKey listing. Lead-free per Skyworks datasheet. AEC-Q100 not applicable for industrial timing IC; halogen-free status not explicitly stated in the verified data.
