SI5367/68-EVB - Si5367/Si5368 Clock Evaluation Board | Skyworks
MPN: SI5367-68-EVB ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
SI5367-68-EVB Overview
A clock generator evaluation board is a hardware development tool that lets engineers characterize the timing performance of a clock IC before committing to a PCB design. Within the timing hierarchy, it sits under Clock & Timing development tools, which belong to the broader family of semiconductor evaluation kits used alongside clock generators, jitter attenuators, and precision clock multipliers. Evaluation boards expose the IC's inputs, outputs, and configuration interfaces on a ready-made PCB, saving weeks of design effort during device selection and prototyping.
The key feature of this kit is dual-device support: it evaluates both the Si5368 jitter attenuating clock and the Si5367 low-jitter clock multiplier on one platform. The Si5367 accepts four clock inputs ranging from 10 MHz to 707 MHz and generates five frequency-multiplied clock outputs ranging from 2 kHz to 945 MHz, with select frequencies to 1.4 GHz, per the Skyworks Si5367 datasheet. This makes it possible to measure phase noise, jitter, and output format behavior across an extremely wide frequency range without soldering or layout work.
Technically, the Si5367 family uses a digitally controlled oscillator (DCO)-based architecture with uP-programmable loop parameters, allowing any-frequency synthesis from a simple configuration file loaded over the onboard interface. The evaluation board provides the necessary power regulation, input clock conditioning, and output SMA-style connections so that laboratory instruments such as phase-noise analyzers and oscilloscopes can connect directly. Supplied contents per the distributor datasheet listing are the board, a cable, and a CD containing configuration and documentation.
Typical applications include line-card and optical module clock design for SONET/SDH and Ethernet systems, verification of jitter cleanup performance for noisy reference clocks, and lab characterization of frequency plans for FPGA, ASIC, and networking PHY designs requiring sub-picosecond level clocking.
A key design consideration: Skyworks marks this evaluation kit as not recommended for new designs (NRND), so use it for evaluating existing designs or for prototyping with the Si5367/Si5368 devices while considering newer Skyworks Si5xx timing platforms for new product development.
This page synthesizes distributor pricing, lifecycle status, datasheet links, and practical evaluation guidance not consolidated in the manufacturer datasheet.
Drop-in alternatives for SI5367-68-EVB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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Request AlternativesSI5367-68-EVB Specifications (manufacturer-published)
| Main Purpose | Timing, Clock Generator evaluation |
| Evaluated Devices | Si5367 clock multiplier, Si5368 jitter attenuator |
| Supplied Contents | Board, Cable, CD |
| Product Type | Clock Generator Timing Evaluation Board |
| Target IC Input Frequency Range (Si5367) | 10 MHz to 707 MHz |
| Target IC Output Frequency Range (Si5367) | 2 kHz to 945 MHz, select frequencies to 1.4 GHz |
| Target IC Clock Inputs | 4 |
| Target IC Clock Outputs (Si5367) | 5 frequency-multiplied outputs |
| Target IC Architecture | uP-programmable precision clock multiplier (DCO-based) |
| Jitter Attenuation Support | Yes (via Si5368) |
| Recommended for New Designs | No (per Skyworks product page) |
SI5367-68-EVB Interfaces & Connectors
No manufacturer-published interface list is available for SI5367-68-EVB. Refer to the manufacturer documentation for connector and header details.
Refer to the manufacturer documentation for the full expansion header pinout and connector pin numbering.
Typical Applications
SI5367-68-EVB is suitable for 6 applications: SONET/SDH Line Card Clock Evaluation, Optical Module Reference Clock Design, FPGA and ASIC Reference Clocking Prototyping, Jitter Attenuation Lab Characterization, Test and Measurement Instrument Clocking, Legacy Timing Design Maintenance and Second Sourcing.
SONET/SDH Line Card Clock Evaluation
The SI5367/68-EVB fits SONET/SDH line-card development because the Si5367 multiplies a standard 10-707 MHz reference to any line-rate clock up to 945 MHz with low jitter, while the Si5368 on the same board cleans noisy plant references before distribution. Engineers connect the backplane reference to an input SMA, load a frequency plan for OC-192 or STM-64 rates, and measure phase noise directly at the outputs. Because the kit ships with the board, cable, and CD, a lab can begin jitter characterization within minutes of unboxing. The main performance consideration is that the Si5367 multiplies without attenuation, so input reference jitter must be budgeted separately or routed through the Si5368 path first.
Recommended
Optical Module Reference Clock Design
Optical transceiver modules such as XFP, SFP+, and QSFP designs need a precise reference clock for their CDR and gearbox ICs, and the SI5367/68-EVB lets module engineers validate frequency plans before layout. The Si5367 accepts four inputs from 10 MHz to 707 MHz, so a module can switch between a low-cost crystal reference and a recovered line clock, and the board exposes all five outputs up to 945 MHz (select frequencies to 1.4 GHz) for direct measurement with a phase-noise analyzer. Using the evaluation board avoids multi-week spin cycles on tiny module PCBs where clock sections are hard to probe. The trade-off is that board-level jitter results include evaluation-board contributions, so final validation should repeat key measurements on the actual module layout.
Recommended
FPGA and ASIC Reference Clocking Prototyping
High-speed FPGA and ASIC prototypes frequently require non-standard reference frequencies, and the SI5367/68-EVB addresses this with the uP-programmable Si5367, whose output spans 2 kHz to 945 MHz and select frequencies to 1.4 GHz. Designers load a custom frequency plan over the board interface, verify the resulting clock with an oscilloscope or spectrum analyzer, and only then fix the frequency plan in production hardware. This evaluation flow catches DCO-range and loop-bandwidth problems early, when they cost hours instead of weeks. The board also demonstrates how many of the four inputs (10-707 MHz each) the system can realistically switch between, which informs clock-tree redundancy decisions in the final FPGA or ASIC design.
Recommended
Jitter Attenuation Lab Characterization
The SI5367/68-EVB doubles as a jitter-attenuation characterization platform because it also supports the Si5368, a jitter-attenuating clock device. Engineers inject a deliberately noisy reference - for example a recovered clock with Allan deviation or jitter beyond spec - into the Si5368 path and observe the cleaned output on a phase-noise analyzer. Per the Skyworks kit description, the board supports simplified evaluation of the Si5368 jitter attenuating clock alongside the Si5367 multiplier, so both clean and raw multiplication paths can be compared side by side on one PCB. This makes it easy to quantify how much jitter budget the attenuator recovers and to set realistic input-reference specifications for the production design.
Recommended
Test and Measurement Instrument Clocking
Test and measurement instruments benefit from low-jitter, arbitrary-frequency sampling clocks, and the SI5367/68-EVB provides a fast way to qualify the Si5367 for that role. The 10 MHz to 707 MHz input range accepts standard lab references such as a 10 MHz rubidium or ovenized oscillator distribution, and outputs anywhere from 2 kHz to 945 MHz cover ADC and DAC sampling requirements; select frequencies reach 1.4 GHz for high-speed converters. Because the kit includes the board, cable, and CD, an instrument team can run frequency-plan experiments in a single afternoon rather than waiting for a custom PCB. Note that the Si5367 multiplies without jitter attenuation, so the lab reference quality directly sets the output phase-noise floor.
Recommended
Legacy Timing Design Maintenance and Second Sourcing
Because the SI5367/68-EVB is NRND, one of its most practical current uses is maintaining and qualifying legacy designs that already contain Si5367 or Si5368 devices. Manufacturers replacing failing units or requalifying an old line card can use the board, cable, and CD supplied with the kit to verify that replacement ICs or revised firmware frequency plans behave identically to the original qualification units. The board reproduces the datasheet operating conditions - four inputs at 10-707 MHz and outputs to 945 MHz (1.4 GHz select) - allowing regression measurements against archived phase-noise plots. Skyworks explicitly notes the kit is not recommended for new designs, so findings should focus on sustaining engineering rather than new product introduction.
Recommended
Recommended Products Summary
Engineering reference data for SI5367-68-EVB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product |
|---|---|
| Package | Evaluation board (no IC package) |
| Brand | Skyworks Solutions |
| Devices Evaluated | Si5367 + Si5368 (dual-device kit) |
| Input Frequency Range | 10 MHz to 707 MHz (4 inputs) |
| Output Frequency Range | 2 kHz to 945 MHz, select to 1.4 GHz (5 outputs) |
| Jitter Attenuation | Yes (Si5368 path) |
| Supplied Contents | Board, Cable, CD |
| Lifecycle Status | NRND (not recommended for new designs) |
Key Differentiators
- Dual-device evaluation on one board (vs Single-device clock evaluation kits)
- Any-frequency output coverage (vs Fixed-frequency clock evaluation boards)
- Honest lifecycle trade-off (vs Active-generation Skyworks timing kits)
Design Notes
Confirm lifecycle before building a design flow around this kit. Skyworks explicitly states the SI5367/68-EVB is not recommended for new designs. Use it for evaluating the Si5368 jitter attenuating clock and Si5367 low-jitter clock multiplier in existing designs, but plan new-product validation on Skyworks' current evaluation kits for the successor timing family, otherwise you risk an unsupportable lab dependency late in a program.
Remember that the Si5367 multiplies without jitter attenuation. When measuring on the evaluation board, inject a clean reference (10-707 MHz) or route through the Si5368 path; output phase noise will otherwise include the integrated jitter of the input source scaled by 20*log10(N) of the multiplication ratio. Use a low-phase-noise lab reference and short, high-quality SMA cables to keep board-level results representative of the IC itself.
Verify the board supply requirement before powering the kit; the board power supply voltage is not stated in the retrieved data and must be confirmed on the Skyworks kit page or supplied documentation before first power-up. Apply the correct, current-limited supply and confirm input clock amplitude against the Si5367 datasheet input requirements (within the 10-707 MHz range) to avoid damaging the device under test.
Compliance Information
Compliance data for the SI5367/68-EVB evaluation board was not present in the retrieved distributor or manufacturer data.