SN74AHC373PWR - Octal Transparent D-Type Latch | TI | 20-TSSOP
MPN: SN74AHC373PWR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.55 | $0.55 |
| 10 | $0.47 | $4.70 |
| 100 | $0.35 | $35.00 |
| 500 | $0.27 | $135.00 |
| 1,000 | $0.22 | $220.00 |
| 3,000 | $0.17 | $510.00 |
SN74AHC373PWR Overview
A latch is a sequential storage element that captures data when the latch-enable is asserted and holds it transparently or in storage mode. As a member of the AHC (Advanced High-speed CMOS) family, this device is pin-compatible with the HC (High-speed CMOS) logic family while delivering lower static power and faster switching at 5V operation. The latches occupy a position in the logic hierarchy between simple flip-flops and bus-oriented register files, making them ideal for address/data bus demultiplexing, I/O port expansion, and state retention in microcontroller-based systems.
Key features include a typical propagation delay of 8.5 ns at 5V, support for +/-8 mA output drive, and ESD protection exceeding JESD 22 (2000V human-body model, 200V machine model, 1000V charged-device model). The device offers low power consumption with a typical quiescent current of 4 uA, supports +/-50 mA bus-hold and bus-drive, and provides true 5V tolerant inputs on a 2V-5.5V supply rail.
Internally, the SN74AHC373 uses eight transparent D latches each with a 3-state output buffer. When LE is HIGH, the latch is transparent and follows the D input; when LE falls LOW, the value is stored. The OE bar pin enables the output buffers; when OE bar is HIGH, outputs are high-impedance. This architecture is widely used as a simple 8-bit data register or address demultiplexer.
Typical applications include LED driving via 8-bit port expansion, address demultiplexing in microcontroller memory interfaces, bus isolation in mixed-voltage systems, and general-purpose 8-bit data storage. The wide 2V-5.5V range enables direct interfacing between 3.3V MCUs and 5V peripherals.
When designing with this part, ensure that OE bar is properly tied to GND through a pull-down resistor if not actively driven, to prevent floating outputs. Unused D inputs should be tied to VCC or GND to avoid floating CMOS inputs. The TSSOP-20 package has a low thermal resistance suitable for industrial temperature operation.
This page synthesizes distributor pricing, drop-in alternatives from same-brand and cross-brand vendors, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for SN74AHC373PWR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SN74AHC373PWR (same form factor and footprint) — differing in Logic Family, Output Type, Package, Input Type, Logic Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SN74AHC373PW
✅ Drop-In📋 Reference alternative (not in catalog)
SN74AHC373PWRG4
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SN74AHC373DWR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SN74AHCT373PWR
✅ Drop-In📋 Reference alternative (not in catalog)
74VHC373MTCX
✅ Drop-In✓ In Stock
$0.29 / Unit
View Datasheet →MC74VHC373DTR2G
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
SN74AHC373PWR Maximum Ratings & Electrical Characteristics
| Function | Octal Transparent D-Type Latch |
| Logic Family | AHC (Advanced High-speed CMOS) |
| Number of Channels | 1 (8:8) |
| Number of Bits | 8 |
| Output Type | Tri-State (3-state) |
| Input Type | Standard CMOS |
| VCC Supply Voltage | 2 V to 5.5 V |
| Output Current (IOL/IOH) | +/-8 mA at 5V |
| Propagation Delay (tpd) | 8.5 ns typical at 5V |
| Quiescent Current (ICC) | 4 uA typical |
| Operating Temperature | -40 C to +85 C |
| ESD Protection (HBM) | 2000 V per JESD 22 |
| ESD Protection (MM) | 200 V per JESD 22 |
| Latch-up Performance | Exceeds 250 mA per JESD 17 |
| Package | TSSOP-20 (PW) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
SN74AHC373PWR Pin Configuration
| Pin 1 | OE — Output Enable (active-low); HIGH = outputs high-impedance |
| Pin 2 | 1Q — Latch 1 output (3-state) |
| Pin 3 | 1D — Latch 1 data input |
| Pin 4 | 2D — Latch 2 data input |
| Pin 5 | 2Q — Latch 2 output (3-state) |
| Pin 6 | 3Q — Latch 3 output (3-state) |
| Pin 7 | 3D — Latch 3 data input |
| Pin 8 | 4D — Latch 4 data input |
| Pin 9 | 4Q — Latch 4 output (3-state) |
| Pin 10 | GND — Ground |
| Pin 11 | LE — Latch Enable; HIGH = transparent, LOW = hold |
| Pin 12 | 5Q — Latch 5 output (3-state) |
| Pin 13 | 5D — Latch 5 data input |
| Pin 14 | 6D — Latch 6 data input |
| Pin 15 | 6Q — Latch 6 output (3-state) |
| Pin 16 | 7Q — Latch 7 output (3-state) |
| Pin 17 | 7D — Latch 7 data input |
| Pin 18 | 8D — Latch 8 data input |
| Pin 19 | 8Q — Latch 8 output (3-state) |
| Pin 20 | VCC — Supply voltage (2V to 5.5V) |
Typical Applications
SN74AHC373PWR is suitable for 7 applications: Microcontroller Bus Demultiplexing, LED Driving and 7-Segment Display Multiplexing, Bus Isolation in Mixed-Voltage Systems, I/O Port Expansion for Microcontrollers, Address Latch for Legacy x86 Memory Interfaces, Data Register and State Retention, Industrial Control Signal Latching.
Microcontroller Bus Demultiplexing
The SN74AHC373PWR serves as an 8-bit address demultiplexer between a microcontroller and external memory or peripherals. With 8.5 ns propagation delay at 5V and OE bar control for bus sharing, it captures multiplexed address/data lines when LE falls, then holds the address stable for the remainder of the cycle. The 2V-5.5V supply range supports both 3.3V ARM Cortex-M and 5V legacy MCU interfaces without level shifters. Its 8 mA drive comfortably sinks into standard memory and peripheral chip-select inputs, and the TSSOP-20 footprint fits dense 4-layer PCBs. Compared to discrete flip-flop solutions, the integrated octal latch reduces BOM cost, board area, and timing skew across parallel bits.
Recommended
LED Driving and 7-Segment Display Multiplexing
In LED matrix and 7-segment display systems, the SN74AHC373PWR latches digit or segment drive data before the common anode/cathode lines are strobed. Its 8-bit transparent latch captures the parallel segment pattern in one write cycle, freeing the microcontroller to refresh other digits in real time. With +/-8 mA drive at 5V, it can directly interface with low-current LED segments or sink into transistor bases for higher-current multiplexing. The high-impedance OE bar enables multiple latches to share the same microcontroller bus without contention. The TSSOP-20 package provides a compact footprint for portable instrumentation and consumer product displays.
Recommended
Bus Isolation in Mixed-Voltage Systems
The SN74AHC373PWR isolates two subsystems operating at different voltages on a shared data bus. When OE bar is HIGH, all eight outputs enter high-impedance, electrically disconnecting the bus segment and allowing a different subsystem to drive it. This enables 3.3V MCUs and 5V peripherals to coexist on the same parallel bus, with the latch acting as a controlled bridge. Its 5V-tolerant inputs accept 5V signals from legacy peripherals even when VCC is 3.3V, providing built-in level tolerance. The TSSOP-20 package keeps the isolator footprint small, and the 8.5 ns propagation delay maintains real-time bus response for control and status interfaces.
Recommended
I/O Port Expansion for Microcontrollers
When a microcontroller runs short of GPIO pins, the SN74AHC373PWR provides eight additional output bits in a single 20-pin package. The MCU writes the desired output pattern to the latch via SPI bit-banging or an 8-bit parallel port; the latch holds the value until updated, freeing the MCU to perform other tasks. This approach reduces BOM cost compared to dedicated I/O expanders while providing direct 8 mA drive. The 2V-5.5V supply range makes it compatible with both 3.3V and 5V MCU families, and the TSSOP-20 footprint integrates easily onto existing MCU breakout boards. Per TI datasheet, the device's low quiescent current of 4 uA typical minimizes its impact on battery-powered designs.
Recommended
Address Latch for Legacy x86 Memory Interfaces
In 8086/8088-style multiplexed address/data memory interfaces, the SN74AHC373PWR captures the lower address byte (AD0-AD7) on the falling edge of the address latch enable (ALE) signal. The latched A0-A7 is then used by memory chips for the duration of the bus cycle. With 8.5 ns propagation delay, it supports bus cycles down to approximately 30 MHz, covering standard 8-bit MCU/memory interfaces. The 5V tolerance makes it compatible with legacy TTL peripherals, and the OE bar enables memory and DMA sharing on the same address bus. The TSSOP-20 package simplifies PCB layout compared to DIP or SOIC alternatives.
Recommended
Data Register and State Retention
The SN74AHC373PWR functions as a simple data register that retains its last written state even when the data source is no longer driving the bus. This makes it useful for configuration storage in microcontroller-based modules where certain outputs must be held at defined levels between transactions. With 4 uA typical quiescent current, the device contributes minimally to standby power consumption in battery-powered systems. The 8.5 ns propagation delay and +/-8 mA drive support real-time control signals to peripheral enable pins and mode-select inputs. The TSSOP-20 package provides the necessary 20 pins for the 8-bit data path plus LE and OE bar controls while keeping the design compact.
Recommended
Industrial Control Signal Latching
In industrial automation and control systems, the SN74AHC373PWR latches set-point or mode-select values for parallel-driven drivers and indicators. With -40C to +85C industrial temperature rating and JESD 17 latch-up protection exceeding 250 mA, it withstands harsh factory environments. The 8 mA drive directly controls optocoupler LEDs, relay driver bases, and panel indicator inputs. The transparent latch behavior allows system engineers to verify the state of each output bit in real time before committing to non-transparent mode. The TSSOP-20 surface-mount package supports automated assembly and high-density industrial control PCB layouts.
Recommended
Recommended Products Summary
Engineering reference data for SN74AHC373PWR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SN74AHC373PW | SN74AHC373PWRG4 | SN74AHCT373PWR | 74VHC373MTCX | MC74VHC373DTR2G |
|---|---|---|---|---|---|---|
| Package | TSSOP-20 (PW) | TSSOP-20 (PW) - same | TSSOP-20 (PW) - same | TSSOP-20 (PW) - same | TSSOP-20 (MTC) - same footprint | TSSOP-20 (DT) - same footprint |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | onsemi | onsemi |
| Logic Family | AHC | AHC | AHC | AHCT (TTL input levels) | VHC | VHC |
| VCC Supply Range | 2V to 5.5V | 2V to 5.5V | 2V to 5.5V | 4.5V to 5.5V | 2V to 5.5V | 2V to 5.5V |
| Output Drive (IOL/IOH) | +/-8 mA at 5V | +/-8 mA | +/-8 mA | +/-8 mA | +/-8 mA | +/-8 mA |
| Propagation Delay (tpd, 5V) | 8.5 ns typical | 8.5 ns | 8.5 ns | 8.5 ns | 7.0 ns | 7.0 ns |
| Quiescent Current (ICC) | 4 uA typical | 4 uA | 4 uA | 4 uA | 4 uA | 4 uA |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Key Differentiators
- Wide 2V to 5.5V supply range supports both 3.3V and 5V logic (vs SN74AHCT373PWR)
- Faster propagation delay than VHC family alternatives (vs 74VHC373MTCX)
- JESD 17 latch-up exceeds 250 mA and JESD 22 ESD exceeds 2000V HBM (vs MC74VHC373DTR2G)
Design Notes
Always tie unused D inputs to VCC or GND through a 10 kOhm resistor. Floating CMOS inputs on the AHC family can drift into the linear region, causing shoot-through current, oscillation, and elevated quiescent current that may exceed 100 uA per floating pin. This is the most common design defect in CMOS logic designs and is frequently missed in prototype debugging.
Route the Latch Enable (LE) signal with controlled impedance and minimum length. Fast LE edges (less than 2 ns) combined with long traces can produce reflections that cause metastability and partial latch behavior. Source-terminate LE with a 33 Ohm series resistor if the trace exceeds 50 mm, or place the latch within 25 mm of the driving MCU to maintain clean transitions and avoid setup/hold violations at high bus speeds.
Add a 0.1 uF ceramic decoupling capacitor as close as possible to the VCC pin (pin 20) on the SN74AHC373PWR. Place a bulk 1-10 uF tantalum or ceramic capacitor on the VCC rail within 50 mm of the device. Multiple latches sharing the same VCC rail should each have their own 0.1 uF bypass capacitor; sharing one across multiple devices can cause voltage spikes during simultaneous output transitions and logic errors.
Keep the data inputs (D0-D7) on one side of the TSSOP-20 package and the outputs (Q0-Q7) routed away to avoid coupling. Maintain 3W spacing between adjacent output traces if the bus is operated above 10 MHz, or use a ground guard trace between high-frequency outputs and sensitive analog signals. The TSSOP-20 thermal pad is not present on this package, so standard TSSOP ground pour provides adequate heat dissipation.
If the SN74AHC373PWR drives long PCB traces or cables (longer than 100 mm), add a 22-33 Ohm series damping resistor at each output to limit edge rates below 5 V/ns and reduce radiated EMI. This is especially important when the latch drives address or data lines on a backplane or external connector. Lower output drive strength (8 mA) compared to ACT family makes this less critical than for ACT/TTL families.
Compliance Information
RoHS compliant per TI product page. Halogen-free per TI packaging materials declaration. Not AEC-Q100 qualified; choose SN74AHC373Q (automotive grade) for automotive applications. Latch-up exceeds 250 mA per JESD 17 and ESD exceeds 2000V HBM per JESD 22 per datasheet.
