FPGA и CPLD
Товары (6666)
A42MX24-2PLG84I - 36K Gate Antifuse FPGA, 84-PLCC | Microchip
The Microchip (Microsemi/Actel) A42MX24-2PLG84I is a member of the MX FPGA family, offering 36,000 system gates, 912 logic cells, and 72 user I/O in an 84-pin PLCC (J-lead) surface-mount package. Built on 0.45um antifuse technology, it operates with a 5.0V core architecture and supports 3.3V/5.0V mixed-voltage I/O, with an industrial temperature rating of -40C to +85C and speed grade -2. An FPGA (Field-Programmable Gate Array) is a type of programmable logic IC that implements custom digital circuits after manufacturing. Unlike SRAM FPGAs, the MX family uses one-time-programmable antifuse interconnects, which makes it a reliable, single-chip ASIC alternative: the configuration is retained permanently, requires no external boot flash, is immune to configuration readback attacks, and powers up instantly with no configuration time. Within the programmable logic hierarchy, the MX family sits as a mature, low-cost, high-volume platform ideal for integrating legacy PLD and glue-logic designs into a single device. Key features include 36K system gates with 912 logic cells, dedicated D-modules arranged around the device periphery that provide fast, wide-input decode functions similar to CPLD architectures, and flexible 3.3V/5V I/O operation for legacy 5V bus interfacing. The 84-PLCC package is through-hole-compatible for socketed use and easy to rework, making it popular for defense, industrial, and long-lifecycle systems. The antifuse fabric architecture delivers deterministic interconnect delays and low static power, while the S-module and C-module combination enables both combinational and sequential logic efficiently. Typical applications include legacy PLD consolidation, industrial control, military/defense subsystems, telecommunications line cards, and 5V-tolerant bus bridging in mixed-voltage systems. Design consideration: because MX devices are one-time-programmable, always complete functional simulation in Libero SoC before programming, and reserve the -2 speed grade timing margin for worst-case industrial temperature operation. Pricing below is as of 2026-08-30.
A42MX24-2PQG160 - 36K Gate 5V Antifuse FPGA 160-PQFP | Microchip
The Microchip Technology (Microsemi) A42MX24-2PQG160 is a 36,000-gate antifuse FPGA from the 42MX family with 912 clocked logic blocks (CLBs), 1890 logic cells, and up to 125 user I/O, housed in a 160-pin PQFP (PQG160) package with 0.635 mm terminal pitch and a speed grade of -2. A field-programmable gate array (FPGA) is a semiconductor device containing programmable logic blocks and interconnects that can be configured after manufacturing. Within the programmable logic hierarchy, the MX family sits in the antifuse FPGA category: one-time programmable (OTP), non-volatile, and inherently design-secure. The 42MX family is built on a 0.45 um CMOS process and operates from a 3.3V/5V supply, making it a cost-effective, single-chip ASIC alternative for high-volume systems and legacy PLD consolidation. Key features include a maximum clock frequency of 114.75 MHz, D-modules arranged around the die periphery that provide fast, wide-input decode functions similar to CPLD architectures, and a flexible 5.0V-tolerant architecture. Antifuse programming gives the device zero configuration-time at power-up, high resistance to bit-stream theft, and low static power compared to SRAM FPGAs. The -2 speed grade balances performance and availability within the family. Logic is implemented in clocked logic blocks and combinatorial modules routed through a segmented interconnect fabric, while dedicated D-modules accelerate wide-decode functions such as address decoding and state-machine detection. Typical applications include legacy system redesign and PLD integration, industrial control logic, glueless bus interfacing, military/industrial 5V systems, and high-volume designs where design security and instant-on operation matter more than reprogrammability. Designers should note that MX devices are one-time programmable: prototype thoroughly in simulation and, where possible, use in-system verification before committing. Power sequencing and 5V/3.3V I/O banking must respect the datasheet electrical limits. This page synthesizes distributor pricing context, drop-in alternatives, pin/package guidance, and practical design notes not found in the manufacturer datasheet.
A42MX24-2PQG160I - 36K Gate 5V FPGA 160-PQFP | Microchip
The Microchip Technology A42MX24-2PQG160I is a member of the Actel/Microsemi 42MX antifuse FPGA family, offering 36,000 system gates, 912 configurable logic cells, and 125 user I/Os in a 160-pin PQFP (BQFP) package. It operates on a flexible 3.3V/5V mixed-voltage architecture with speed grade 2 and industrial temperature range (-40C to +85C). A field-programmable gate array (FPGA) is a semiconductor device containing a matrix of configurable logic blocks (CLBs) and programmable interconnects that designers configure after manufacturing. The MX family belongs to the antifuse FPGA category, meaning its interconnect is one-time programmable and retains configuration at power-up without an external configuration ROM - a key reliability advantage over SRAM-based FPGAs. FPGAs sit above CPLDs and below ASICs in the integration hierarchy and serve as a single-chip ASIC alternative for legacy PLD consolidation. Key features include MultiPlex I/Os supporting mixed-voltage 5.0V and 3.3V systems, programmable PCI operation fully compliant with the PCI Local Bus Specification version 2.1, and a low-power mode. The 0.45um CMOS process delivers dependable, single-chip, high-volume operation at low cost. The antifuse architecture provides inherent resistance to configuration upsets, making the A42MX24 well suited to industrial control, legacy system sustainment, high-reliability embedded logic, and military/defense retrofit programs where 5V compatibility is mandatory. Designers should note that the antifuse fabric is one-time programmable, so design iteration requires new devices; plan programming yields accordingly. Verify 114.75MHz-class timing closure against the DS2136 datasheet for your speed grade.
A42MX24-3PLG84 - 36K Gate MX FPGA, 84-PLCC | Microchip
The Microchip Technology (formerly Microsemi/Actel) A42MX24-3PLG84 is a member of the MX FPGA family, delivering 36,000 system gates with 912 logic cells and 72 user I/O in an 84-pin PLCC (84-LCC J-Lead, 29.31 x 29.31 mm) surface-mount package. It operates from dual supply rails (3.0V-3.6V core and 4.75V-5.25V I/O) across a 0C to +70C commercial temperature range. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing configurable logic blocks and programmable interconnects that designers configure after manufacturing. The MX family occupies the antifuse-based FPGA category within the broader programmable logic hierarchy (FPGA -> programmable logic -> semiconductors), positioning it as a single-chip ASIC alternative for legacy system integration. Key features include the flexible 5.0V-tolerant architecture inherited from the Actel MX lineage, antifuse programmability that yields non-volatile, single-chip operation with no configuration PROM, and D-modules with wide-decode circuitry providing fast, wide-input AND functions similar to CPLD architectures. The -3 speed grade denotes the fastest commercial timing bin in the family, and the antifuse fabric provides inherent resistance to configuration upset compared to SRAM-based FPGAs. Architecturally, the A42MX24 uses a 0.45 um process with combinatorial and sequential logic modules arranged in an efficient routed fabric, well suited to glue logic consolidation, bus interface bridging, and legacy PLD integration. According to Microchip product documentation, MX devices target high-volume, low-cost platforms where a reliable single-chip ASIC alternative is required. Typical applications include industrial control systems, legacy PLD integration onto one device, 5V-tolerant bus interfacing, and defense/aerospace upgrade programs standardizing on proven MX silicon. Design consideration: this part carries Last Time Buy lifecycle status per distributor data (lead time ~10 weeks), so new designs should evaluate the same-package A42MX16 PLCC-84 variants or plan lifetime buys accordingly.
A42MX24-3PQG160 - 36K Gate MX FPGA, 125 I/O | Microchip
The Microchip Technology A42MX24-3PQG160 is a 36,000-system-gate MX family Field Programmable Gate Array (FPGA) with 912 logic elements, 125 user I/O, and a speed grade of -3, housed in a 160-pin Ball-grid-compatible plastic quad flat pack (160-BQFP / PQFP-G160) with gull-wing terminals on all four sides. An FPGA (Field Programmable Gate Array) is a semiconductor device containing configurable logic blocks and programmable interconnects that the designer configures after manufacturing. Within the programmable logic hierarchy, the MX family sits between CPLDs and high-end FPGAs: it is a one-time-programmable (fuse-based), single-chip ASIC alternative positioned as a low-cost, high-volume platform for integrating legacy PLD designs into a single device. Key features of the A42MX24 include a flexible 5.0 V tolerant architecture, which makes it especially attractive for integrating legacy 5V PLD logic; D-modules arranged around the device periphery that provide wide-decode circuitry for fast, wide-input AND functions similar to CPLD/PAL architectures; and the non-volatile Actel fuse antifuse technology, which means the configuration is retained without an external configuration PROM and is inherently immune to configuration readback or single-event configuration upsets compared to SRAM FPGAs. Technically, the device belongs to the 42MX family alongside the larger A42MX36. The MX architecture combines combinational logic modules with these wide-decode D-modules; the -3 speed grade denotes the fastest commercial grade in the family, supporting clock rates in the 100 MHz-plus class for datapath and state-machine functions. Pricing and stock are available from six distributors as tracked by Octopart as of 2026-08-30. Typical applications include legacy 5V system glue logic consolidation, industrial control and motor interface boards, aerospace/defense retaining designs, and high-volume ASIC prototyping or bridge-to-ASIC production where a reliable, single-chip programmable alternative is preferred. When designing with this part, note that it is one-time programmable: unlike SRAM FPGAs there is no re-programming, so design freezes and thorough simulation before programming are essential. This page synthesizes distributor pricing, drop-in family alternatives, and practical design guidance not consolidated in the manufacturer datasheet.
A42MX24-3PQG208I - 36K Gate 5V FPGA, PQFP-208 | Microchip
The Microchip Technology (Microsemi) A42MX24-3PQG208I is a member of the 42MX FPGA family, offering 36,000 system gates, 912 logic cells, and 176 user I/Os in a 208-pin fine-pitch PQFP (BFQFP) package with industrial temperature rating (-40C to +85C) and speed grade -3. Built on a 0.45um antifuse process, it operates from dual 3.3V/5V supplies. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing programmable logic blocks and interconnects that designers configure after manufacturing, making it a flexible alternative to fixed-function ASICs. Within the programmable logic hierarchy, the MX family sits as a low-cost, high-volume platform for integrating legacy PLDs and glue logic into a single chip. Unlike SRAM FPGAs, Microchip MX devices use antifuse technology, which is non-volatile and radiation-tolerant by nature of the one-time programmable architecture. Key features include MultiPlex I/O supporting mixed-voltage 3.3V/5.0V systems, programmable PCI compliance with the PCI Local Bus Specification (version 2.1), a low-power mode, and D-modules arranged around the device periphery that perform wide-decode functions at speeds comparable to CPLDs and PALs. Each D-module output includes a programmable inverter for active-HIGH or active-LOW assertion, enabling efficient wide-input AND functions. The 42MX architecture combines C-modules (combinational logic) with the decode-oriented D-modules, giving A42MX24 devices CPLD-like wide-decode performance alongside fine-grained FPGA fabric. This makes the device particularly effective for state machines, address decoding, bus interfacing, and legacy design consolidation. Typical applications include industrial control and automation, legacy PLD integration, 5V PCI bus interfaces, military/industrial system upgrades, and high-volume ASIC prototyping where 5.0V I/O compatibility is mandatory. Design consideration: as a one-time-programmable antifuse device, verify your design thoroughly in simulation before programming, since design iterations require a new device. Confirm supply sequencing between the 3.3V core/IO and 5V I/O domains per the 40MX/42MX datasheet (DS2136).
A42MX24-3TQG176 - 36K Gate MX FPGA 150 I/O | Microchip
The Microchip Technology A42MX24-3TQG176 is an MX family field-programmable gate array (FPGA) delivering 36,000 system gates with 912 configurable logic cells and 150 user I/Os in a 176-pin TQFP package. Operating from a dual 3.3V/5V supply, the -3 speed grade targets high-volume, cost-sensitive designs. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing a fabric of configurable logic blocks and interconnects that designers program to implement custom digital circuits. Within the programmable logic hierarchy, FPGAs sit above CPLDs and PLDs in capacity and below ASICs in unit cost, making them the standard single-chip ASIC-alternative for mid-volume systems. The MX family is specifically positioned by Microchip as a reliable, single-chip ASIC replacement for consolidating legacy PLDs. Key features include the 42MX architecture with C-modules and S-modules for combinational and sequential logic, plus D-modules around the device periphery that provide fast, wide-input decode functions similar to CPLD architectures. The 5.0V-tolerant architecture allows direct interfacing with legacy 5V systems, a rarity in modern FPGAs. Commercial temperature range is 0C to +70C with SMD/SMT mounting. Technically, the device uses a 0.6 um-class CMOS process with antifuse-free reprogrammable-style configuration flow supported by Microchip (formerly Actel/Microsemi) Libero design tooling. The 176-terminal TQFP measures 24 mm x 24 mm with 1.60 mm seated height, supporting standard surface-mount assembly. Typical applications include legacy PLD consolidation, industrial glue logic, ASIC prototyping, bus interface bridging, and military/industrial control systems that require 5V compatibility. The 150 I/O count supports wide parallel buses common in these designs. Design consideration: this part is commercial-grade (0C to +70C); for extended temperature use, select the -I suffix variant, and always verify 5V I/O bank budgeting in Libero before layout.
A42MX24-FTQG176 - 36K Gate MX FPGA | Microchip Technology
The Microchip Technology A42MX24-FTQG176 is a field-programmable gate array (FPGA) from the MX family, offering 36,000 system gates and 912 logic modules in a 176-pin LQFP package. It operates at both 3.3V and 5.0V, providing a flexible, single-chip ASIC alternative for integrating legacy PLDs into a low-cost, high-volume design. The device features 150 user I/Os and is fully compliant with the PCI Local Bus Specification (version 2.1), making it suitable for a wide range of industrial and communication applications. An FPGA is an integrated circuit that can be programmed after manufacturing to implement custom digital logic functions. Unlike fixed-function ASICs, FPGAs offer reconfigurability, allowing designers to iterate on logic designs without the cost and lead time of custom silicon. The MX family sits within the broader hierarchy of programmable logic devices, bridging the gap between CPLDs and high-density FPGAs, and is optimized for 5V legacy systems while supporting 3.3V operation. Key features of the A42MX24-FTQG176 include 36K system gates, 912 modules, and 150 user I/Os. The device supports mixed-voltage systems through MultiPlex I/Os, which enable programmable PCI and provide a low-power mode. It also includes D-modules for wide-decode functions, delivering speeds comparable to CPLDs and PALs. The 176-pin LQFP package offers a compact footprint for space-constrained designs. Technically, the A42MX24 is built on a 0.45um process technology, balancing performance and power consumption. The architecture includes S-modules and C-modules for logic implementation, along with D-modules for wide-input AND functions. The device supports both 3.3V and 5.0V I/O, with internal voltage regulation for core logic. This flexibility allows seamless integration into existing 5V systems while enabling migration to lower-voltage designs. Typical applications include industrial control, telecommunications, automotive electronics, and legacy system integration. The A42MX24-FTQG176 is ideal for designs that require high I/O count and moderate logic density, such as bus interfaces, memory controllers, and protocol converters. Its PCI compliance makes it suitable for add-on cards and embedded systems. When designing with this FPGA, consider the power supply requirements: both 3.3V and 5.0V rails may be needed, and proper decoupling is essential. The device supports in-system programming, allowing firmware updates in the field. Ensure adequate thermal management for high-I/O designs, as the LQFP package has limited heat dissipation. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing a comprehensive resource for engineers evaluating the A42MX24-FTQG176.
A42MX24-PL84 - 36K Gate FPGA, 84-PLCC | Microchip Technology
The Microchip (Microsemi/Actel) A42MX24-PL84 is a member of the 42MX FPGA family, delivering 36,000 system gates and 912 logic cells with 72 user-programmable I/O in an 84-pin PLCC (84-LCC J-Lead) surface-mount package. It operates from dual supply rails of 3.0V to 3.6V (core/I/O bank) and 4.75V to 5.25V, on a 0.45um CMOS process. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing a fabric of configurable logic blocks and programmable interconnects that the designer configures after manufacturing. Within the programmable-logic hierarchy (FPGA -> programmable logic device -> digital IC), FPGAs sit between fixed-function ASICs and CPLDs. The MX family is specifically positioned as a reliable, single-chip ASIC alternative and an ideal platform for integrating legacy PLDs into a single low-cost device, thanks to its flexible 5.0V-tolerant architecture. Key features include the 42MX modular architecture with C-modules (combinatorial), R-modules (sequential/registers), and on the A42MX24, D-modules arranged around the device periphery that provide fast wide-input decode functions similar to CPLD-style wide-decode circuitry. The device is antifuse-programmable, giving non-volatile configuration, high design security, and instant-on behavior without external configuration memory - a differentiator over SRAM FPGAs. Dual 3.3V/5V supply operation simplifies interfacing with legacy 5V systems. The architecture delivers deterministic, low-skew routing with high performance for glue logic, bus interfacing, address decoding, state machines, and system integration tasks. Typical applications include industrial control, legacy PLD consolidation, 5V-system interfacing, aerospace/defense upgrades of obsolete designs, and high-volume cost-sensitive systems replacing ASIC NRE. Design consideration: the PLCC-84 package offers moderate I/O density; verify supply sequencing of the 3.3V and 5V rails and follow the 40MX/42MX FPGA Families datasheet (DS2316) power and layout recommendations. Pricing referenced as of 2026-08-30.
A42MX24-PLG84M - 36K Gate FPGA, 84-PLCC | Microchip
The Microchip (Microsemi) A42MX24-PLG84M is a member of the Actel 42MX FPGA family, offering 36,000 equivalent system gates, 924 logic modules, and 72 user I/O in an 84-pin PLCC (PLG84) package. Fabricated on a 0.45 um CMOS process, the device operates from a 5.0V core with 3.3V/5V tolerant I/O support, making it a proven single-chip ASIC alternative for legacy and high-volume industrial designs. A field programmable gate array (FPGA) is a semiconductor device containing configurable logic blocks and interconnects that designers program in the field. Within the programmable logic hierarchy, the MX family sits as a fuse-based, antifuse-style, non-volatile programmable logic platform - an alternative to CPLDs and standard-cell ASICs for glue logic, legacy PLD consolidation, and moderate-density control functions. Key features include the MX 5.0V architecture with efficient routing, D-modules with wide-decode circuitry providing fast wide-input AND functions similar to CPLD architectures, and dual supply support (3.3V/5V). The 42MX family integrates legacy PLDs into a single low-cost device, reducing board area and component count in cost-sensitive systems. Architecturally, A42MX24 combines C-modules (combinational), S-modules (sequential with registers), and D-modules (wide decode) arranged to balance logic density and fast decode paths. The antifuse-style non-volatile programming means the device configures instantly at power-up with no external boot PROM, improving system reliability and security compared to SRAM FPGAs. Typical applications include industrial control and automation, legacy system redesign and BOM consolidation, glue logic integration, high-volume appliances, and military/aerospace upgrade programs where proven, radiation-tolerant-heritage programmable logic is valued. Design consideration: verify speed grade and temperature suffix in the full ordering code, and confirm PLCC through-hole/socket mounting constraints early, since PLCC packaging differs from modern surface-mount QFP/BGA footprints.
A42MX24-PQ160I - 36K Gate 5V FPGA 160-BQFP | Microchip
The Microchip Technology (formerly Actel/Microsemi) A42MX24-PQ160I is an MX family antifuse FPGA providing 36,000 system gates, 912 logic cells, and 125 user I/O in a 160-pin BQFP surface-mount package. The industrial-grade (I) suffix supports operation from -40C to +85C. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing programmable logic blocks and interconnects that designers configure after manufacturing. The MX family belongs to the one-time-programmable (OTP) antifuse FPGA category, positioned within the broader programmable logic hierarchy: FPGA -> programmable logic device -> digital IC -> semiconductor. Unlike SRAM FPGAs, antifuse programming is permanent, radiation-tolerant by nature, and requires no configuration PROM, making MX devices a reliable single-chip ASIC alternative for high-volume systems. Key features include a flexible 5.0V-tolerant architecture with dual supply rails (3V to 3.6V core and 4.75V to 5.25V I/O per Microchip USA data), 0.45um antifuse process technology, and 125 programmable I/O supporting legacy 5V logic integration. The MX family enables consolidation of legacy PLDs, PALs, and glue logic into a single low-cost device, reducing board space and component count. The Actel antifuse architecture (R-Cell and C-Cell modular blocks) delivers deterministic routing and inherent security against design theft, since the programmed netlist cannot be read back. This makes the A42MX24 well suited to applications where IP protection and configuration immutability matter. Typical applications include industrial control systems, legacy 5V system migrations, aerospace and defense logic replacement, telecommunications interface boards, and high-volume consumer/industrial ASIC prototyping. The 160-BQFP package (28x28 mm) offers 0.65mm pin pitch for rework-friendly assembly. Design consideration: antifuse FPGAs are one-time programmable - fully verify your design in simulation (Libero SoC or Actel Designer toolchain) before programming, as no design iteration is possible on the same device.
A42MX24-PQG160A - 36K Gate 5V MX FPGA | Microchip Technology
The Microchip Technology (Microsemi) A42MX24-PQG160A is a 36,000-system-gate FPGA from the MX family, provided in a 160-pin PQFP (BQFP) surface-mount package with 125 user I/O. It operates from dual supply rails of 3V to 3.6V and 4.5V to 5.5V, supports a 135 MHz system speed grade, and is rated for -40C to +125C (TA) automotive environments. An FPGA (Field Programmable Gate Array) is a semiconductor device containing a matrix of configurable logic blocks and programmable interconnects that the designer programs to implement custom digital logic. Within the hierarchy of programmable logic, FPGAs sit above CPLDs in density and flexibility, and the MX family specifically serves as a single-chip ASIC alternative: the 42MX devices integrate legacy PLD, glue-logic, and control functions into one low-cost, high-volume 0.45 um process device. Key features of the A42MX24 include 36K system gates with 912 logic cells, a flexible 5.0V-tolerant architecture that simplifies integration with legacy 5V systems, 125 user I/O, and industrial-plus temperature range suitable for automotive and harsh-environment deployments. The device is ROHS3 compliant and lead free, easing transition of mature 5V designs to current environmental standards. Architecturally, the MX family combines combinatorial and sequential logic modules with embedded routing resources, delivering deterministic performance of up to 135 MHz - adequate for legacy control, interface bridging, and state-machine applications. As a one-time or low-volume programmable platform, it eliminates NRE costs of full-custom ASICs while shortening the design and development cycle. Typical applications include legacy PLD consolidation, industrial control systems, 5V bus interfacing, automotive modules requiring -40C to +125C operation, and ASIC prototyping for the MX/AX architecture migration path. When designing with the A42MX24-PQG160A, respect the two-rail supply requirement (3V-3.6V core/I-O domain and 4.5V-5.5V domain) and follow the Microchip/Microsemi MX datasheet power-up sequencing and decoupling recommendations. Note the 10-week manufacturer lead time when planning production buys.
A42MX24-PQG160M - 36K Gate MX FPGA, 160-PQFP | Microchip
The Microchip Technology (Microsemi) A42MX24-PQG160M is a 36,000-system-gate antifuse FPGA from the 42MX family, providing 912 configurable logic blocks (CLBs), 125 user I/Os, and a maximum toggle frequency of 114.75 MHz, housed in a 160-pin PQFP (BQFP) package with gull-wing leads. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing an array of programmable logic blocks and reconfigurable interconnects that the designer wires together to implement custom digital hardware. Within the product hierarchy, the A42MX24 belongs to the FPGA category under programmable logic ICs, positioned as a single-chip ASIC alternative for high-volume systems and legacy PLD integration. Key features include Microsemi's proven 0.45 um antifuse technology, which produces a one-time-programmable, non-volatile configuration that is inherently immune to configuration readback attacks and radiation-induced configuration upset. The device operates from a 5.0V supply with 3.3V-tolerant multiPlex I/O support, enabling mixed-voltage system designs. D-modules arranged around the die periphery provide wide-decode functions comparable to CPLD and PAL architectures, and a low-power mode reduces static consumption in standby. The architecture combines C-modules (8-input combinational logic), S-modules (sequential flip-flop logic), and D-modules (wide-decode), giving designers flexible mapping of state machines, decoders, and glue logic. Because the antifuse fabric is programmed permanently, there is no configuration PROM required at power-up, reducing bill-of-materials cost and boot time versus SRAM FPGAs. Typical applications include industrial control, automotive subsystems (the M-suffix automotive grade), communications bridging, bus interfacing including programmable PCI, and consolidation of legacy 5V PLD/CPLD designs into one low-cost device. Design consideration: the 5.0V core supply is mandatory; designers must respect the 114.75 MHz frequency ceiling and verify I/O voltage levels for 3.3V interfacing using the multiPlex I/O configuration options. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet.
A42MX24-PQG208A - 36K Gate MX FPGA, 176 I/O | Microchip
The Microchip Technology A42MX24-PQG208A is a field-programmable gate array (FPGA) from the MX family, offering 36,000 system gates and 912 logic modules in a 208-pin PQFP (plastic quad flat pack) package. It operates from a 5.0 V supply and provides 176 user I/Os, making it a reliable single-chip alternative to ASICs for integrating legacy PLDs into a low-cost, high-volume platform. An FPGA is an integrated circuit that can be configured by the customer or designer after manufacturing—hence "field-programmable." FPGAs contain a fabric of programmable logic blocks and interconnects, allowing them to implement arbitrary digital logic functions. They sit between fixed-function ASICs and general-purpose processors, offering flexibility and parallel processing capabilities. The MX family is a mature, 5.0 V architecture optimized for high-volume applications where cost and reliability are paramount. Key features of the A42MX24-PQG208A include 36,000 system gates, 912 logic modules, 176 user I/Os, and support for 5.0 V and 3.3 V mixed-voltage systems via MultiPlex I/Os. The device is fully compliant with the PCI Local Bus Specification (version 2.1), enabling direct interface to PCI buses without additional glue logic. It also features a low-power mode, making it suitable for power-sensitive designs. Technically, the MX family uses a 0.45 µm process technology and supports system speeds up to 135 MHz. The device includes dedicated clock networks and programmable I/O standards, allowing flexible integration into various system architectures. The 208-pin PQFP package provides a compact footprint while offering ample I/O for medium-density logic designs. Typical applications include industrial control, transportation systems, consumer electronics, and legacy PLD consolidation. The 5.0 V operation and PCI compliance make it ideal for interfacing with older 5 V logic families and PCI-based systems, while the low-power mode extends battery life in portable applications. When designing with this FPGA, ensure proper decoupling of the 5.0 V supply and follow the manufacturer's layout guidelines for the PQFP package to minimize signal integrity issues. The device supports in-system programming, allowing firmware updates without removing the component from the PCB. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a comprehensive resource for evaluating the A42MX24-PQG208A.
A42MX24-TQG176A - 36K Gate 5V FPGA, 176-TQFP | Microchip
The Microchip Technology (formerly Microsemi) A42MX24-TQG176A is a member of the 42MX family of antifuse-based field programmable gate arrays, delivering 36,000 system gates in a 176-pin thin quad flat package (TQFP) with 150 usable user I/Os. It operates from a single 5.0V supply, making it a proven platform for legacy 5V system integration and high-volume, cost-sensitive designs. An FPGA (field programmable gate array) is a type of programmable logic device that implements user-defined digital circuits through configurable logic blocks and programmable interconnects. Within the semiconductor hierarchy, it sits under programmable logic, alongside CPLDs and ASICs. The MX family uses Microsemi antifuse technology, a one-time-programmable interconnect that provides non-volatile, single-chip operation without external configuration devices. Key features include a flexible 5.0V architecture, 1890 logic cells organized into 912 configurable logic blocks (CLBs), and a maximum toggle-rate-oriented system performance suited to glue logic consolidation, legacy PLD integration, and industrial control. The antifuse fabric is inherently non-volatile and secure, with no bitstream to load at power-up, reducing BOM cost and configuration time compared to SRAM FPGAs. Technically, the MX architecture combines Combinatorial Modules and Register Modules, allowing efficient implementation of wide combinatorial functions and registered pipelines. The die is fabricated on a CMOS process, and the TQG176A package is a 176-lead TQFP, 24x24 mm body, 0.5 mm lead pitch, surface mount. Typical applications include legacy aerospace and industrial board redesigns, bus-interface logic consolidation, and single-chip replacements of multiple PLDs, PALs, and GALs in 5V systems. Design consideration: because the device is antifuse-based (one-time programmable), a programming service or programmer step is required before assembly; plan your design freeze and programming flow accordingly.
A42MX24-TQG176M - 36K Gate 5V MX FPGA, 176-TQFP | Microchip
The Microchip Technology A42MX24-TQG176M (originally Actel/Microsemi) is a member of the MX FPGA family, delivering 36,000 system gates with 912 logic cells in a 176-pin TQFP (LQFP) package offering 150 user I/O. It is fabricated on a 0.45um process and operates from 3.3V/5.0V supply rails, making it one of the few truly 5V-tolerant FPGA platforms available today. An FPGA (Field-Programmable Gate Array) is a class of programmable logic IC that implements user-defined digital circuits through configurable logic blocks and interconnect. Within the programmable logic hierarchy, the MX family sits as a single-chip ASIC alternative: unlike SRAM FPGAs it is non-volatile, and unlike antifuse families it is reprogrammable in-system. This positions MX as an ideal platform for integrating legacy PLDs, glue logic, and CPLDs into a single, low-cost, high-volume device. Key features of the A42MX24 include 36K system gates, dual-voltage 3.3V/5V operation, and D-modules with wide-decode circuitry around the device periphery that provide fast, wide-input AND functions similar to CPLD architectures, enabling efficient state machines and address decoding. The architecture combines C-modules and S-modules for flexible combinational and sequential logic mapping. Technically, the MX family uses a flexible 5.0V-tolerant fabric with 0.45um flash-based configuration storage, so designs retain their programming through power cycles without external configuration devices. The 176-TQFP package is a widely available gull-wing surface-mount format compatible with standard reflow assembly. Typical applications include industrial control systems, military and defense upgrades of 5V-era designs, legacy PLD consolidation, bus interfacing, and high-volume embedded systems where a reliable single-chip ASIC alternative is required. Design consideration: budget power distribution for the 3.3V/5V dual-rail requirements and verify I/O bank voltage assignments against the 40MX/42MX datasheet before pin locking.
A42MX36-1BGG272 - MX FPGA, 54K Gates, 272-BGA | Microchip
The Microchip Technology (Microsemi) A42MX36-1BGG272 is an MX family Field Programmable Gate Array (FPGA) in a 272-ball BGA package, offering 54,000 equivalent gates, 1184 Configurable Logic Blocks (CLBs), 2438 logic cells, 2560 total RAM bits, and 202 configurable user I/Os. The -1 speed grade supports a maximum clock frequency of 83 MHz. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing programmable logic blocks and interconnects that designers configure after manufacturing. Within the programmable logic hierarchy, the MX family sits as a one-time-programmable antifuse FPGA - a single-chip ASIC alternative - under the broader category of programmable logic devices (PLDs), which also includes CPLDs and PLDs. Key features include Microchip's reliable antifuse architecture operating at 5.0V, which provides non-volatile, tamper-resistant configuration that is live at power-up with no external configuration PROM required. This makes MX devices ideal for integrating legacy PLD designs, glue logic, and bus interfaces into a single low-cost, high-volume device. The 272-ball BGA (JESD-30 BBGA) package provides high I/O density in a surface-mount footprint. The A42MX36 is the largest member of the 42MX family. It uses a CMOS process with a flexible routing fabric suited to state machines, address decoding, bus interfacing, and control logic. Design entry and programming use the Microchip (Microsemi) Libero SoC design suite. Typical applications include legacy ASIC/PLD consolidation, industrial control, military and aerospace systems (ceramic CQ208/CQ256 versions are screened to MIL-STD-883 levels), telecommunications line cards, and embedded system glue logic. Design consideration: the 5.0V core/I-O architecture requires a 5V power rail; verify I/O voltage compatibility with adjacent modern 3.3V or 2.5V devices and use appropriate level shifting or series resistors on mixed-voltage busses.
A42MX36-1PQG208 - 54K Gate FPGA, 176 I/O | Microchip
The Microchip Technology (Microsemi/Actel) A42MX36-1PQG208 is a 54,000-gate flash-based FPGA from the MX family, providing 1184 configurable logic blocks, 2560 logic modules, and 176 user I/O in a 208-pin BFQFP (PQFP) surface-mount package. It operates on a flexible 3.3V/5.0V mixed-voltage architecture with a -1 standard speed grade. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing programmable logic blocks and interconnects that designers configure after manufacturing, offering a single-chip ASIC alternative. The MX family sits in the broader hierarchy of programmable logic devices (PLDs), bridging legacy CPLD/PLD integration and full ASIC development, and is a proven high-volume platform for consolidating legacy designs. Key features include MultiPlex I/O supporting mixed-voltage systems, programmable PCI compliance with the PCI Local Bus Specification version 2.1 at both 5.0V and 3.3V, a low-power mode, and embedded dual-port SRAM modules optimized for FIFO, LIFO, and scratchpad datapath functions. The A42MX36 also contains wide-decode modules for high-fan-in address decoding, and the PQ208 package is pin-compatible with the CQ208 ceramic package used in MIL-STD-883 screened versions. The device uses Actel's antifuse-style MX architecture (0.45um class CMOS process), delivering non-volatile, secure, single-chip configuration without external boot flash - a key reliability advantage for industrial and defense designs. Logic density is deployed through the Designer software and ACTgen Macro Builder for memory macro generation. Typical applications include legacy PLD consolidation, industrial control, glue-logic integration, PCI interface bridging, and mil/aero systems requiring the ceramic-package variant. The 5.0V-tolerant I/O makes it especially suitable for interfacing with legacy 5V buses. Design consideration: plan I/O banking carefully for mixed 3.3V/5.0V systems and verify timing at the -1 speed grade; use adequate decoupling on the multiple VCC/VCCA pins per the 40MX/42MX datasheet (DS2136) power guidelines.
A42MX36-2PQG208 - 54K Gate 5V FPGA PQFP-208 | Microchip
The Microchip Technology (Microsemi) A42MX36-2PQG208 is a 54,000-gate antifuse field programmable gate array (FPGA) from the 42MX family, packaged in a 208-pin fine-pitch plastic QFP (208-BFQFP, 28x28 mm) with 176 user I/Os. It operates from dual supply rails of 3V-3.6V (core) and 4.5V-5.5V (I/O), over the industrial temperature range of -40C to +85C. An FPGA (field programmable gate array) is a semiconductor device containing configurable logic blocks (CLBs), routing fabric, and I/O cells that designers program to implement custom digital circuits. The 42MX family belongs to the broader FPGA hierarchy: FPGA -> programmable logic device (PLD) -> programmable logic IC -> semiconductor. The MX family uses antifuse programming technology, providing a non-volatile, single-chip ASIC alternative with inherently high design security and no configuration PROM required. Key features include 1184 CLBs, 2560 bits of dual-port SRAM (256-bit blocks configurable as 32x8 or 64x4, cascadable into FIFO/LIFO buffers), a 0.45um CMOS process, and a -2 speed grade supporting system speeds around 91 MHz (per Microchip parametric data). The 5V-tolerant I/O architecture makes the device ideal for integrating legacy 5V PLD designs into a single low-cost, high-reliability chip. The antifuse fabric yields deterministic interconnect delays and is immune to configuration upsets from radiation compared with SRAM FPGAs, supporting aerospace, industrial, and defense applications. CQ208 ceramic package variants screened to MIL-STD-883 are pin-compatible with PQ208 plastic parts, enabling prototype-to-production conversion. Typical applications include legacy system redesign, glue logic integration, industrial control, and high-reliability embedded systems. Design with the Microchip Libero SoC and Designer software using ACTgen macro builder for memory functions. Note the 12-week manufacturer lead time when planning production buys.
A42MX36-3BGG272 - 54K Gate 5V FPGA, 272-ball BGA | Microchip
The Microchip Technology A42MX36-3BGG272 is a 54,000-equivalent-gate Field Programmable Gate Array (FPGA) from the MX (42MX) family, offering 1184 Configurable Logic Blocks (CLBs), 202 programmable I/O pins, and combinatorial delays of up to 1.9 ns, housed in a 272-ball BGA package. An FPGA is a semiconductor device containing an array of programmable logic blocks and reconfigurable interconnects that a designer can program in the field to implement custom digital circuits. FPGAs occupy a position in the digital IC hierarchy between fixed-function ASICs and microcontrollers, providing ASIC-like parallelism with NRE-free flexibility. The MX family is specifically positioned by Microchip as a reliable, single-chip ASIC alternative built on an efficient, flexible 5.0V architecture, making it an ideal platform for integrating legacy PLDs into a single, low-cost, high-volume device. Key features of the A42MX36-3BGG272 include its family-leading 54k gate capacity, 1184 CLBs of configurable logic, 202 user-programmable I/O, and fast 1.9 ns combinatorial delay for high-speed state machines and glue logic. The 5.0V supply architecture provides native compatibility with legacy 5V TTL/5V CMOS system environments that many modern, low-voltage FPGAs cannot directly interface with. Technically, the MX architecture uses a segmented routing fabric with combinational and sequential modules per CLB, verified over automotive and military temperature ranges per the Microchip (formerly Microsemi/Actel) 40MX/42MX datasheet. The largest family member, A42MX36, is additionally available in CQ208 and CQ256 ceramic packages screened to MIL-STD-883 levels; CQ208 and PQ208 devices are pin-compatible for prototyping-to-production conversion. Typical applications include legacy PLD consolidation, ASIC prototyping and emulation, 5V industrial control systems, military/aerospace upgrades, and telecommunications backplane glue logic. The 202 I/O count suits large bus interfacing, while 1.9 ns combinatorial delays support fast decode and arbitration logic. Design consideration: the 5.0V architecture is a deliberate feature for legacy 5V systems; for new low-voltage designs, current Microchip families are a better fit, so verify rail compatibility before finalizing the BOM. This page synthesizes distributor pricing, drop-in package-compatible alternatives, and practical design guidance not found in the manufacturer datasheet.
A42MX36-BGG272 - 54K-Gate 5V FPGA, 202 I/O 272-BBGA | Microchip
The Microchip (Microsemi) A42MX36-BGG272 is a 54,000 usable-gate MX-family FPGA with 202 user-programmable I/O pins, 2560 bits of configurable dual-port SRAM, and up to 250 MHz internal performance, housed in a 272-ball BGA (BBGA) package. It is the largest member of the 42MX family and serves as a reliable single-chip ASIC alternative. An FPGA (Field-Programmable Gate Array) is a semiconductor device that implements custom digital logic through programmable interconnect and configurable logic modules, sitting within the broader programmable-logic hierarchy: FPGA -> programmable logic device -> digital IC -> semiconductor. The Microchip/Microsemi MX family was designed specifically as a low-cost, high-volume platform for consolidating legacy PLDs, PALs, and glue logic into a single device operating at 5V. Key features include 3,000 to 54,000 system gates, up to 2.5 kbits of configurable dual-port SRAM with 5 ns access time, fast wide-decode circuitry, 5.6 ns clock-to-output, and 100 MHz FIFO capability. The device operates from dual supply rails of 3V to 3.6V (core/auxiliary) and 4.75V to 5.25V (I/O), allowing direct interface to legacy 5V TTL-level systems. The MX architecture uses a fine-grained, mux-based logic module that maps legacy schematics and PAL-style designs efficiently, with predictable timing across process corners. The A42MX36 supports both plastic 272-ball BGA packaging and, for the same die, CQ208/CQ256 ceramic packages screened to MIL-STD-883 levels for defense and aerospace programs, with pin-compatible PQ208/CQ208 options for prototype-to-production conversion. Typical applications include legacy 5V system obsolescence management, industrial control, defense electronics, test equipment, and ASIC prototyping where 5V I/O compatibility and long-term availability matter more than leading-edge density. When designing with this device, plan the dual-rail power sequencing and account for the BGA fanout; 202 usable I/O in a 272-ball footprint requires disciplined escape routing on at least 4 signal layers. This page synthesizes distributor pricing, same-family drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet alone.
A42MX36-CQ256BX130 - 54K Gate FPGA, 256-CQFP | Microchip
The Microchip Technology A42MX36-CQ256BX130 is a field-programmable gate array (FPGA) from the 42MX family, offering 54,000 system gates, 1,184 logic modules, and 202 user-programmable I/O pins in a 256-pin ceramic quad flat pack (CQFP) with tie bar. It operates at 5.0 V and 3.3 V, with a maximum internal clock frequency of 131 MHz and a clock-to-out delay of 5.6 ns. The device integrates 2.5 kbits of configurable dual-port SRAM and wide-decode circuitry, making it a reliable single-chip ASIC alternative for high-volume applications. An FPGA (field-programmable gate array) is an integrated circuit that can be configured by the customer after manufacturing to implement arbitrary digital logic functions. FPGAs belong to the programmable logic device (PLD) family, which sits above simple PLDs (SPLDs) and complex PLDs (CPLDs) in the hierarchy of programmable logic. They are used to prototype ASICs, implement glue logic, and accelerate data-path functions in systems ranging from industrial controllers to aerospace electronics. Key features of the A42MX36-CQ256BX130 include 202 user I/Os with MultiPlex I/O support for mixed-voltage systems, programmable PCI compliance (PCI Local Bus Specification version 2.1), and a low-power mode. The device provides 5.6 ns clock-to-out, 250 MHz performance, 5 ns dual-port SRAM access, and 100 MHz FIFO operation. It is fully compliant with the PCI Local Bus Specification (version 2.1) and supports both 5.0 V and 3.3 V operation. Technically, the A42MX36 is built on a 0.45 um CMOS process and contains 1,184 logic modules, each capable of implementing combinatorial and sequential logic. The embedded dual-port SRAM modules are optimized for high-speed datapath functions such as FIFOs, LIFOs, and scratchpad memory. The wide-decode modules enable fast address decoding and state-machine implementation. The device is available in ceramic packages screened to MIL-STD-883 levels for high-reliability applications. Typical applications include legacy PLD integration, bus interfacing, protocol conversion, and aerospace/defense systems requiring radiation-tolerant or high-reliability components. The 5.0 V architecture makes it ideal for interfacing with legacy 5 V logic families, while the 3.3 V capability supports mixed-voltage systems. The device is also used in industrial control, test and measurement, and communication infrastructure. When designing with this FPGA, consider the power supply decoupling: place 0.1 uF and 10 uF capacitors close to each VCC and GND pin to minimize switching noise. The device supports both 5.0 V and 3.3 V I/O, so ensure proper voltage translation for mixed-voltage interfaces. For high-speed designs, pay attention to signal integrity on the clock and data lines. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a comprehensive resource for evaluating the A42MX36-CQ256BX130.
A42MX36-FPQG208 - 54K Gate 5V FPGA, 208-QFP | Microchip
The Microchip Technology (Microsemi) A42MX36-FPQG208 is a 54,000-system-gate FPGA from the MX family, packaged in a 208-pin fine-pitch QFP (208-BFQFP, 28x28 mm) with 176 user I/Os and 2560 bits of embedded dual-port SRAM. Fabricated on a 0.45 um CMOS process, it operates on a flexible 3.3V/5.0V architecture targeted at legacy system integration. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing a fabric of configurable logic blocks (CLBs), routing resources, and I/O cells that designers program in the field. Within the programmable logic hierarchy, the MX family sits as a single-chip ASIC alternative, bridging PLDs, CPLDs, and ASICs for high-volume, cost-sensitive designs. Key features include 1184 logic cells across 1184 CLBs, embedded dual-port SRAM modules optimized for FIFOs, LIFOs, and scratchpad memory, wide-decode modules, and selectable PCI output drives achieving 100% compliance with PCI specification version 2.1 (per the 40MX/42MX families datasheet). A low-power mode turns off all inputs and outputs, reducing current consumption below 500 uA. The MX architecture provides deterministic, antifuse-based one-time programmability, making it attractive for design security, single-event robustness considerations, and long-lifecycle industrial platforms. The 208-QFP surface-mount package supports conventional reflow assembly without ball-grid-array inspection overhead, easing prototyping and rework for legacy-form-factor boards. Typical applications include legacy PLD consolidation, industrial control glue logic, PCI bus interface logic, mil-aero-style long-lifecycle systems, and high-volume ASIC prototyping where 5V-tolerant I/O is required. Design consideration: as a one-time-programmable antifuse device, functional verification must be completed via simulation and (if available) emulation before programming; plan I/O banking carefully between 3.3V and 5V domains to respect drive and tolerance limits. Pricing and stock below are as of 2026-08-30.
A42MX36-PQG208A - 54K Gate 5V FPGA 208-QFP | Microchip
The Microchip Technology (formerly Microsemi/Actel) A42MX36-PQG208A is a member of the 42MX FPGA family, delivering 54,000 system gates and 1184 CLBs (2438 logic cells) in a 208-pin plastic quad flat pack (208-BFQFP/PQFP). It operates from a single 5.0V supply with 176 user I/Os and supports clock rates up to 116 MHz on 0.45 um CMOS technology. An FPGA (Field-Programmable Gate Array) is a semiconductor device containing a fabric of configurable logic blocks and programmable interconnects that designers configure in the field. Within the programmable logic hierarchy, the MX family sits as a cost-effective, single-chip ASIC alternative for high-volume systems, positioned above simple PLDs and below modern high-density FPGAs. Key features include the flexible 5.0V architecture ideal for integrating legacy PLDs into a single low-cost device, MultiPlex I/Os supporting mixed-voltage 5.0V/3.3V systems, programmable PCI compliance with the PCI Local Bus Specification version 2.1, and a low-power mode. The A42MX36 is the largest member of the 40MX/42MX families and is fully tested over automotive and military temperature ranges. The MX architecture uses a proven antifuse-based design flow with Libero SoC design tool support, enabling reliable, one-time programmable configurations immune to configuration-bit upsets in radiation-prone or high-vibration environments. High volume production makes MX a durable platform for long-lifecycle industrial programs. Typical applications include legacy 5V system integration, industrial control, MIL/aerospace upgrades using pin-compatible CQ208 ceramic packages, PCI bus interfaces, and single-chip replacement of multiple PLDs and glue logic. Design consideration: the 5.0V core supply is mandatory; plan power distribution and I/O banking for mixed 5.0V/3.3V operation, and verify pin compatibility between PQ208 and CQ208 packages when prototyping.