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DS90LV001TM - 800 Mbps 3.3V LVDS Buffer | Texas Instruments
The Texas Instruments DS90LV001TM is a 3.3 V single-channel LVDS-to-LVDS buffer designed for data rates up to 800 Mbps and supplied in an 8-pin SOIC package. It accepts an LVDS input signal and provides an LVDS output signal for rebuilding and distributing high-speed differential data across backplanes, cable assemblies, and board-to-board links. An LVDS buffer is a low-voltage differential-signaling interface device that improves signal integrity by receiving a differential data stream and retransmitting it as a new LVDS signal. In the technology hierarchy, LVDS signaling belongs to high-speed differential interface electronics, while the DS90LV001TM is specifically a signal buffer rather than a general-purpose logic gate, transceiver, or isolation device. Its buffering function can isolate a transmitter from downstream loading and can help extend usable routing options when transmission-line impedances are controlled. According to the Texas Instruments product page and manufacturer datasheet, key verified features include an 800 Mbps maximum data rate, 3.3 V supply operation, one buffered channel, CMOS technology, and an operating temperature range of -40 °C to +85 °C. The manufacturer describes the part as an LVDS-LVDS buffer, confirming that both the input and output use LVDS signaling. The distributor listings classify the DS90LV001TM as an 8-SOIC signal buffer or re-driver. At the circuit level, the device provides a defined input stage, an internal signal path, and an LVDS output stage intended for controlled-impedance routing. LVDS systems commonly require correct termination, controlled differential impedance, and careful branch or stub management. Because the verified data identifies the part as an 800 Mbps LVDS buffer but does not provide detailed rise-time, jitter, propagation-delay, input-capacitance, output-voltage, or differential-threshold figures, those characteristics should be confirmed in the manufacturer datasheet before release to production. Typical uses include LVDS clock distribution, point-to-point backplane links, cable extension, test and measurement equipment, industrial control systems, and communication equipment. In each case, the buffer is most useful when the source cannot reliably drive the complete downstream load or when regenerated edge behavior is preferable to continuing a lossy transmission-line segment. The principal design task is preserving the intended LVDS signal integrity at 800 Mbps. Use a controlled-impedance PCB layer, place the device close to the relevant connector or receiver, apply the termination scheme specified by the system architecture, and avoid unnecessary stubs. Power and ground pins should have low-impedance bypass connections close to the device. This page combines the verified Texas Instruments product information, distributor inventory references, package details, compatible orderable variants, and practical LVDS design guidance. It also distinguishes electrically equivalent catalog variants from true functional alternatives and identifies where detailed electrical, pricing, or lifecycle data still requires manufacturer confirmation.
DS90LV001TMX/NOPB - 800 Mbps LVDS Buffer | Texas Instruments
The Texas Instruments DS90LV001TMX/NOPB is a single-channel LVDS-to-LVDS buffer / re-driver that supports signaling rates up to 800 Mbps in an 8-pin SOIC (D) package with an exposed thermal pad area. The device takes a standard LVDS input signal and re-transmits an LVDS signal at the output, while operating from a single 3.3 V supply (3.0 V to 3.6 V) and consuming roughly 70 mA of supply current. It is qualified across the -40 C to +85 C industrial temperature range and is supplied in a tape-and-reel SOIC-8 package on a 3.90 mm body width. An LVDS buffer (Low-Voltage Differential Signaling buffer / re-driver) is a type of high-speed differential interface IC that regenerates and re-shapes a weak or distorted differential signal so it can drive another transmission line segment. In the broader system hierarchy it sits under interface ICs, then signal-conditioning devices, and ultimately under wired-connectivity semiconductors. LVDS buffers are essential building blocks in any system where the original LVDS transmitter cannot source enough current to reach a distant receiver while still meeting the TIA/EIA-644 eye-diagram mask. Key features of the DS90LV001TMX/NOPB include a 2.0 ns typical propagation delay, low jitter and low skew design that holds the differential output within tight limits, integrated 100 ohm input termination across the LVDS input pair, and an LVDS output stage that supports both point-to-point and multi-drop topologies. The device is designed to accept LVPECL inputs when AC-coupled, giving it cross-standard compatibility within the same SOIC-8 footprint. A single channel is provided per package, and the part is pin-to-pin compatible with the rest of the DS90LV001 family. Architecturally, the DS90LV001 uses a current-mode LVDS driver with on-chip bias generation. The differential receiver detects the incoming signal and re-times it through an internal logic stage that drives the output current-steering network. Because the part is a transparent buffer, it does not add protocol encoding or clock-data recovery - it simply regenerates the differential edge, restoring amplitude and common-mode level so the signal can traverse another cable, connector, or FR-4 stub. Typical applications for the DS90LV001TMX/NOPB include clock distribution across backplanes, buffering LVDS links between mezzanine cards, extending FR-4 trace runs in telecom and networking line cards, cable driving in point-to-point LVDS links, and acting as a stub-length isolator in large distributed systems where the unterminated stub length would otherwise limit the maximum achievable data rate. Designers also use it as a fan-out repeater when one LVDS source must drive two downstream loads. A key design consideration is the placement of external AC-coupling capacitors when LVPECL sources must be interfaced - these capacitors must be placed close to the device inputs to control the common-mode voltage. The DS90LV001's 8-pin SOIC footprint keeps the layout small but thermal performance is modest, so for applications that require higher output drive or multi-channel operation a higher-current or multi-channel LVDS part from the same family should be considered. This page synthesizes distributor stock, drop-in SOIC-8 alternatives, and practical PCB-layout notes not found in the manufacturer datasheet.
DS90LV017ATM - 600Mbps LVDS Driver | Texas Instruments
The Texas Instruments DS90LV017ATM is a single high-speed differential LVDS driver with data rates above 600 Mbps, equivalent to 300 MHz, in an 8-pin SOIC narrow package. It uses a 3.3 V supply, supports an operating temperature range from -40°C to 85°C, and is designed for low-power, high-speed point-to-point signal transmission. Its current-mode architecture maintains low power dissipation as operating frequency rises while also minimizing short-circuit fault current. An LVDS driver is a low-voltage differential-signaling interface circuit that converts a single-ended logic signal into two complementary differential outputs. LVDS belongs to the broader signal-interface and interface-IC hierarchy, where differential current-mode signaling reduces sensitivity to common-mode noise and supports reliable data transmission across printed-circuit-board traces or balanced cables. The differential outputs allow a receiver to interpret the voltage difference between the two conductors, improving noise immunity in systems operating at high data rates. The DS90LV017A family is optimized around three principal characteristics: operation above 600 Mbps, low power consumption, and controlled short-circuit fault current. The current-mode output stage is especially important at high frequencies because it avoids the rising power dissipation commonly associated with voltage-mode drivers. The manufacturer identifies the device as a single differential driver, making it useful when one channel is required without the channel count and pin count of a quad driver. The interface complies with the EIA-644-A and TIA-644-A technologies identified for this device family. Its operating characteristics are suited to high-speed point-to-point links in test equipment, industrial control, communications infrastructure, video systems, and data-acquisition equipment. In each case, the differential signaling method supports rapid data transfer while the low-power current-mode implementation helps manage system heat and board-space requirements. When laying out a circuit using the DS90LV017ATM, treat the two differential outputs as a controlled impedance pair. Route them together with matched geometry, minimize stubs, and provide the decoupling and return-path structure required by the manufacturer's application guidance. Keep the signal path away from unrelated switching nodes, because differential signaling improves common-mode rejection but does not eliminate sensitivity to coupled noise or impedance discontinuities. This product page combines the manufacturer's interface description, package and operating information, pricing structure, replacement guidance, and practical PCB implementation notes. It also distinguishes true same-footprint alternatives from related multi-channel LVDS devices, helping engineers evaluate upgrade paths without assuming that a related family member is electrically or mechanically interchangeable.
DS90LV017MX - 155Mbps LVDS Driver | Texas Instruments
The Texas Instruments DS90LV017MX is a single-channel LVDS differential driver with a 155 Mbps data rate, 3 V to 3.6 V supply range, and an 8-SOIC package. It converts one CMOS input into a balanced LVDS differential output for high-speed point-to-point communication links. The device is specified for 0°C to 70°C operation and is packaged in an 8-pin SOIC, making it suitable for industrial and commercial equipment requiring a compact differential line driver. An LVDS differential driver is an interface IC that transmits data across a balanced copper connection. LVDS, or Low-Voltage Differential Signaling, belongs to the interface IC family and uses complementary differential signals to improve noise immunity and reduce electromagnetic interference compared with single-ended logic. The DS90LV017MX provides one driver channel in a small 8-SOIC package for systems that need a single high-speed differential output. Key features include one LVDS driver channel, a 155 Mbps maximum data rate, operation from 3 V to 3.6 V, and a 0°C to 70°C operating-temperature range. The reported operating voltage allows the driver to be used with 3.3 V system rails, while the LVDS output supports low-voltage, high-speed signaling across suitable board-level or balanced-cable interconnects. The package is specified as 8-SOIC, with a 0.154 inch, 3.90 mm body width. The DS90LV017MX is intended for point-to-point links where a transmitter must launch a compliant differential signal into a controlled impedance interconnect. Because LVDS relies on balanced signaling, the receiving device, trace geometry, connector, and terminations determine whether the intended signal integrity and data-rate margins are achieved. The driver is therefore best suited to applications where the complete channel has been characterized rather than relying on the IC alone. Typical applications include industrial control links, test and measurement equipment, computer peripherals, point-to-point backplanes, and embedded communication interfaces. Its single-driver configuration makes it useful when a system needs one LVDS transmit path and requires a small package. The 0°C to 70°C temperature range supports commercial and industrial environments within that specified range. When designing around the DS90LV017MX, verify the input amplitude, supply sequencing, output termination, differential trace impedance, and receiver compatibility in the complete channel. The 3 V to 3.6 V supply range requires a valid 3.3 V rail, and the 0°C to 70°C rating must be checked against the equipment enclosure temperature. This product page consolidates distributor availability, package information, operating limits, verified cross-reference results, and practical selection guidance into one engineering-oriented reference for the DS90LV017MX LVDS driver.
DS90LV018ATM - 400 Mbps LVDS Receiver | Texas Instruments
The Texas Instruments DS90LV018ATM is a 3 V LVDS single CMOS differential line receiver capable of data rates above 400 Mbps, equivalent to 200 MHz, in an 8-pin SOIC package. It accepts a typical 350 mV differential LVDS input and translates it to 3 V CMOS logic levels. The receiver is designed for low power dissipation, low noise, high data rates, and robust operation in point-to-point balanced data links. An LVDS receiver is an interface IC that recovers a digital signal carried by two low-voltage differential conductors. LVDS belongs to the differential data-interface hierarchy, where the voltage difference between the pair carries the information while common-mode voltage rejection helps limit noise pickup. The DS90LV018A therefore belongs to the broader interface IC category, where it sits between a physical data link and the CMOS logic, processor, serializer, or test equipment receiving the recovered data. The device supports data rates in excess of 400 Mbps, or 200 MHz, while maintaining a typical differential input sensitivity of 350 mV. According to the Texas Instruments DS90LV018A datasheet, the receiver converts the differential LVDS input into 3 V CMOS output levels. It also supports open, shorted, and 100-ohm terminated-input fail-safe conditions, with the receiver output remaining HIGH in every specified fail-safe condition. The flow-through pin arrangement simplifies routing between the LVDS input connector or transceiver and the receiving digital circuitry. Its CMOS interface allows direct connection to compatible TTL or CMOS logic domains when voltage and timing requirements are satisfied. The architecture is intended for systems needing low power consumption and low noise without the complexity of a general-purpose differential receiver with programmable controls. The 8-pin SOIC outline also supports conventional surface-mount PCB assembly. Typical uses include industrial control links, test and measurement equipment, computer peripherals, video or imaging interfaces, and communication equipment operating over balanced cables. The receiver is especially useful where the transmitter produces an LVDS signal over a cable or PCB trace and the destination requires a single-ended CMOS result. System timing should still be evaluated across the complete transmitter, channel, receiver, and downstream logic path. When laying out the receiver, place input and output decoupling capacitors close to their associated power pins and keep the differential route compact, symmetrical, and away from noisy switching nodes. Use controlled-impedance routing where the interconnect behaves as a transmission line, and follow the datasheet's recommended termination arrangement for the source and receiver configuration. Verify signal integrity at the target data rate rather than relying only on a maximum-rate headline specification. This product page combines the manufacturer's core operating specifications, same-package replacement guidance, application-specific engineering guidance, and a parameter-by-parameter comparison. It is intended to shorten receiver selection while preserving the package, interface, and fail-safe details that determine whether an LVDS link can be deployed reliably.
DS90LV019TM - 3.3V/5V LVDS Transceiver | Texas Instruments
The Texas Instruments DS90LV019TM is a 3.3 V or 5 V low-voltage differential signaling transceiver containing one differential driver and one differential receiver in a 14-pin SOIC package. It supports data rates up to 100 Mbps and accepts TTL/CMOS-compatible driver inputs while providing a CMOS-compatible receiver output. The device is intended for high-speed, low-power point-to-point interconnects where differential signaling improves noise immunity and reduces EMI. An LVDS transceiver is an interface IC that converts a single-ended logic signal into a low-voltage differential pair on the transmit side and converts a received differential pair back into a single-ended logic signal on the receive side. In the signal-chain hierarchy, DS90LV019TM is an LVDS interface transceiver, belonging to the broader interface-IC and data-communications semiconductor categories. Its differential signaling is associated with the EIA-644-A and TIA-644-A technologies identified in the verified component data. Key features include independent operation of the driver and receiver, support for both 3.3 V and 5 V supplies, and a 3.5 mA LVDS output loop current. The 14-pin SOIC package uses a flow-through pin arrangement that permits short PCB routing between device pins and an external connector. A maximum data rate of 100 Mbps makes the device suitable for moderate-speed point-to-point links rather than very high-speed multimode channels. The architecture uses a current-mode differential driver to maintain controlled output current while transferring data across a balanced connection. Because the two transmission lines carry complementary signals, external circuitry reconstructs the logic state from their voltage difference. This approach can reduce sensitivity to common-mode noise relative to an unbalanced single-ended link, provided the receiver termination, connector, and cable geometry satisfy the interface requirements. Typical uses include industrial control links, test and measurement equipment, computer peripherals, video or display interconnects, and embedded systems that need a compact LVDS point-to-point interface. Because the driver and receiver are independent, a board can transmit and receive over separate balanced pairs. The 14-pin SOIC package is also suitable for conventional surface-mount PCB assembly where sufficient copper and solder mask clearance are available. Designers should preserve the flow-through routing advantage and keep LVDS traces short, properly terminated, and referenced to a continuous ground plane. Input and output logic levels must remain compatible with the selected 3.3 V or 5 V supply. Because the supplied excerpts do not provide a verified pin-number-to-pin-name table, the pinout is intentionally left unpopulated rather than presenting inferred connections as authoritative data. This page combines verified manufacturer and distributor information, package details, interface characteristics, application guidance, and strict drop-in equivalence analysis. It also distinguishes electrically similar parts that use a different package and therefore cannot be treated as true PCB drop-in replacements.
DS90LV027AHM - 600Mbps Dual LVDS Driver | TI
The Texas Instruments DS90LV027AHM is a dual LVDS differential driver optimized for high-data-rate and low-power applications, supporting data rates in excess of 600 Mbps (300 MHz) in an 8-pin SOIC package. It provides two driver channels, operates from a 3 V to 3.6 V supply, and uses a current-mode architecture to limit power dissipation at high frequency. The high-temperature grade supports operation from -40°C to +125°C. An LVDS driver is a line-driver interface that converts low-voltage digital signals into a differential low-voltage signal for reliable, high-speed transmission over balanced interconnects. Within the signal-chain hierarchy, the DS90LV027AHM belongs to the LVDS interface-driver category, uses Low Voltage Differential Signaling, and provides a current-mode differential output suitable for clock and data links. The device’s key features include support for data rates above 600 Mbps, a typical output swing of 360 mV, and low differential output swing for reduced EMI. Its flow-through pin arrangement simplifies PCB routing by allowing signals to pass through the device without changing direction. The driver architecture also provides short-circuit fault-current limiting, supporting fault-tolerant operation in cables and connectorized backplanes. Two independent differential outputs allow one package to drive two LVDS channels, reducing board area for parallel clock and data links. Because the outputs are current-mode devices, their power consumption remains low at high operating frequencies. The 3 V to 3.6 V supply range integrates directly with common low-voltage digital systems, while the high-temperature rating supports applications with extended ambient-temperature requirements. Typical uses include clock distribution, high-speed data transmission, industrial control links, test equipment, backplanes, and industrial systems requiring more than 600 Mbps operation. The DS90LV027AHM can be paired with the DS90LV028AH dual line receiver to form a complete differential transmission path when signal integrity and protocol requirements are compatible. PCB implementation should preserve the flow-through signal path, use a continuous ground reference plane, and minimize stubs on differential traces. Keep the input and output branches short, maintain closely matched trace geometry, and follow the manufacturer’s recommended supply bypassing and controlled-impedance layout practices. This page combines the manufacturer’s device characteristics, verified part identification, package information, practical interface-design guidance, and a strict assessment of drop-in replacement options to support faster engineering selection and sourcing.
DS90LV027M - Dual 600 Mbps LVDS Driver | Texas Instruments
Texas Instruments DS90LV027M is a dual LVDS differential line driver supporting data rates in excess of 600 Mbps, equivalent to a 300 MHz serialized data rate, in an 8-lead SOIC package. The device uses a 3.3 V supply, implements a low-power current-mode architecture, and minimizes short-circuit fault current. Its two differential outputs are intended for point-to-point, low-voltage, differential signaling over controlled-impedance interconnects. An LVDS driver is a high-speed interface device that converts low-voltage digital inputs into balanced differential outputs. LVDS belongs to the differential line-driver hierarchy within interface ICs, where it supports high data rates while limiting signal amplitude, crosstalk, and ground-reference sensitivity. The DS90LV027M is therefore positioned between general-purpose logic drivers and higher-power physical-layer drivers for links requiring a compact, low-voltage solution. Key characteristics include two LVDS outputs, operation from a 3.0 V to 3.6 V supply, a data rate above 600 Mbps, and a nominal 3.3 V operating point. The current-mode implementation is significant because it allows power dissipation to remain comparatively low at high operating frequencies. Reduced fault current also improves robustness when an output is shorted. According to the manufacturer product information, the package uses a flow-through pin arrangement intended to simplify PCB routing. The device is suited to high-speed point-to-point links, including display and panel interfaces, industrial control links, communications equipment, and embedded digital systems. The dual-channel architecture lets one package drive two independent differential channels, reducing component count and simplifying synchronization when both channels carry related data. PCB design should preserve controlled differential impedance and minimize the distance between each output and its receiver. Input and output return paths should be referenced consistently, and unused inputs must not be left floating. Because the verified source data does not provide the complete numbered pin assignment, termination guidance, or electrical-characteristic tables, those engineering details should be confirmed against the manufacturer datasheet before layout release. This page consolidates the verified manufacturer description, distributor packaging information, device parameters, and practical replacement guidance. It also distinguishes documented ordering-code differences from a genuine cross-brand drop-in claim, helping engineers make a sourcing decision without confusing functional similarity with PCB compatibility.
DS90LV027MX - Dual 600Mbps LVDS Driver | Texas Instruments
Texas Instruments DS90LV027MX is a dual CMOS LVDS differential driver optimized for high-data-rate, low-power signal transmission. It supports data rates in excess of 600 Mbps, operates from a nominal 3.3 V supply, and is packaged in an 8-lead SOIC. Each channel uses a current-mode differential driver, while the device’s flow-through pin arrangement simplifies high-speed PCB routing. According to the Texas Instruments product page, the driver maintains low power dissipation at high frequency and minimizes short-circuit fault current. Its differential outputs typically swing about 340 mV, providing low EMI while transferring clock and data signals. The DS90LV027MX is therefore positioned between general-purpose logic interfaces and the broader LVDS interface-IC category, where differential signaling, controlled output current, and low-noise operation are central requirements. An LVDS driver is a line and bus driver that converts a low-voltage CMOS logic input into a balanced differential output. Because LVDS transmits information as the voltage difference between two conductors, it can support high data rates while reducing sensitivity to common-mode noise and limiting electromagnetic emissions. The DS90LV027MX includes two independent differential drivers, allowing clock, data, control, or serial-interface signals to be transmitted in parallel. Its dual-channel architecture increases routing flexibility while conserving board area compared with two separate single-channel devices. The manufacturer describes the DS90LV027 as a current-mode driver optimized for high-data-rate and low-power operation. This architecture helps power dissipation remain low as operating frequency increases and also reduces the short-circuit fault current available from the outputs. Differential output swing is typically 340 mV, which supports LVDS-compatible receivers and limits output voltage excursions. The 8-lead SOIC package uses a flow-through layout intended to make PCB layout easier, particularly when traces must pass through or around the device on high-speed digital boards. The verified device information identifies DS90LV027MX as a 2/0 LVDS driver in an 8-SOIC package. The related lead-free DS90LV027MX/NOPB listing identifies a 3.0 V to 3.6 V supply range, while Mouser lists the commercial-temperature variant at 0°C to 70°C. The DS90LV027 family is designed for data rates in excess of 600 Mbps, equivalent to more than 300 MHz of serialized information according to the family description. The current-mode implementation and controlled differential swing help balance high throughput, power consumption, and EMI control. Typical uses include clock distribution, parallel-to-serial data links, industrial-control interfaces, test and measurement equipment, video timing links, and communications systems that transmit high-speed clock or data over balanced lines. Because the DS90LV027MX provides two differential outputs, a board designer can use one channel for a clock and another for data, or deploy two independent data streams. In each case, the receiver, cable, connector, and PCB geometry must be designed consistently with LVDS signal integrity requirements. The most important layout consideration is to preserve controlled differential impedance and minimize the distance over which the two traces of a pair are separated. Place decoupling close to the supply pins, route the differential pair as a tightly coupled pair, and avoid unnecessary stubs or test-point discontinuities. The 8-lead SOIC footprint is easy to source, but package parasitics, connector transitions, and imperfect pair geometry can still reduce the practical benefit of the device’s high supported data rate. This product page combines the verified Texas Instruments and distributor information with package, application, selection, and design guidance. It also distinguishes confirmed ordering variants from unsupported substitutes and identifies every parameter that still requires confirmation from the manufacturer datasheet or distributor record.
DS90LV028AHM - 3V LVDS Dual Differential Line Receiver | Texas Instruments
The Texas Instruments DS90LV028AHM is a dual CMOS differential line receiver designed for ultra-low power dissipation, low noise and high data rates, housed in an 8-pin SOIC package. It accepts low-voltage differential signals of 350 mV typical and translates them to CMOS/TTL logic levels, supporting data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology. An LVDS receiver is a type of line receiver that converts a small-amplitude differential pair into a single-ended digital output. Differential signaling belongs to the broader hierarchy of interface ICs, because common-mode rejection, equalization and low swing allow reliable transfer over longer cables or PCB traces where single-ended signals would be corrupted by noise. The DS90LV028AH is the receiving half of a point-to-point link; the matching line driver is the DS90LV027A family. Key characteristics of the DS90LV028AHM include support for 400 Mbps (200 MHz) data rates, a 3.3 V supply rail, a flow-through pin arrangement that simplifies point-to-point PCB routing, and a high-temperature grade rated from -40 C to +85 C for industrial and automotive-adjacent environments. The dual-channel architecture lets one package carry two independent LVDS links, reducing board area in multi-channel point-to-point systems. Internally the receiver uses CMOS logic with differential input stages, giving low power dissipation compared with PECL or ECL receivers while retaining low noise. Because LVDS receivers present a high-impedance differential input, the part draws minimal DC current from the driver, which increases the achievable link distance and reduces connector and cable loading. The flow-through layout places input pins opposite output pins so the device can sit in-line on a board edge or cable-riser interface. Typical applications include backplane and board-to-board point-to-point links, industrial and telecom backplanes, video and imaging data paths, and instrumentation or test equipment that needs high-rate transfer over a few metres of twisted pair. It is also used where a high-power PECL/ECL receiver would waste power, since the LVDS approach delivers the same throughput at a fraction of the power. When designing with this receiver, keep differential trace pairs tightly coupled with matched length and controlled impedance, and provide solid ground-plane return under the pair. The 3.3 V supply should be decoupled close to the VCC pin. Because the part is a high-temperature grade variant, verify your system ambient and the associated operating limits against the datasheet before using it in elevated-temperature locations. This page brings together the manufacturer specifications, drop-in ordering-code options for the same die, and practical layout and signal-integrity guidance that engineers normally have to piece together from several separate documents.
DS90LV028ATM - Dual 400 Mbps LVDS Receiver | Texas Instruments
Texas Instruments DS90LV028ATM is a dual CMOS differential line receiver for Low Voltage Differential Signaling (LVDS) data links, supporting data rates in excess of 400 Mbps (200 MHz) in an 8-pin SOIC package. The receiver accepts a typical differential input voltage of 350 mV and converts each LVDS input into a CMOS-compatible logic output. Its dual-channel architecture allows one package to receive two independent low-voltage differential signals. An LVDS receiver is an interface IC within the broader line-receiver and interface-IC hierarchy. LVDS is a differential signaling technology in which data is transmitted as the voltage difference between two complementary conductors. That architecture provides useful noise immunity for high-speed links, while the receiver converts the small differential signal into a single-ended CMOS output that can be processed by digital logic, a controller, or a field-programmable gate array. According to the Texas Instruments DS90LV028A product page, the device is designed for applications requiring ultra-low power dissipation, low noise, and high data rates. The verified technical summary identifies a maximum data rate in excess of 400 Mbps, equivalent to a 200 MHz parallel data rate. The related distributor data also identifies a 3 V supply class, a 1.5 ns receiver performance figure, and approximately 9 mA of operating current, although the exact test conditions are not included in the supplied excerpts. The DS90LV028A family provides two independent receiver channels, making it useful in point-to-point industrial links, test and measurement equipment, instrumentation, and backplane communication. The 8-pin SOIC footprint simplifies assembly in designs that already use conventional surface-mount packages. Because LVDS is a differential interface, each receiver channel requires a matched differential input and appropriate cable or board-level termination. Designers should preserve the receiver's common-mode operating limits, provide the specified termination network, and maintain a controlled return path between the transmitter and receiver. Differential routing on the printed circuit board should minimize impedance discontinuities and keep the pair length-matched. The receiver should also be evaluated for fail-safe behavior when the cable is open, shorted, or terminated because those conditions affect receiver metastability and output state. This product page consolidates the verified manufacturer specifications, distributor identifiers, package information, application guidance, and substitution constraints for DS90LV028ATM. It also distinguishes a true pin-compatible replacement from similar LVDS receivers that require a different pinout, circuit modification, or data-rate tradeoff.
DS90LV031ATM - 3V Quad LVDS Line Driver | Texas Instruments
The Texas Instruments DS90LV031ATM is a 3V quad CMOS differential line driver designed for low-power, high-speed LVDS communication links. It supports data rates in excess of 400 Mbps, equivalent to a 200 MHz clock rate, and translates low-voltage LVTTL or LVCMOS inputs into four low-voltage differential outputs. The device is packaged in a 16-pin SOIC. An LVDS line driver is a differential interface component that converts a single-ended CMOS logic signal into two complementary low-voltage outputs. This differential signaling method reduces common-mode noise, lowers electromagnetic emissions, and improves signal integrity over longer point-to-point interconnects. In the broader component hierarchy, the DS90LV031A belongs to the line-driver family, interface IC category, and high-speed digital communication ecosystem. The principal features of the DS90LV031ATM include four differential drivers, operation from a 3V supply, support for rates above 400 Mbps, and common enable controls for tri-state output operation. LVTTL and LVCMOS input compatibility allows the device to interface directly with common digital logic families. The common EN and EN-bar controls support active-high or active-low output enable management while coordinating all four channels. The DS90LV031A architecture provides a practical alternative to high-power pseudo-ECL devices in point-to-point interface systems. Differential output signaling improves noise immunity by rejecting noise that appears equally on both output conductors. Its CMOS implementation is intended for systems where data throughput matters more than the very short reach and low logic levels associated with conventional ECL devices. Typical uses include clock distribution, parallel data links, backplane communication, telecommunications equipment, industrial control systems, and test and measurement instruments. The companion DS90LV032A receiver provides the corresponding four-channel differential receiving function for complete point-to-point links. PCB layout is critical when operating at LVDS rates. Use controlled-impedance routing, keep differential pairs closely coupled, minimize stub lengths, and place any termination components close to the receiving device. Confirm the output voltage, supply tolerance, propagation delay, and enable timing in the manufacturer datasheet before releasing a high-volume design. This page organizes the device characteristics, pin and package requirements, application guidance, and verified drop-in alternatives into one engineering reference. It also highlights practical distinctions between the standard, lead-free, and related DS90LV031A ordering codes so that compatibility can be checked before a PCB respin or production release.
DS90LV032ATM - 400 Mbps 4-Channel LVDS Receiver | Texas Instruments
Texas Instruments DS90LV032ATM is a 3 V LVDS quad differential line receiver designed for high-speed point-to-point data links. It converts four low-voltage differential input pairs into 3 V CMOS outputs while supporting data rates in excess of 400 Mbps, equivalent to a 200 MHz clock rate. The device is packaged in a 16-pin narrow SOIC and is identified by the DS90LV032A family designation. An LVDS receiver is an interface circuit that recovers a digital signal from a small differential voltage carried over a balanced pair of conductors. LVDS belongs to the broader class of differential line receivers and interface ICs used to move high-speed data reliably between boards, backplanes, and rack-mounted systems. The DS90LV032A accepts low-voltage differential signals, typically 350 mV, and translates them into CMOS-compatible logic levels for downstream digital circuits. Key features of the DS90LV032ATM include four independent receiver channels, data-rate operation above 400 Mbps, and a single 3 V supply. The receiver architecture is suited to low-power consumption and high-speed digital communication. The 16-pin SOIC package allows direct comparison with other 16-pin LVDS receiver families, although input and output pin functions should always be verified against the specific manufacturer datasheet before substitution. The DS90LV032A is commonly used in point-to-point LVDS links, test and measurement equipment, industrial control systems, and digital backplanes. Its differential inputs help reject common-mode noise, while the CMOS outputs connect directly to FPGA, ASIC, or other digital logic inputs. The device supports data rates beyond 400 Mbps, making it appropriate for high-speed clock, control, and data-transfer connections. Designers should pay attention to differential pair routing, controlled-impedance transmission lines, connector and via geometry, and the receiver supply decoupling. The TI DS90LV032A datasheet is the authoritative source for input thresholds, propagation delay, supply-current behavior, and absolute maximum ratings. The manufacturer product page identifies the DS90LV032A as an active 3 V LVDS quad CMOS differential line receiver, while the DS90LV032ATM orderable designation is listed in a 16-pin SOIC package. This page combines the manufacturer datasheet, product-page information, distributor records, and cross-reference results for the DS90LV032ATM. It also provides application guidance, package-level design notes, comparison parameters, and drop-in alternative candidates for engineers evaluating an LVDS receiver redesign or second-source plan.
DS90LV032TMX - Quad LVDS Receiver | Texas Instruments
Texas Instruments DS90LV032TMX is a four-channel differential line receiver that translates low-voltage differential signaling into 3-V CMOS output signals. It supports data rates in excess of 400 Mbps, equivalent to 200 MHz, accepts differential inputs with a typical signal magnitude of 350 mV, and is packaged in a 16-pin flat-pack configuration. The device is intended for high-speed point-to-point connections requiring low power dissipation and reliable differential-signal detection. A low-voltage differential signaling receiver is a line receiver that distinguishes the voltage difference between two conductors rather than the voltage referenced to ground. LVDS belongs to the broader interface-IC and data-converter interface hierarchy. Its differential architecture reduces sensitivity to common-mode noise, supports low-voltage signaling, and is commonly used when a system must transfer clock or data signals over a compact cable or PCB trace. The DS90LV032TMX provides four receiver channels, operation beyond 400 Mbps, and translation of approximately 350 mV differential input signals to 3-V CMOS levels. Its four-channel arrangement allows one receiver package to handle four independent data paths or multiple clock and data lanes. The low-power design is useful when the receiver must operate close to high-speed processors, FPGAs, serializers, or test equipment without adding substantial system power. Internally, the receiver compares the two differential inputs for each channel and uses the polarity of that voltage difference to recover the intended logic state. Differential detection rejects noise that appears equally on both inputs, while the CMOS output interface connects the recovered data to ordinary digital logic. The exact supply-voltage limits, propagation-delay limits, input-current limits, and temperature ratings should be taken from the manufacturer data sheet before finalizing a high-speed design. Typical applications include LVDS clock distribution, camera and video interfaces, industrial control links, test-and-measurement equipment, and general-purpose high-speed digital connections. Quad-channel density is particularly attractive when a design needs several low-voltage differential inputs but has limited board space. The receiver can also support links operating below its maximum rated speed when the source amplitude, termination, trace geometry, and timing budget satisfy the interface requirements. PCB implementation should preserve the differential characteristics of each input pair. Route the two conductors of a channel as a tightly coupled pair, provide the specified input termination, avoid stubs, and keep return-path discontinuities away from the signal traces. Differential impedance, receiver input capacitance, connector geometry, and source-edge rate can affect eye opening and therefore determine whether a nominal 400-Mbps-capable receiver maintains adequate margin. This product overview combines the DS90LV032 family specifications, package information, sourcing context, and practical implementation guidance. It also distinguishes exact-family replacements from electrically similar receivers that may use different thresholds, supply rails, or pin arrangements, helping engineers narrow a replacement search before committing to a board-level substitution.
DS90LV047ATMTC/NOPB - 400 Mbps LVDS Quad Driver | TI 16-TSSOP
The Texas Instruments DS90LV047ATMTC/NOPB is a 400 Mbps (200 MHz) quad CMOS flow-through differential line driver implementing Low Voltage Differential Signaling (LVDS) technology, housed in a 16-pin TSSOP package. The device accepts LVTTL/CMOS input levels and translates them to a 350 mV differential LVDS output, providing ultra-low power dissipation and high data rates for point-to-point high-speed interface applications. A line driver in the LVDS family is a transceiver front-end component that converts single-ended logic levels into a low-voltage differential pair, and the DS90LV047A belongs to that LVDS sub-family which also includes line receivers (DS90LV048A), transceivers (DS90LV049), and serializers/deserializers. Within the broader hierarchy of interface ICs, LVDS drivers sit under differential signaling ICs, which themselves sit under interface ICs, then under wired-connectivity ICs, and finally under integrated circuits. The DS90LV047A and companion line receiver DS90LV048A provide an alternative to high-power pseudo-ECL devices, offering CMOS-level power consumption with multi-hundred-megahertz switching speeds. Key features include four independent drivers with flow-through pinout, typical differential output swing of 350 mV across a 100 ohm load, support for data rates in excess of 400 Mbps (200 MHz toggle rate), and 3.3 V nominal supply operation from 3.0 V to 3.6 V. Flow-through pin ordering simplifies PCB routing by allowing the input on one side and the LVDS output on the opposite side, which reduces layer count and via usage. The architecture uses a current-mode LVDS driver stage with on-chip termination, providing controlled edge rates, low EMI, and robust common-mode noise immunity. The wide common-mode range on the differential pair and the LVDS standard's inherent noise margin allow reliable transmission over FR-4 backplanes and ribbon cable at lengths exceeding several meters. Typical applications include LCD display row/column drivers, board-to-board high-speed data links, clock distribution networks, printers and copiers, network switches and routers, and backplane interconnect for telecommunications equipment. The device is also commonly paired with the DS90LV048A quad receiver to form complete LVDS links. When designing with this device, maintain a 100 ohm differential termination at the receiver end of the pair, place decoupling capacitors close to the VCC pin, and keep differential traces matched within 10 mil to preserve duty-cycle balance and minimize reflections. This page synthesizes distributor pricing, drop-in TSSOP alternatives, and practical design guidance not found in the manufacturer datasheet.
DS90LV047ATMTCX - 400Mbps Quad LVDS Driver | Texas Instruments
The Texas Instruments DS90LV047ATMTCX is a 400 Mbps quad CMOS flow-through differential line driver with four LVDS transmitters, a 3 V to 3.6 V supply range, and a 16-pin TSSOP (PW) package. It converts low-voltage TTL/CMOS inputs into low-voltage differential LVDS outputs for high-speed point-to-point interfaces. The device supports data rates in excess of 400 Mbps, equivalent to more than 200 MHz according to the manufacturer product page. An LVDS differential line driver is an interface IC that transmits complementary signals through a balanced pair. Because the two conductors carry equal and opposite signals, the transmitted signal is less susceptible to common-mode noise than a single-ended interface. This makes the DS90LV047A family suitable for links requiring low power consumption, high data rates, and reliable point-to-point signal transfer across a board or cable. The principal verified features are four differential outputs, a 3 V to 3.6 V supply, a 400 Mbps signaling rate, and low-voltage differential signaling. The flow-through architecture supports signal routing where data enters and exits on corresponding package sides. The manufacturer identifies the device as an alternative to high-power pseudo-ECL devices in high-speed point-to-point interface applications. The DS90LV047ATMTCX is a line driver rather than a receiver, ADC, DAC, or transceiver. Each of its four channels accepts TTL or CMOS logic and produces an LVDS differential output. The 16-pin TSSOP package is suitable for compact surface-mount layouts, while the quad-channel arrangement reduces the number of interface ICs needed when several independent links are required. Typical applications include high-speed backplanes, point-to-point industrial links, digital video and control paths, communications equipment, and instrumentation requiring reliable differential transmission. The companion DS90LV048A family provides line receivers, allowing a transmitter and receiver pair to be designed into a complete LVDS link. For PCB design, place the driver close to the source device, route differential pairs with matched geometry, and keep the pair away from unrelated high-current switching nodes. Confirm LVDS output amplitude, receiver compatibility, termination, and edge-rate requirements using the manufacturer datasheet before releasing a new layout. This page combines verified manufacturer and distributor information with practical interface design guidance, application context, and replacement considerations that are not present in a raw distributor listing.
DS90LV048ATM - 400 Mbps Quad LVDS Receiver | Texas Instruments
The Texas Instruments DS90LV048ATM is a 3.3 V quad CMOS differential line receiver supporting LVDS signaling rates above 400 Mbps, equivalent to 200 MHz, in a 16-pin SOIC package. It accepts differential inputs with a typical signal amplitude of 350 mV and provides four independent receiver channels for high-speed point-to-point data links. The device is designed for low-power operation and an industrial temperature range of -40°C to +85°C. An LVDS receiver is an interface integrated circuit that converts a low-voltage differential signal into a complementary CMOS logic output. LVDS, or Low Voltage Differential Signaling, belongs to the differential interface IC hierarchy and supports reliable high-speed communication by comparing the voltage difference between two conductors. By rejecting common-mode noise and using low swing levels, LVDS is well suited to compact industrial, communications, and data-processing systems. The DS90LV048A family provides four flow-through differential receivers and supports data rates in excess of 400 Mbps. Its 350 mV typical differential input amplitude allows it to operate with the companion DS90LV047A line-driver family. The receiver architecture translates each differential LVDS input into a CMOS output suitable for downstream digital logic, while its quad-channel organization consolidates four links into one 16-pin device. The flow-through arrangement helps preserve signal timing by keeping the data path direct through the package. This is particularly valuable in point-to-point links where receiver-to-logic propagation delay must remain predictable. A listed 1.5 ns propagation-delay value and 15 mA operating-current figure place the device in the low-power, high-speed interface class, although application-specific limits should be checked against the manufacturer datasheet before final timing and power-budget calculations. Typical uses include point-to-point links between a transmitter and field-programmable gate array, industrial control equipment, video-processing systems, and other high-speed digital backplanes. The quad receiver can reduce component count when four differential channels are required. It is also appropriate where a 3.3 V supply and CMOS outputs match the receiving logic, while cable length, connector behavior, connector pin assignments, and system-level LVDS timing remain design constraints. For PCB implementation, place the receiver close to the source connector, route the differential pair as a tightly coupled pair, and provide a solid ground reference. Keep unused receiver inputs properly terminated according to the device recommendations. Confirm supply sequencing, output-load limits, and the relationship between input threshold, propagation delay, and system timing before operating the link at its maximum data rate. This product overview combines the manufacturer's functional description with package, interface, sourcing, replacement, and layout guidance. It also distinguishes genuine same-footprint receiver options from functionally similar parts that require separate electrical and timing review, helping engineers select a replacement without overlooking enable, pinout, or temperature requirements.
DS90LV048ATMTCX - 400 Mbps Quad LVDS Receiver | TI
Texas Instruments DS90LV048ATMTCX is a four-channel CMOS flow-through differential line receiver that supports LVDS data rates above 400 Mbps (200 MHz), operates from a 3 V to 3.6 V supply, and is packaged in a 16-pin TSSOP (PW). It converts four low-voltage differential inputs into four CMOS outputs. An LVDS receiver is an interface circuit that recovers a digital signal from a low-voltage differential pair. LVDS belongs to differential line-driver and receiver technology within interface ICs. Its two-wire differential signaling helps reject common-mode noise, while the receiver converts the small differential voltage into a logic-level signal for downstream digital equipment. Key verified features include four differential receivers, data rates in excess of 400 Mbps, a typical differential input signal of 350 mV, and a 3 V to 3.6 V supply range. The flow-through architecture supports high-speed point-to-point links while its CMOS outputs connect the recovered data to controllers, FPGAs, test equipment, or other digital logic. The DS90LV048A family is positioned for low-power, high-rate LVDS communication. Unlike a single-channel receiver, this quad device consolidates four channels into one package. Its supply voltage matches the provided DS90LV048A product description, while the 16-TSSOP package supports conventional surface-mount assembly. Exact propagation delay, input thresholds, output timing, and current limits are not supplied in the verified excerpts and therefore are not inferred here. Typical uses include multi-channel digital backplanes, point-to-point data links, industrial control interfaces, communications equipment, and FPGA or controller connectivity. The receiver is most appropriate where four LVDS pairs must be converted to CMOS logic on a 3.3 V system. Designers should preserve the differential pair geometry, provide a clean reference ground, route the two members of each pair together, and verify input common-mode and timing requirements against the complete manufacturer datasheet. The verified source identifies DS90LV048A rather than a complete revision-specific pin table for this exact orderable suffix. This page combines manufacturer and distributor findings with package, application, lifecycle, and purchasing guidance while clearly separating verified facts from unavailable electrical details.
DS90UB947TRGCRQ1 - 1080p oLDI Dual FPD-Link III Serializer | TI
The Texas Instruments DS90UB947TRGCRQ1 is a 1080p OpenLDI (oLDI) to FPD-Link III dual serializer with up to 3.36 Gbps forward-link data rate, packaged in a 64-pin VQFN (RGC) 9x9 mm with exposed thermal pad. It converts parallel RGB/YCbCr video plus I2S audio and control data into a single differential pair for transmission over STP/AWG cable to a matching DS90UB948/DS90UH948 deserializer. What is a serializer/deserializer (SerDes) channel? A serializer is a mixed-signal interface IC that compresses a wide parallel bus (LVCMOS color, sync, audio, control) into a high-speed serial differential link using embedded clock technology. FPD-Link III is TI's proprietary SerDes family used for automotive and industrial displays where EMI, cable weight, and connector count must be minimized. A serializer sits on the SoC/FPGA side of the harness and a deserializer on the display side, replacing 20-30 LVDS lanes with a single twisted pair. Key features of the DS90UB947TRGCRQ1 include 3.36 Gbps forward channel, a 40 kbps to 1 Mbps back-channel return path for touch/control data, support for WUXGA (1920x1200) and 1080p60 in non-reduced-blanking mode, multi-channel I2S audio, and adaptive equalization at the deserializer side. The device supports up to 24-bit color depth and offers backward-compatible operation at WXGA and 720p over a single link. The device uses low-voltage differential signaling (LVDS), data scrambling, and randomization to minimize EMI - critical for CISPR 25 Class 5 automotive compliance. Internal pattern generation and BIST modes allow in-system link validation without external equipment. Typical applications include automotive infotainment head units, ADAS driver-assist displays, rear-seat entertainment, instrument clusters, and industrial HMI panels where a single twisted pair must replace wide parallel RGB harnesses. When designing with the DS90UB947TRGCRQ1, choose a matched DS90UB948-Q1 (1080p) or DS90UH948-Q1 (4K) deserializer, plan for 100-ohm differential routing of the FPD-Link III pair, and use TI's WEBENCH FPD-Link III tool to validate cable length and pre-emphasis settings. This page synthesizes distributor pricing, AEC-Q100 qualification evidence, drop-in package-compatible alternatives, and practical PCB layout notes not found in the manufacturer datasheet alone.
DS90UB948TNKDRQ1 - 1080p FPD-Link III Deserializer | Texas Instruments
The Texas Instruments DS90UB948TNKDRQ1 is a 1080p oLDI Dual FPD-Link III Deserializer that converts 1-lane or 2-lane FPD-Link III serial streams back into an OpenLDI (FPD-Link) parallel interface, supporting up to 3.36 Gbps throughput per lane and housed in a 64-pin WQFN (9x9 mm) package. Designed to pair with the DS90UB949A-Q1, DS90UB949-Q1, or DS90UB947-Q1 serializers, it recovers clock, video data, control, and GPIOs over cost-effective 50 ohm single-ended coaxial or 100 ohm differential shielded twisted-pair (STP) cabling. The device supports dual LVDS output ports (Port 0 and Port 1) with a maximum output data rate of 3.36 Gbps and is AEC-Q100 qualified for automotive camera, infotainment, and instrument-cluster applications. Operating from a 1.8 V supply, the deserializer integrates adaptive equalization, clock data recovery, and dual-link OpenLDI formatting for resolutions up to 1920x1080p at 60 Hz. An FPD-Link III deserializer is a serializer-deserializer (SerDes) receiver IC that converts high-speed serialized LVDS-style differential streams into a parallel RGB/LVDS display interface, enabling long-reach video transmission over a minimal wire count while embedding a bidirectional control channel and DC-balanced data scrambling for EMI reduction. In the broader system taxonomy, this device sits inside interface ICs -> serializer/deserializer (SerDes) -> automotive video interface, sitting above physical-layer transceivers and below the display timing controller. Key features include dual-port LVDS/OOpenLDI output, integrated adaptive receiver equalization supporting up to 10 m of coax or 15 m of STP cable at full speed, I2C-compatible control channel with up to 400 kHz pass-through, 9+ bidirectional GPIOs, hardware BIST (Built-In Self-Test), and an INT/AT power protection profile. The 64-pin WQFN package with exposed thermal pad provides low thermal resistance for automotive-grade operating temperature ranges. The device is suitable for ADAS surround-view, rear-view, and e-mirror camera systems that demand high-bandwidth uncompressed video over robust automotive cabling. Typical applications include automotive 1080p camera deserialization for ADAS platforms, surround-view and rear-view camera hubs, digital instrument cluster displays, in-vehicle infotainment (IVI) head units, and LVDS-to-OOpenLDI bridge designs replacing legacy parallel RGB links. When designing, place 0.1 uF and 1 uF decoupling capacitors adjacent to each supply pin and route the FPD-Link III differential traces as a 100 ohm differential pair with controlled 50 ohm single-ended impedance for coax variants.
DS90UH949TRGCTQ1 - 1080p HDMI to FPD-Link III Bridge | TI
The Texas Instruments DS90UH949TRGCTQ1 is a 1080p HDMI-to-FPD-Link III bridge serializer with HDCP support, supplied in a 64-pin VQFN (RGC) package (9 mm x 9 mm) with exposed thermal pad. It serializes HDMI input up to WXGA and 720p resolutions at 24-bit color depth in backward-compatible mode, and up to 1080p with deep color support in FPD-Link III mode, delivering 5.95 Gbps over a single differential pair to a paired FPD-Link III deserializer such as the DS90UH928Q or DS90UH940-Q1. Key specifications include a 5.95 Gbps forward-channel data rate (up to 2.975 Gbps per lane), integrated HDCP 1.4 cipher engine for content-protected video transport, an embedded clock over the bidirectional control channel, and an I2C-compatible pass-through interface for remote peripheral access. The device accepts up to three digital-input video sources and provides an adaptive equalization receiver on the back-channel, enabling operation across long-distance STP or coaxial cables commonly used in automotive infotainment backbones. A serializer/deserializer pair, often abbreviated SerDes, is a fundamental building block of modern in-vehicle video distribution. SerDes converters sit in the signal chain between a graphics source (HDMI, DSI, OpenLDI) and a remote display panel, compressing parallel RGB/clock lines into a high-speed serial stream and embedding the clock in the data - which dramatically reduces wiring harness count, EMI, and connector pin count. FPD-Link III is TI's third-generation Flat Panel Display Link family, designed for AEC-Q100-qualified automotive display modules; it adds HDCP content protection, bidirectional I2C/audio transport, and adaptive equalization on top of the original FPD-Link II architecture. A differential output architecture and integrated PLL with low jitter reduce the need for external clock-recovery components. Automotive-grade qualification (AEC-Q100) makes the DS90UH949TRGCTQ1 a drop-in solution for head-unit-to-display video transport in instrument clusters, center-stack displays, and rear-seat entertainment. Compatibility with backward-mode 24-bit color and reduced blanking formats lets the same part serve legacy panels. Typical applications include automotive head-unit video links, digital instrument clusters, HUD projectors, and rear-seat entertainment displays. The DS90UH949TRGCTQ1 also serves industrial touch-panel bridges and medical imaging displays where HDCP-protected video must traverse long cables. The device pairs naturally with the DS90UH940-Q1 deserializer for full HDCP-end-to-end support. When designing with this part, follow TI's reference layout for the 64-VQFN exposed pad, which provides the primary thermal path; insufficient solder coverage will derate the thermal envelope. Use AC-coupled interconnects on the FPD-Link III output, keep the HDMI input traces impedance-controlled at 100 ohms differential, and place the local 1.8 V/3.3 V decoupling within 5 mm of each supply pin. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
DS90UR124QVS - 24-Bit FPD-Link II Deserializer | Texas Instruments
The Texas Instruments DS90UR124QVS is a 24-bit DC-balanced FPD-Link II deserializer for parallel-to-serial display interfaces. According to the manufacturer product page, it supports a 5 MHz to 43 MHz pixel-clock range and a maximum data rate of 1.03 Gbps. The device is packaged in a 64-pin TQFP package measuring 10 mm by 10 mm and is also available in an automotive-grade ordering option designated DS90UR124QVS/NOPB. An FPD-Link II interface is a serializer and deserializer technology used to transfer video data, control signals, and clock information over low-voltage differential signaling pairs. The DS90UR124 receives one serial FPD-Link II input and reconstructs 24 parallel outputs, providing a transparent link between a graphics source and a display receiver. Embedded clock forwarding removes the need for a separate source-synchronous clock trace, reducing the number of interconnects required for a wide parallel display bus. The interface supports DC-balanced 24-bit transfers, including pixel data and associated synchronization or control channels. Its 5 MHz to 43 MHz clock range covers display timing requirements commonly encountered in industrial panels, automotive graphics systems, and embedded human-machine-interface displays. A maximum serial rate of 1.03 Gbps provides ample link headroom for the supported pixel-clock interval. The DS90UR124 is the receiving half of the DS90UR241/124 chipset. The companion serializer converts a 24-bit parallel bus into a fully transparent FPD-Link II LVDS stream with embedded clock information. TI identifies this chipset as suitable for graphical data transport to displays requiring 18-bit color depth using RGB666 plus horizontal sync, vertical sync, data enable, and three additional general-purpose data channels. The 64-pin TQFP package provides the required LVDS input, parallel data outputs, supply rails, reference network, and control connections. Because the package is not a thermally exposed package, board-level copper and airflow remain important when the deserializer operates near its full data rate in a high-temperature enclosure. Automotive-qualified ordering information identifies an operating range of -40°C to 105°C for the Q1 variant. When integrating the DS90UR124, preserve the LVDS pair routing recommended in the manufacturer datasheet, keep the input pair geometry symmetrical, and place the required network and bypass components close to their associated pins. The deserializer also requires a stable reference for correct lane detection and data reconstruction, making reference-network layout as important as the high-speed differential routing. This page summarizes the interface architecture, ordering options, application roles, and design considerations that help engineers evaluate the DS90UR124QVS before integrating it into an LVDS display link.
DS90UR241IVS - 1.03Gbps 24-Bit FPD-Link II Serializer | TI
Texas Instruments DS90UR241IVS is a 1.03 Gbps, 24-bit FPD-Link II serializer designed for parallel-to-serial video and control-data transmission over low-voltage differential signaling links. It accepts a 24-bit parallel input operating from 5 MHz to 43 MHz, consolidates the associated clock and control signals into a serial stream, and provides one differential LVDS output in a 48-pin TQFP package measuring 7 mm by 7 mm. The device is intended for point-to-point display and graphics interfaces where a compact, low-noise serial link can replace a wide parallel bus. An FPD-Link II serializer is an interface IC within the LVDS serializer and deserializer chipset category. Its function is to convert a parallel source bus into a high-speed differential data stream while preserving timing through embedded clock information. This approach can reduce PCB routing width, connector pin count, cable size, and system cost compared with routing 24 individual data lines between a graphics source and its destination. The DS90UR241's principal operating parameters are a 5 MHz to 43 MHz pixel-clock range, 24 parallel input bits, one LVDS output, and a maximum data rate of 1.03 Gbps. DC-balanced signaling reduces the cumulative DC offset associated with unbalanced data transfer and supports reliable point-to-point communication. The embedded clock allows the receiving device to recover timing from the serial stream without a separate source-synchronous clock. The chipset architecture supports transparent transfer of pixel data and control information. Typical signal combinations include 18-bit RGB data with horizontal sync, vertical sync, data enable, and three additional general-purpose channels. The serializer therefore supports display-oriented transfers that combine video, synchronization, and control information into one serial link while maintaining a defined relationship between the parallel source and serialized output. Typical uses include graphics controllers driving flat-panel displays, industrial human-machine interfaces, medical imaging consoles, automotive display systems, point-of-sale terminals, and compact control panels. In each case, the link must satisfy both the source timing requirements and the receiver's supported input and data-rate limits. The 43 MHz upper pixel-clock boundary is particularly important when selecting display modes, cable length, connector geometry, and receiver capabilities. Layout is critical because the serializer contains high-speed differential outputs that require controlled impedance, short routing, and a continuous return path. Follow the manufacturer pin-description table and recommended layout guidance, place decoupling and interface-support components close to their associated pins, and verify eye quality at the intended pixel-clock rate. The LVDS cable or PCB channel should also be characterized when loss, skew, reflections, or EMI margin are significant. This page combines the exact operating facts, package information, application guidance, comparison criteria, and practical interface-design considerations engineers need when qualifying the DS90UR241IVS for a new graphics link.
E-L9637D013TR - ISO 9141 K-Line Bus Driver/Transceiver | STMicroelectronics
The STMicroelectronics E-L9637D013TR is a monolithic ISO 9141 K-Line bus driver and transceiver designed for automotive on-board diagnostics (OBD-II) and bidirectional serial communication, packaged in an 8-pin SOIC (SO-8, 0.154 inch/3.90 mm width) and shipped in Tape & Reel (TR). It operates from a wide 4.5 V to 36 V supply, tolerates 40 V transients, and survives reverse-battery connection down to VS = -24 V while drawing approximately 2.3 mA supply current. What is a K-Line / ISO 9141 transceiver? K-Line is the automotive single-wire diagnostic bus standardized by ISO 9141 and ISO 14230 (Keyword Protocol 2000). It typically operates at ~10.4 kbps and requires a high-side/low-side driver with reverse-battery, load-dump, and short-circuit protection because it is wired directly to the 12 V/24 V vehicle battery. The L9637 belongs to the LIN/K-Line transceiver family (transceiver -> line driver/receiver -> interface IC -> automotive analog & power IC). Key features include K output current limitation of typ. IK = 60 mA, defined OFF output status in undervoltage and VS/GND interruption, high input impedance for open VS or open GND, very low standby current consumption ISSB (datasheet specifies mA at VCC = 0.5 V), and integrated reverse-battery/overvoltage safeguards. The 1A.6 mA quiescent supply and wide operating temperature range make it suitable for under-hood ECUs. Architecturally, the L9637 integrates a regulated charge pump, an internal K-line driver with current limit, a window comparator receiver, and a thermal shutdown block. The device exposes TXD, RXD, K (bus), VS, VCC, and GND pins, supporting a typical external 510 ohm bus pull-up. Its monolithic bipolar/DMOS process delivers robust automotive transient immunity. Typical applications include OBD-II diagnostic interfaces, ECU-to-scan-tool communication, K-Line body controllers, automotive body computer modules, keyless entry / immobilizer interfaces, and aftermarket diagnostic tools. Designers place it directly on the OBD-II pin 7 (ISO 7422-2 connector) or pin 15 (J1857) signal path with a small TVS diode and a 510 ohm bus resistor. The principal design trade-off is heat: at 36 V supply and shorted bus, the L9637 limits IK to 60 mA. Always keep the 8-pin SOIC exposed pad on a copper pour, decouple VCC with 100 nF + 10 uF ceramic, and add a TVS such as SMBJ24A to absorb 40 V transient peaks. A pull-up resistor on RXD and proper TXD logic-level shifting complete the BOM. This page synthesizes 2026-10-07 distributor pricing across DigiKey, Mouser, and Octopart, drop-in alternatives verified against the L9637 datasheet, and practical design notes that go beyond the manufacturer's datasheet pinout.