積體電路

子分類

📁 ADC/DAC 2,700+ 產品 📁 放大器 IC 1,100+ 產品 📁 音訊編解碼器 18 產品 📁 音訊 IC 2 產品 📁 時脈與計時 470+ 產品 📁 DSP 1,000+ 產品 📁 資料擷取 IC 2 產品 📁 數位電位器 4 產品 📁 顯示驅動器與控制器 1 產品 📁 FPGA 與 CPLD 6,800+ 產品 📁 介面 IC 2,200+ 產品 📁 LED 驅動器 1 產品 📁 邏輯 IC 360+ 產品 📁 記憶體 IC 870+ 產品 📁 微控制器 19,000+ 產品 📁 微處理器 4 產品 📁 馬達驅動器 1 產品 📁 其他 1 產品 📁 感測器與偵測器介面 1 產品 📁 特殊用途 IC 15 產品 📁 視訊 IC 13 產品

產品（35,000+)

iCE40UP5K-SG48 - 5280 LUT UltraPlus FPGA QFN-48 | Lattice
iCE40UP5K-SG48

iCE40UP5K-SG48 - 5280 LUT UltraPlus FPGA QFN-48 | Lattice

The Lattice Semiconductor iCE40UP5K-SG48 is an iCE40 UltraPlus low-power FPGA with 5280 Look-Up Tables (LUTs), 128 Kbit of dual-port block RAM, 1 Mbit of single-port RAM, and eight 16x16 DSP MAC blocks, housed in a 48-pin VFQFN exposed-pad (SG48) package. A Field Programmable Gate Array (FPGA) is a reconfigurable logic device that implements digital circuits through programmable interconnect and logic blocks. Within the semiconductor hierarchy, FPGAs sit alongside microcontrollers and ASICs as programmable silicon; the iCE40 UltraPlus family occupies the ultra-low-power end of the FPGA spectrum, targeting mobile, IoT, and AI/ML edge applications where milliwatts matter. Key features include two hard-IP SPI and two hard-IP I2C controllers that offload protocol handling from soft logic, two internal oscillators (10 kHz and 48 MHz) that eliminate external clock sources in cost-sensitive designs, three 24 mA constant-current RGB outputs with hard RGB PWM IP for direct LED drive, and dedicated DSP blocks with 16x16 multiply and 32-bit accumulate for lightweight neural network inference. Architecturally, the iCE40UP5K combines a 4-input LUT plus carry chain plus flip-flop fabric with 120 Kbit of distributed sysMEM block RAM and 1 Mbit SPRAM, a phase-locked loop (PLL) for clock synthesis, and low-power 1.2V core operation consistent with the family's positioning as the lowest-power machine learning solution in its class. Typical applications include sensor aggregation and pre-processing for mobile platforms, always-on AI/ML inference at the edge, and system management or bridge logic where two SPI and two I2C hard IPs reduce firmware complexity. The SG48 QFN footprint also suits compact boards such as the iCEBreaker open-source FPGA platform. Design consideration: use the SG48 package with QSPI flash configuration and account for the exposed thermal pad in PCB layout for reliable ground return. This page synthesizes distributor listings, drop-in family alternatives, and practical design notes not consolidated in the manufacturer datasheet.

詢價 聯絡我們