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DP83865BVH - 8/8 Gigabit Ethernet PHY | Texas Instruments
DP83865BVH

DP83865BVH - 8/8 Gigabit Ethernet PHY | Texas Instruments

The Texas Instruments DP83865BVH is an 8/8 Gigabit Ethernet physical-layer transceiver with integrated support for 10BASE-T, 100BASE-TX, and 1000BASE-T operation, supplied in a surface-mount 128-pin PQFP package measuring 14 x 20 mm. Its verified operating supply information includes 1.8 V and 2.5/3.3 V rails, while its transceiver architecture connects an Ethernet MAC through a digital parallel interface to copper cabling. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, is the semiconductor layer that converts logical data transmitted by a network controller into electrical or optical signals suitable for a communications medium. Within the Ethernet hierarchy, a PHY sits below the MAC and above the physical medium. For copper Ethernet, the PHY handles encoding, signaling, clock recovery, link negotiation, and reception of data transmitted over twisted-pair cabling. The DP83865BVH is identified as an 8/8 transceiver, providing eight transmit and eight receive channels for parallel network-interface implementations. Verified source data identifies 10BASE-T and 100BASE-TX support and notes integrated PMD sublayers associated with 1000BASE-T operation. This makes the device relevant to multiport Ethernet switches, routers, network interface controllers, and industrial communication equipment requiring several copper ports. The 128-PQFP package is physically substantial compared with compact QFN Ethernet PHYs because it exposes a broad high-speed parallel interface, multiple PHY channels, supply rails, reference clocks, and copper-network connections. Its surface-mount construction supports automated assembly, but careful power-plane distribution, controlled clock routing, and high-speed signal-integrity management remain necessary in multi-channel Ethernet designs. Typical applications include 8-port Gigabit Ethernet switches, network interface cards, routers, industrial Ethernet equipment, and embedded communication systems. The 8/8 organization can reduce the number of discrete PHY devices required when several copper ports share one board, although system partitioning, thermal distribution, and magnetics selection must still be evaluated. For a new design, engineers should use the official Texas Instruments datasheet and pinout rather than assigning connections solely from generic Ethernet conventions. Verify every supply rail, transceiver channel, clock input, resistor network, magnetic-interface component, and exposed thermal or supply connection against that document before layout release. This page consolidates verified distributor specifications, package data, sourcing links, application context, and compatibility cautions. Its key information gain is the distinction between a true pin-to-pin replacement and a merely similar 8/8 Ethernet PHY, which prevents an electrically or mechanically invalid substitution.

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DP83865DVH - 1G Ethernet PHY, 128-PQFP | Texas Instruments
DP83865DVH

DP83865DVH - 1G Ethernet PHY, 128-PQFP | Texas Instruments

The Texas Instruments DP83865DVH is a single-port Gigabit Ethernet physical-layer transceiver supporting 10BASE-T, 100BASE-TX, and 1000BASE-T in a 128-PQFP package measuring 14 x 20 mm. It operates from a 1.71 V to 1.89 V core supply and supports data rates through 1 Gbit/s. The commercial-temperature device is specified for 0 C to +70 C and has eight media-interface transmit or receive channels. An Ethernet PHY is the physical-layer component that converts digital Ethernet data supplied by a MAC into electrical signaling for a copper network, and receives analog signals from the cable. Within the Ethernet hierarchy, the PHY connects the digital MAC interface and the 10/100/1000BASE-T medium. This distinction matters because protocol handling remains above the PHY while the DP83865DVH performs line signaling, clock and data recovery, and physical-layer encoding functions. Verified source data identifies a 1 Gbit/s data rate, eight transceiver channels, a 1.71 V to 1.89 V supply range, approximately 430 mA supply current, and a 128-pin PQFP package. The device integrates physical medium-dependent sublayers required for 10BASE-T, 100BASE-TX, and 1000BASE-T Ethernet. Exact media-interface modes, clock tolerances, transceiver electrical limits, and pin-level functions are not present in the supplied search extracts and therefore require confirmation from the manufacturer datasheet before layout release. Typical implementation is a copper Gigabit Ethernet port in industrial controllers, embedded computers, test equipment, network interface cards, and communications hardware. The 128-PQFP footprint favors multilayer PCB routing and external magnetics rather than compact modules, while the 1.89 V maximum stated core supply requires a regulator with suitable headroom and power integrity. A network magnetics or integrated coupling arrangement is also required at the cable side, subject to the complete reference design. Engineers should preserve the exact interface voltage, termination, crystal or clock source, reset, and power-tree requirements given in the full DP83865 datasheet. Because no verified pricing schedule was supplied, unit prices remain marked as data needed rather than being inferred from generic distributor listings. The search data also indicates that no pin-to-pin DP83865 replacement is offered by TI, so substitution requires interface and PCB validation rather than an assumed footprint match. This page consolidates the verified distributor specifications, procurement sources, replacement evidence, and engineering cautions. It distinguishes confirmed electrical facts from unavailable details and avoids treating functionally similar PHYs as verified drop-in devices. That distinction is critical because Ethernet PHYs may use the same 128-pin package while differing in interface modes, strap behavior, clocking, register maps, and analog performance.

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DP83867CRRGZR - 1GbE Robust Ethernet PHY | Texas Instruments
DP83867CRRGZR

DP83867CRRGZR - 1GbE Robust Ethernet PHY | Texas Instruments

Texas Instruments DP83867CRRGZR is a low-power, robust 10/100/1000BASE-T Ethernet physical-layer transceiver with RGMII and SGMII interfaces, supplied in a 48-pin VQFN package designated RGZ. It supports 10BASE-T, 100BASE-TX, and 1000BASE-T protocols and is designed for copper Ethernet links requiring integrated PHY functions in a compact surface-mount package. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, is the semiconductor interface between a digital network controller and twisted-pair cabling. The PHY converts digital data into electrical signaling, performs line coding and signal conditioning, and supports the physical protocols used by 10 Mb/s, 100 Mb/s, and 1 Gb/s Ethernet. The DP83867 family places this network-access function within the broader hierarchy of Ethernet controller, network interface controller, interface IC, and semiconductor. The DP83867CRRGZR provides a single 10/100/1000BASE-T Ethernet channel and supports both RGMII and SGMII host interfaces. According to the Texas Instruments product information, the device is a robust, low-power physical-layer transceiver with integrated PMD sublayers. The RGZ package contains 48 pins, and the commercial-temperature ordering option is specified for 0°C to 70°C. The RGMII interface provides a parallel digital connection for a compatible Ethernet controller, while SGMII provides a high-speed serial interface for systems that use serial Ethernet links. The integrated PMD sublayers support 10BASE-T, 100BASE-TX, and 1000BASE-T operation. This coverage lets one physical design accommodate 10 Mb/s and 100 Mb/s legacy links as well as 1 Gb/s links, subject to the capabilities of the connected switch, router, network interface controller, and cabling infrastructure. The manufacturer also identifies cable diagnostics, IEEE 1588 support, and a JTAG 1149.1 debug interface as features of the DP83867 family comparison information. Typical applications include industrial Ethernet equipment, industrial automation controllers, network switches, routers, test equipment, servers, and embedded platforms that connect a digital Ethernet controller to a single copper port. In these systems, the PHY is normally paired with a host controller that handles higher-layer traffic and configuration, while the DP83867CRRGZR manages the physical medium. RGMII is useful when the host controller exposes a parallel interface; SGMII is useful when the system architecture favors a serial link between MAC and PHY. Layout and power design remain central to reliable operation. Place the PHY, magnetic-interface components, crystal or clock source, and decoupling capacitors according to the manufacturer reference layout, and preserve the high-speed differential return paths. Account for the exposed thermal pad when evaluating temperature rise. Review interface timing, magnetics selection, and supported Ethernet standards against the manufacturer datasheet before releasing a production layout. This product page combines the exact ordering information, supported Ethernet rates, interface choices, package details, and temperature grade with practical replacement guidance. It also provides application-specific design context, comparison criteria, and an engineering checklist for evaluating the DP83867CRRGZR without changing the core Ethernet architecture.

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DP83867CRRGZT - Gigabit Ethernet PHY | Texas Instruments
DP83867CRRGZT

DP83867CRRGZT - Gigabit Ethernet PHY | Texas Instruments

Texas Instruments DP83867CRRGZT is a low-power, robust 10/100/1000 Base-TX Ethernet physical-layer transceiver with RGMII and SGMII interfaces, supplied in a 48-pin VQFN (RGZ) package. It supports 10BASE-T, 100BASE-TX, and 1000BASE-T operation and is designed to connect a digital Ethernet controller or processor to twisted-pair cabling. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, converts logical data transmitted by a media-access controller into electrical signals suitable for copper cabling. The PHY belongs to the network-interface hierarchy: Ethernet controller > Ethernet PHY > 10/100/1000 Base-T interface > physical-layer transceiver. Integrating the physical medium, physical coding, and physical data sublayers allows the host controller to communicate through standardized Ethernet protocols. The DP83867CRRGZT combines robust Gigabit Ethernet operation with low power consumption and a compact 48-VQFN package. Its RGMII and SGMII interfaces provide flexible connections to controllers with different internal architectures. The device also supports cable diagnostics, IEEE 1588 start-of-frame support, and JTAG 1149.1, according to the available manufacturer and comparison data. A 7 mm by 7 mm package supports compact industrial and network equipment designs. The CRRGZT ordering option is associated by the verified product information with a 48-pin VQFN (RGZ) package and an operating-temperature range of 0 °C to 70 °C. Its three principal operating supply voltages are 1.8 V, 2.5 V, and 3.3 V. Detailed electrical limits, clock requirements, register defaults, magnetic-component recommendations, and timing margins must be taken from the manufacturer datasheet before layout release. Typical applications include industrial Ethernet controllers, automated machinery, network switches, embedded Linux systems, test equipment, and industrial IoT gateways. The device is particularly relevant when a board needs 10/100/1000-Mbps copper Ethernet and the host controller supports RGMII or SGMII. For an RMII-only controller, the verified comparison information states that a bridging translator such as the Microchip LAN9354 is required. A critical design consideration is interface timing: RGMII clock and data paths must meet the required setup and hold windows, while the copper-channel magnetics, center taps, and termination network must follow the reference design. PCB layout should separate high-speed digital clocks from analog receive circuitry and provide a low-impedance, continuous return path beneath the PHY and magnetics. This page consolidates verified manufacturer and distributor information, supported PHY variants, interface-selection guidance, and practical integration considerations. It distinguishes documented facts from electrical details that still require confirmation from the current Texas Instruments datasheet, helping engineers evaluate the DP83867CRRGZT without relying on an unverified cross-reference listing.

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DP83867CSRGZR - Gigabit Ethernet PHY RGMII/SGMII | Texas Instruments
DP83867CSRGZR

DP83867CSRGZR - Gigabit Ethernet PHY RGMII/SGMII | Texas Instruments

Texas Instruments DP83867CSRGZR is a robust, low-power, fully featured Gigabit Ethernet Physical Layer transceiver (PHY) supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols with RGMII and SGMII MAC interface options, packaged in a 48-pin VQFN (RGZ) 7x7 mm footprint. The device integrates the PMD sublayer and exceeds 8 kV IEC 61000-4-2 ESD (direct contact) immunity, targeting factory automation, motor drives, and other electrically harsh industrial environments. SGMII support enables seamless connection to MACs that lack parallel MII/GMII/RGMII pins, simplifying board routing on space-constrained designs. An Ethernet PHY (Physical Layer transceiver) is the analog front-end of an Ethernet link: it sits between the RJ45/magnetics on the line side and the MAC controller on the host side, performing PCS/PMA encoding, clock/data recovery, echo/ crosstalk cancellation, and link training. As a sub-class of network interface IC, the PHY falls under the broader hierarchy of networking ICs > interface ICs > integrated circuits. The DP83867CS series specifically targets the industrial Gigabit PHY niche where high ESD immunity, wide temperature support, and small form factor matter. Key features include configurable I/O voltage (3.3 V, 2.5 V, 1.8 V) for direct connection to FPGAs, SoCs, and ASICs of any logic family; ultra-low RGMII latency (TX < 90 ns, RX < 290 ns) which is essential for Time Sensitive Network (TSN) compliant systems; integrated cable diagnostics; and JTAG boundary scan support. The device ships in a 48-pin VQFN (RGZ) package with exposed thermal pad, and supports an extended industrial operating temperature range. The CS variant offers a low-power 457 mW typical operating power profile. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), human-machine interfaces (HMIs), motor and motion control, factory automation backbones, and embedded networking on single-board computers. The wide operating temperature range and ESD robustness also make it well suited to outdoor PoE end-points and ruggedized IoT gateways where commercial-grade PHYs would be unreliable. Designers should refer to the manufacturer datasheet for the recommended magnetics, RJ45 integration, and reference clock selection, and should follow the IBIS model for SI-validated board layout.

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DP83867CSRGZT - Robust GbE PHY, RGMII/SGMII, VQFN-48 | TI
DP83867CSRGZT

DP83867CSRGZT - Robust GbE PHY, RGMII/SGMII, VQFN-48 | TI

The Texas Instruments DP83867CSRGZT is a low-power, robust, fully-featured Gigabit Ethernet Physical Layer transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols, offered in a 48-pin VQFN (RGZ) 7x7 mm package. Key headlines: 10/100/1000 Mbps operation, RGMII and SGMII MAC interface options, configurable I/O voltage (3.3 V, 2.5 V, 1.8 V), and an industrial-grade 0 C to 70 C operating range with TI's high-immunity PHY core. An Ethernet PHY (Physical Layer transceiver) is the analog/digital mixed-signal device sitting between a Media Access Controller (MAC) and the magnetics/RJ45 connector on a copper Ethernet link. The PHY handles line encoding/decoding (PAM-5 for 1000BASE-T, MLT-3 for 100BASE-TX), link training, echo cancellation, and cross-talk mitigation across four twisted pairs, while presenting a parallel or serial digital interface to the MAC. As a Physical Layer transceiver within the seven-layer OSI model, the PHY is part of the wired networking interface layer, and a critical power-management and signal-integrity IC in any embedded Ethernet design. Key features include cable diagnostics, low RGMII latency (TX < 90 ns, RX < 290 ns), Time-Sensitive Network (TSN) compliance, fast link drop mode, JTAG 1149.1 boundary scan support, and integrated PMD sublayers. The DP83867CS provides high ESD/EMC immunity and an ultra-low RGMII latency profile. Compared to integration assemblers using lower-immunity PHYs, the CS variant offers enhanced robustness for noisy industrial environments. Architecturally, the device uses TI's proprietary DSP-based echo canceller and baseline wander corrector across all four pairs, with auto-negotiation and Auto-MDIX, allowing direct connection to either a straight-through or crossover cable. The SGMII option reduces MAC-to-PHY pin count to four differential signals, freeing board area in space-constrained designs. Typical applications include industrial Ethernet switches, factory automation controllers, motor drives with EtherCAT/PROFINET support, building automation, and any embedded system requiring a small-footprint, low-power gigabit copper interface. The wide temperature range and immunity rating make the part especially suitable for industrial Ethernet switches and PLCs. When designing with this device, pay careful attention to MDI trace routing (100-ohm differential, length-matched within the pair), magnetics selection, and decoupling on each supply pin. Reference the TI DP83867 design checklist for layout guidance, especially the four-pair MDI routing and chassis-ground separation.

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DP83867E - Gigabit Ethernet PHY, RGMII/SGMII, 48-VQFN | TI
DP83867E

DP83867E - Gigabit Ethernet PHY, RGMII/SGMII, 48-VQFN | TI

The Texas Instruments DP83867E is a robust, low-power, fully-featured 10/100/1000 Mbps Ethernet Physical Layer transceiver with integrated PMD sublayers, supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols, housed in a 48-pin VQFN (7x7 mm) package. The device delivers extra-low latency (TX < 90 ns, RX < 290 ns) and is offered in an industrial extended-temperature grade with SGMII and RGMII MAC interfaces. An Ethernet PHY (Physical Layer transceiver) is a mixed-signal IC that connects a MAC controller to the copper medium (twisted-pair cable), handling line encoding/decoding, link training, echo/next-crosstalk cancellation, and clock/data recovery across the MDI. The DP83867E sits at the bottom of the OSI physical layer, translating digital MAC frames into analog baseband signals on the cable. In the taxonomy: Ethernet PHY -> transceiver -> network interface IC -> communication semiconductor. The part exceeds 8 kV IEC 61000-4-2 ESD on the cable pins, making it a robust choice for industrial and automotive-grade Ethernet links. Key features include support for both RGMII and SGMII MAC interfaces, integrated 1.25 GHz SerDes for SGMII, low-power 1000BASE-T operation, programmable LED outputs, and a flexible MDIO/MDC management interface. The extended-temperature grade (-40C to +105C ambient with proper thermal design) targets industrial control, factory automation, and outdoor equipment where commercial-grade PHYs derate. Architecturally, the DP83867E uses a DSP-based echo and crosstalk canceller, an integrated 1000BASE-T PMA/PMD with on-chip termination, and a low-jitter PLL to recover the 125 MHz reference. The SGMII variant routes the recovered data over a 1.25 Gbps differential serial link, eliminating the 12-bit parallel RGMII bus and reducing board-layer routing complexity in space-constrained SoMs. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), factory-floor IO modules, motor drives, telecom base-station routers, and automotive Ethernet PHYs for in-vehicle networking. The SGMII interface in particular suits SoCs that place the PHY on a remote daughter card or that prefer serial MAC connectivity. Design consideration: the MDI traces require 100-ohm controlled differential impedance and an integrated magnetics RJ-45 with center-tap; the 1.0 V analog and 2.5/3.3 V digital rails must be cleanly decoupled to meet the IEEE 802.3 return-loss mask. Use the TI reference design checklist for BOM and stack-up. This page synthesizes distributor pricing, package-accurate cross-references, and practical PCB design notes that go beyond the manufacturer datasheet to accelerate your Ethernet hardware bring-up.

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DP83867ERGZR - 1GbE SGMII PHY | Texas Instruments
DP83867ERGZR

DP83867ERGZR - 1GbE SGMII PHY | Texas Instruments

The Texas Instruments DP83867ERGZR is a single-port 10/100/1000BASE-T Ethernet physical-layer transceiver with RGMII and SGMII interfaces, supplied in a 48-pin VQFN RGZ package measuring 7 mm by 7 mm. It supports 1.0 V, 1.8 V, and 2.5 V supply options according to the verified distributor and comparison data. The extended-temperature ordering option operates from -40 °C to 105 °C, making the device suitable for industrial embedded networking and communications equipment that requires extended environmental coverage. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, is the circuit that converts digital Ethernet data between a MAC or communications processor and a physical copper network. The DP83867E belongs to the Gigabit Ethernet PHY hierarchy: Ethernet transceiver > physical-layer transceiver > PHY > semiconductor. Its 10BASE-T, 100BASE-TX, and 1000BASE-T support allows one physical network interface to accommodate 10 Mb/s, 100 Mb/s, and 1 Gb/s Ethernet operation, depending on the link negotiation and connected equipment. The verified ordering information identifies a 48-VQFN RGZ package, a 7 mm square land pattern, a 0.5 mm lead pitch, and a tape-and-reel shipping format. RGMII provides a parallel digital interface for a conventional MAC-to-PHY connection, while SGMII provides a high-speed serial interface for designs that benefit from fewer signal connections. The available comparison data also identifies cable-diagnostics, IEEE 1588 support of the stated SOF type, and JTAG 1149.1 among the notable device features. Because the DP83867ERGZR is specified as an extended-temperature, robust, low-latency Gigabit Ethernet PHY, it is relevant to industrial automation, motor-drive systems, embedded routers, test equipment, and communications infrastructure. These systems benefit from a compact 48-pin surface-mount package and flexible RGMII or SGMII host connectivity. The exact supported link rates, electrical characteristics, clocking requirements, media-access procedures, and recommended external circuitry must be confirmed against the manufacturer datasheet before a board design is released. A critical implementation consideration is that the PHY is part of a high-speed mixed-signal system. Designers should follow the manufacturer’s reference layout, provide the specified power and decoupling networks, and route high-speed differential pairs as controlled-impedance transmission lines. Magnetics, RJ45 circuitry, clock sources, reset timing, and the exact operating mode also require validation in the complete system rather than substitution based only on package similarity. This page consolidates the verified manufacturer and distributor information for DP83867ERGZR, adds application and design context, distinguishes documented facts from missing technical data, and evaluates only same-package drop-in candidates that can be traced to the supplied web results. It is intended to accelerate component screening while preserving the need for datasheet-level engineering verification before procurement or PCB release.

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DP83867ERGZT - 1GbE SGMII PHY | Texas Instruments
DP83867ERGZT

DP83867ERGZT - 1GbE SGMII PHY | Texas Instruments

The Texas Instruments DP83867ERGZT is a single-port 10/100/1000BASE-T Ethernet physical-layer transceiver with RGMII and SGMII host interfaces, extended-temperature capability, and a 48-VQFN 7 x 7 mm package. It supports 10BASE-T, 100BASE-TX, and 1000BASE-T protocols, integrates the required physical medium device sublayers, and connects directly to a transformer-based twisted-pair network interface. The device is specified for robust operation with ESD protection exceeding 8 kV under IEC 61000-4-2 direct-contact conditions. An Ethernet physical-layer transceiver, or Ethernet PHY, is the component that translates between a digital MAC-side interface and analog electrical signaling on a copper Ethernet cable. The DP83867 belongs to the interface-IC hierarchy and supports the physical layer for 10 Mb/s, 100 Mb/s, and 1 Gb/s Ethernet networks. Its RGMII and SGMII interfaces allow it to connect with a host processor, FPGA, network controller, or Ethernet switch subsystem while retaining compatibility with common copper-Ethernet infrastructure. Key features include support for all three standard copper Ethernet rates, simultaneous RGMII and SGMII interface options, a small 48-VQFN package, and a low-latency design intended for demanding communication equipment. The manufacturer describes the DP83867E as a robust, low-power, fully featured physical-layer transceiver. Its extended-temperature ordering option makes it suitable for industrial equipment and other installations where operating-temperature limits, reliability, and ESD immunity are important design considerations. The device integrates the PMD and PCS functions needed to interface with standard 10BASE-T, 100BASE-TX, and 1000BASE-T networks. Unlike a software-only MAC, the PHY performs the physical encoding, signaling, and recovery associated with copper Ethernet. The SGMII option is particularly useful when the PHY must connect across a serial high-speed digital interface, while RGMII provides a wider parallel interface for designs using a local processor or FPGA. Typical uses include industrial Ethernet switches, programmable logic controller gateways, factory automation controllers, network-attended test equipment, embedded systems, and rugged communications infrastructure. It is also appropriate for designs requiring a compact, single-port Gigabit Ethernet interface without the footprint of a larger multi-port transceiver. Designers should carefully follow the manufacturer reference layout for the exposed-pad package, provide the specified power and decoupling networks, and use a qualified Ethernet transformer with the required center-tap and termination arrangement. RGMII timing is especially sensitive to trace length and clock skew, while SGMII requires controlled impedance and low-jitter routing. Magnetics selection, isolation boundaries, grounding, and surge protection must be reviewed against the target installation environment. This product page consolidates manufacturer-supported functionality, verified distributor pricing, interface-focused comparisons, and practical Ethernet design guidance. It also distinguishes verified drop-in alternatives from pin-compatible parts that differ in package, temperature grade, register map, or interface support.

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DP83867IRPAPR - Industrial Gigabit Ethernet PHY | Texas Instruments
DP83867IRPAPR

DP83867IRPAPR - Industrial Gigabit Ethernet PHY | Texas Instruments

The Texas Instruments DP83867IRPAPR is an industrial-temperature 10/100/1000 Base-T Ethernet physical-layer transceiver with RGMII and SGMII interfaces, packaged in a 64-pin HTQFP (PAP) package measuring 10 mm by 10 mm. It is designed for robust Gigabit Ethernet equipment operating from -40 °C to 85 °C. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, converts between a digital MAC-side interface and analog signals carried over twisted-pair cabling. The DP83867IR belongs to the physical-layer layer of the Ethernet hierarchy, supporting 10BASE-T, 100BASE-TX, and 1000BASE-T operation. Its RGMII and SGMII interfaces allow connection to a network controller or other suitable Ethernet digital interface. The DP83867IR is positioned for industrial systems that require a single-port Gigabit Ethernet physical layer with high-immunity operation. The verified product information identifies cable diagnostics, IEEE 1588 support, and JTAG 1149.1 among the device features. Its -40 °C to 85 °C industrial-temperature range supports deployment in factory automation, industrial controls, communications equipment, and embedded systems operating across extended temperature environments. The 64-pin HTQFP (PAP) construction provides a conventional surface-mount footprint for industrial Ethernet designs. The RGMII interface supports conventional parallel Ethernet connectivity, while SGMII offers a serial alternative for designs using a compatible controller or PHY arrangement. Interface selection should be made during schematic definition because signal timing, clocking, voltage domains, and controller support determine which implementation is appropriate. Typical uses include industrial Ethernet switches, programmable automation controllers, factory-floor gateways, motor-control platforms, building-control equipment, and embedded communications modules. The -40 °C to 85 °C range is particularly relevant to equipment installed near machinery, outdoor enclosures, or other locations with wide ambient-temperature variation. Design planning must include the complete DP83867IR datasheet pin list, power requirements, clocking scheme, magnetic-interface configuration, and initialization sequence. Validate the selected board layout, magnetics, cable reach, EMC behavior, and link negotiation in the final industrial enclosure rather than relying only on generic Ethernet design assumptions. This product page consolidates the verified device classification, package information, temperature range, interface details, sourcing data, and practical engineering considerations into one design reference. It also distinguishes a true same-footprint substitute from related parts and evaluation modules that cannot automatically replace the DP83867IRPAPR.

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DP83867IRPAPT - Industrial GbE PHY, RGMII/GMII, 64-HTQFP | TI
DP83867IRPAPT

DP83867IRPAPT - Industrial GbE PHY, RGMII/GMII, 64-HTQFP | TI

The Texas Instruments DP83867IRPAPT is a robust, low-power, fully-featured gigabit Ethernet Physical Layer (PHY) transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T protocols, housed in a 64-pin HTQFP (PAP) 10x10 mm package. It delivers GMII, MII, and RGMII MAC interface support, an industrial temperature range of -40C to +85C, and ESD protection exceeding 8 kV IEC 61000-4-2 (direct contact). Full operating power is approximately 490 mW (PAP variant) and it includes cable diagnostics, IEEE 1588 Start of Frame Detection, and JTAG 1149.1 boundary scan. An Ethernet PHY (physical layer transceiver) is the lowest layer of the OSI model that converts digital MAC data into analog signaling for transmission over copper twisted-pair cable and recovers the analog signal at the receiving end. PHYs handle line coding (PAM-3 for 10BASE-Te, MLT-3 for 100BASE-TX, PAM-5 for 1000BASE-T), echo/next cancellation, equalization, and clock/data recovery. In the broader taxonomy, an Ethernet PHY is a type of network interface IC -> wired communication IC -> interface IC -> semiconductor. PHY choice (industrial temp, low latency, IEEE 1588 SOF) drives MAC selection, magnetics, and PCB stack-up decisions. The DP83867IRPAPT combines an integrated PHY with hardware timestamping (IEEE 1588 SOF), enabling sub-microsecond synchronization accuracy required by industrial Ethernet protocols such as EtherCAT, PROFINET, and TSN. The device supports both RGMII and GMII for flexible MAC attachment, including low-power mode down to approximately 230 mW (estimated from PAP data) when link is established. Cable diagnostics (TDR-based) detect open/short distance and polarity on each twisted pair, simplifying field installation. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), industrial sensors and drives, factory automation gateways, and any embedded system requiring reliable GbE connectivity in harsh EMI/noisy environments. The industrial temperature rating and high ESD immunity make it well suited to factory floor equipment, motor drives, and outdoor installations where commercial-grade PHYs would fail. When designing in this part, allocate sufficient PCB area for the 64-HTQFP thermal pad and follow TI's reference layout for the magnetic interface. Use a 25 MHz reference clock or rely on the integrated 25 MHz crystal oscillator, and add proper decoupling (0.1 uF + 10 uF) near each supply pin to meet EMI/ESD margins. This page synthesizes distributor pricing, drop-in alternatives (same-brand first, then cross-brand), and practical PCB/thermal design notes not collected in any single distributor listing or in the manufacturer datasheet alone.

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DP83867IRRGZ - Industrial GbE PHY, RGMII/SGMII, VQFN-48 | Texas Instruments
DP83867IRRGZ

DP83867IRRGZ - Industrial GbE PHY, RGMII/SGMII, VQFN-48 | Texas Instruments

The Texas Instruments DP83867IRRGZ is a robust, low-power, fully featured Gigabit Ethernet physical layer (PHY) transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T over twisted-pair copper, housed in a 48-pin VQFN (RGZ) 7x7 mm package with exposed thermal pad. It features MAC interfaces of RGMII and SGMII, an industrial temperature range of -40C to +85C, and ESD protection that exceeds 8 kV IEC 61000-4-2 on the cable-side pins. The device targets harsh industrial Ethernet applications where EMI immunity, extended temperature, and long cable reach are required. An Ethernet PHY (Physical Layer transceiver) sits at layer 1 of the OSI model and converts digital MAC-side data into the analog differential signaling required by 10/100/1000BASE-T, while handling line coding, link training, echo/ crosstalk cancellation, and clock/data recovery. PHYs connect directly to an Ethernet MAC inside a switch controller, FPGA, SoC, or MCU, making them the physical bridge between the digital host and the RJ45/Magnetics front end. The DP83867 family belongs to the industrial-grade GbE PHY category, sitting above commercial-temperature PHY ICs and below automotive-qualified variants such as the DP83867IRRGZ-Q1. Key features include sub-1.5 W typical power consumption at gigabit speeds, integrated termination resistors, programmable LED drivers, IEEE 1588/SOF timestamping support, cable diagnostics (TDR), and a 25 MHz reference clock input. The RGMII/SGMII MAC interface gives the designer flexibility to bridge to either an FPGA/SoC with parallel RGMII pins or a serdes-based MAC with differential SGMII signaling. The wide 1.1 V / 2.5 V / 3.3 V supply rails simplify integration with mixed-voltage hosts, while the 8 kV ESD rating eliminates the need for external TVS arrays on the MDI pins in many designs. The internal architecture combines a DSP-based echo canceller and crosstalk canceller with an analog front-end optimized for 1000BASE-T PAM-5 signaling over 100 m of Cat5e/Cat6 cable. Auto-negotiation and Auto-MDIX streamline bring-up, while Energy-Efficient Ethernet (EEE) reduces idle power. Hardware diagnostics including cable length estimation and open/short detection assist field commissioning and predictive maintenance. Typical applications include industrial Ethernet switches, PLC communication modules, motor-control and servo-drive feedback links, factory-floor sensor backbones, ruggedized PoE PD/PoE+ powered devices, and embedded gateways that need deterministic GbE connectivity. The industrial temperature rating makes the part a standard choice for IEC 61131-2 / IEC 61850 environments. When designing with this PHY, place the 25 MHz crystal/oscillator within 50 mm of the XI/XO pins and keep the MDI differential pairs length-matched within 2 mm and referenced to a continuous ground plane. Add a 1 nF HV decoupling cap on each MDI center-tap and follow the reference schematic in the DP83867 datasheet for the RJ45 magnetics to pass IEEE conformance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, accelerating PHY selection and PCB bring-up.

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DP83867IRRGZR - Industrial GbE PHY, RGMII/SGMII, VQFN-48 | Texas Instruments (Tape & Reel)
DP83867IRRGZR

DP83867IRRGZR - Industrial GbE PHY, RGMII/SGMII, VQFN-48 | Texas Instruments (Tape & Reel)

The Texas Instruments DP83867IRRGZR is a robust, low-power, fully featured Gigabit Ethernet physical layer (PHY) transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T over twisted-pair copper, housed in a 48-pin VQFN (RGZ) 7x7 mm package with exposed thermal pad. It features MAC interfaces of RGMII and SGMII, an industrial temperature range of -40C to +85C, and ESD protection that exceeds 8 kV IEC 61000-4-2 on the cable-side pins. The device targets harsh industrial Ethernet applications where EMI immunity, extended temperature, and long cable reach are required. An Ethernet PHY (Physical Layer transceiver) sits at layer 1 of the OSI model and converts digital MAC-side data into the analog differential signaling required by 10/100/1000BASE-T, while handling line coding, link training, echo/ crosstalk cancellation, and clock/data recovery. PHYs connect directly to an Ethernet MAC inside a switch controller, FPGA, SoC, or MCU, making them the physical bridge between the digital host and the RJ45/Magnetics front end. The DP83867 family belongs to the industrial-grade GbE PHY category, sitting above commercial-temperature PHY ICs and below automotive-qualified variants such as the DP83867IRRGZR-Q1. Key features include sub-1.5 W typical power consumption at gigabit speeds, integrated termination resistors, programmable LED drivers, IEEE 1588/SOF timestamping support, cable diagnostics (TDR), and a 25 MHz reference clock input. The RGMII/SGMII MAC interface gives the designer flexibility to bridge to either an FPGA/SoC with parallel RGMII pins or a serdes-based MAC with differential SGMII signaling. The wide 1.1 V / 2.5 V / 3.3 V supply rails simplify integration with mixed-voltage hosts, while the 8 kV ESD rating eliminates the need for external TVS arrays on the MDI pins in many designs. The internal architecture combines a DSP-based echo canceller and crosstalk canceller with an analog front-end optimized for 1000BASE-T PAM-5 signaling over 100 m of Cat5e/Cat6 cable. Auto-negotiation and Auto-MDIX streamline bring-up, while Energy-Efficient Ethernet (EEE) reduces idle power. Hardware diagnostics including cable length estimation and open/short detection assist field commissioning and predictive maintenance. Typical applications include industrial Ethernet switches, PLC communication modules, motor-control and servo-drive feedback links, factory-floor sensor backbones, ruggedized PoE PD/PoE+ powered devices, and embedded gateways that need deterministic GbE connectivity. The industrial temperature rating makes the part a standard choice for IEC 61131-2 / IEC 61850 environments. When designing with this PHY, place the 25 MHz crystal/oscillator within 50 mm of the XI/XO pins and keep the MDI differential pairs length-matched within 2 mm and referenced to a continuous ground plane. Add a 1 nF HV decoupling cap on each MDI center-tap and follow the reference schematic in the DP83867 datasheet for the RJ45 magnetics to pass IEEE conformance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, accelerating PHY selection and PCB bring-up.

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DP83867IRRGZT - Robust Gigabit Ethernet PHY | Texas Instruments
DP83867IRRGZT

DP83867IRRGZT - Robust Gigabit Ethernet PHY | Texas Instruments

Texas Instruments DP83867IRRGZT is a robust gigabit Ethernet physical-layer transceiver supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T over twisted-pair copper cables. It is a single-port Ethernet PHY with RGMII, MII, GMII, and SGMII interface options, designed for industrial temperature operation from -40 °C to 85 °C. The device is supplied in a 48-pin VQFN RGZ package measuring 7 mm by 7 mm. A physical-layer transceiver is the active electronics that converts digital Ethernet data into voltage or current signals suitable for transmission over a copper cable, while recovering those signals at the receiving end. The DP83867 belongs to the Ethernet PHY, network-interface IC, communications-semiconductor, and power-management hierarchy. It is used beneath a network controller or processor with an appropriate MAC interface, providing the physical connection to an RJ45 magnetics module or other Ethernet network medium. The DP83867IR family is positioned for systems requiring high immunity and low-power Ethernet connectivity. The product information identifies a power consumption of 457 mW, integrated MDI termination resistors, programmable RGMII delay modes on both receive and transmit paths, and programmable MII, GMII, and RGMII termination impedance. These features support flexible timing alignment between the PHY and the connected Ethernet controller. The component also supports cable diagnostics and IEEE 1588 SOF features according to the manufacturer comparison information. These functions can assist commissioning and network timing applications. The RGMII interface is particularly useful for processors, FPGAs, and programmable logic devices that need a high-speed parallel Ethernet connection while keeping the external pin count and PCB area manageable. Typical installations include industrial Ethernet equipment, factory automation controllers, networked sensors, communications gateways, embedded computers, test equipment, and industrial data-acquisition systems. The industrial-temperature grade makes the device appropriate for equipment where ambient temperature and electrical robustness are important design constraints. A 48-pin VQFN also requires careful PCB layout, thermal management, and high-speed signal-integrity practices. For a new design, confirm the exact interface mode, strap configuration, clocking method, media configuration, magnetics selection, and firmware or register configuration against the manufacturer datasheet. When replacing an existing PHY, verify the complete pinout, strap behavior, clock source, termination settings, and supported interface mode rather than relying on the package name alone. The DP83867IRRGZT is the industrial-temperature RGZ-package ordering option identified by Texas Instruments.

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DP83867ISRGZR - Robust Industrial Gigabit Ethernet PHY | TI
DP83867ISRGZR

DP83867ISRGZR - Robust Industrial Gigabit Ethernet PHY | TI

Texas Instruments DP83867ISRGZR is an industrial-temperature, robust 10/100/1000 Ethernet physical-layer transceiver with integrated PMD sublayers, RGMII and SGMII interfaces, and a 48-VQFN 7 x 7 mm package. It combines support for 10BASE-T, 100BASE-TX, and 1000BASE-T Ethernet protocols with low-power operation and enhanced electrostatic-discharge protection. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, converts between a digital MAC interface and analog signaling over twisted-pair cabling. The DP83867 belongs to the PHY, Ethernet transceiver, network interface IC, and power management semiconductor hierarchy. Its RGMII interface supports integration with a digital Ethernet controller, while SGMII provides a serial option for higher-speed serial links. The DP83867IS supports all three standard Gigabit Ethernet copper rates: 10 Mb/s, 100 Mb/s, and 1000 Mb/s. The manufacturer identifies the IS grade as an industrial-temperature option intended for robust networking equipment. The device is supplied in a compact 48-pin VQFN package measuring 7 x 7 mm, reducing board area compared with larger Ethernet transceiver packages while exposing the high-speed digital, analog, clock, power, and ground connections required by the interface. Electrostatic-discharge robustness is a central feature of the device. According to the TI datasheet, the DP83867 exceeds 8 kV IEC 61000-4-2 direct-contact ESD protection. This makes the transceiver suitable for connectivity equipment installed near externally accessible cables, provided the board-level protection network, grounding, and layout guidance in the manufacturer datasheet are followed. The package also uses 1 V, 1.8 V, and 2.5 V digital I/O levels, allowing interface-voltage selection based on the connected Ethernet controller. Typical uses include industrial switches, routers, gateways, embedded network modules, test equipment, and communication equipment requiring a single copper-Ethernet port. RGMII is useful when the PHY is placed beside an Ethernet MAC in a high-performance system, while SGMII can simplify connections to serializers or controllers that support that interface. The same PHY can negotiate the link rate and support 10BASE-T, 100BASE-TX, or 1000BASE-T operation according to the connected network. A successful design must preserve high-speed signal integrity around the RGMII, SGMII, clock, and differential copper interfaces. Place decoupling capacitors close to the supply pins, use the recommended magnetics and impedance-controlled differential routing, and follow the exposed-pad thermal and assembly requirements. Do not substitute a non-drop-in transceiver solely because its headline data rate matches. This page organizes the manufacturer specifications, sourcing information, drop-in family options, application guidance, package constraints, and practical PCB considerations needed to evaluate DP83867ISRGZR before committing it to a design.

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DP83867ISRGZT Industrial Gigabit Ethernet PHY | Texas Instruments
DP83867ISRGZT

DP83867ISRGZT Industrial Gigabit Ethernet PHY | Texas Instruments

The Texas Instruments DP83867ISRGZT is an industrial-temperature, single-port 10/100/1000 Ethernet physical-layer transceiver with RGMII and SGMII interfaces, operating from -40°C to +85°C in a 48-pin RGZ VQFN package. It supports 10BASE-T, 100BASE-TX, and 1000BASE-T protocols and uses 1.0 V, 1.8 V, and 2.5 V interface rails. An Ethernet physical-layer transceiver, or Ethernet PHY, is the semiconductor layer that converts digital Ethernet data into signals suitable for transmission over twisted-pair cable. It sits between a network controller or system-on-chip and the external RJ45 magnetic interface. Within the network architecture, the DP83867IS belongs to the PHY, physical-layer transceiver, Ethernet interface IC, and semiconductor hierarchies. The DP83867IS is positioned for industrial systems that require robust Gigabit Ethernet connectivity. Its operating-temperature range of -40°C to +85°C exceeds the range of typical commercial-temperature PHYs. A single-port architecture simplifies board routing, while RGMII support allows direct connection to many Ethernet controllers and SGMII support supports serial links to higher-speed fabric or switching silicon. The device integrates the physical-medium dependent sublayers required for 10BASE-T, 100BASE-TX, and 1000BASE-T operation. Supporting all three rates in one PHY permits a single copper-network design to accommodate legacy 10 Mbit/s and 100 Mbit/s endpoints as well as full-duplex Gigabit links. The availability of 1.0 V, 1.8 V, and 2.5 V interface rails supports integration with processors, FPGAs, switching fabrics, and industrial controllers operating at different logic levels. Typical applications include industrial Ethernet controllers, factory automation equipment, networked sensors, motor-drive systems, building-automation gateways, and embedded routers. The combination of RGMII and SGMII makes the device suitable for designs that must accommodate parallel MAC connections, serial fabric links, or platform variants using different network architectures. PCB implementation requires careful treatment of the exposed pad, analog supply rails, clock sources, and high-speed digital interfaces. Place the PHY close to the network connector and magnetics, route differential pairs as impedance-controlled pairs, and use a solid ground-plane arrangement beneath the device. Follow the manufacturer datasheet for the exposed-pad connection, decoupling capacitors, isolation boundaries, and analog-layout requirements. This page organizes the DP83867ISRGZT’s industrial Ethernet role, interface options, temperature range, package constraints, application guidance, drop-in candidates, and engineering considerations into a practical selection reference for designers building robust copper-based Ethernet equipment.

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DP83869HMRGZR - High-Immunity Gigabit Ethernet PHY | TI
DP83869HMRGZR

DP83869HMRGZR - High-Immunity Gigabit Ethernet PHY | TI

The Texas Instruments DP83869HMRGZR is an extended-temperature, high-immunity gigabit Ethernet PHY transceiver with integrated PMD sublayers, supplied in a 48-pin VQFN (RGZ) 7x7 mm package. It supports 10BASE-Te, 100BASE-TX, and 1000BASE-T copper protocols along with 1000BASE-X and 100BASE-FX fiber interfaces, operating from a 1.8V/2.5V/3.3V supply rail. An Ethernet PHY (Physical Layer transceiver) is the interface IC that connects a MAC (Media Access Controller) to the physical copper or fiber cable, handling line coding, link training, echo/return-loss compensation, and clock/data serialization. As part of the Physical Layer transceiver -> Ethernet transceiver -> Network Interface IC -> Power Management/Connectivity IC hierarchy, gigabit PHYs sit one layer below the MAC and one layer above the magnetics/RJ-45 (or SFP fiber cage), translating MII/GMII/RGMII parallel data into differential serial signals compliant with IEEE 802.3 10/100/1000BASE-T. Key features of the DP83869HMRGZR include: IEEE 802.3 10/100/1000 Mbps operation, integrated PMD sublayers for copper and fiber, RGMII/MII/GMII MAC interfaces, media-conversion between copper and fiber ports, AEC-Q100-qualified extended-temperature grade (-40C to +125C), low-latency cut-through mode, and 8 kV IEC 61000-4-2 ESD protection (direct contact). The 48-pin VQFN (RGZ) package exposes a thermal pad for heat dissipation and supports reflow soldering on standard industrial PCB processes. Architecturally, the DP83869HMRGZR integrates the entire physical coding sublayer (PCS), physical medium attachment (PMA), and physical medium dependent (PMD) blocks on-chip, eliminating the need for external PHY magnetics tuning circuits. The device supports both SGMI and RGMII host interfaces with selectable timing modes, and includes integrated termination resistors that simplify the BOM. Cable diagnostics, loopback modes, and jumbo-frame support extend its utility in industrial Ethernet switches. Typical applications include industrial Ethernet switches, factory automation controllers, motor-drive communication boards, 5G small-cell fronthaul, automotive Ethernet gateways, and fiber-to-copper media converters. The wide temperature and high immunity make it well suited for IEC 61000-4 industrial EMC environments where standard PHYs would fail conformance. When designing with this part, ensure the MDI traces are 100-ohm differential with controlled 50-ohm single-ended impedance, place the 1.8V/2.5V/3.3V decoupling capacitors within 2 mm of each supply pin, and use a 4-layer PCB with a continuous ground plane below the PHY to meet IEEE 802.3 return-loss masks. This page synthesizes distributor pricing, drop-in TI same-family alternatives, design notes, and an honest comparison against cross-brand gigabit PHYs - content not aggregated on any single manufacturer or distributor page.

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DP83901AV - 5V Serial Network Controller | Texas Instruments
DP83901AV

DP83901AV - 5V Serial Network Controller | Texas Instruments

The Texas Instruments DP83901AV is a 5 V serial network interface controller, or SNIC, with 110 mA typical supply current in a 68-pin PLCC J-lead package measuring 25.13 mm by 25.13 mm. Designed for CSMA/CD local-area networks, the device supports Ethernet 10BASE5, Thin Ethernet 10BASE2, and twisted-pair Ethernet 10BASE-T implementations. A serial network interface controller is a semiconductor that coordinates data exchange between a host computer and an Ethernet physical layer. Within the network-interface hierarchy, it sits between host hardware or software drivers and a network-medium transceiver. The DP83901AV consolidates functions required to manage Ethernet packet transfer, addressing, access, and station communication while operating from a single 5 V supply. The verified source material identifies the DP83901AV as a microCMOS VLSI controller with a serial interface, 7 pF typical input capacitance, and 7 pF typical output capacitance under the stated test conditions. Its nominal 110 mA supply current makes board-level power planning important in systems that operate continuously. Commercial temperature grade and tray packaging are also identified in the verified component listings. Because the part targets legacy Ethernet standards, its strongest design roles are 10BASE5, 10BASE2, and 10BASE-T network-interface designs rather than modern switched Gigabit Ethernet equipment. A host processor must provide the required bus, interrupt, memory, and network-driver environment. Designers should also preserve the exact timing, signal-conditioning, and pin functions documented for this legacy controller. Typical implementation choices include industrial data acquisition, embedded test systems, service equipment, and legacy Ethernet adapters that require 10BASE-T connectivity. The controller can be paired with suitable transceivers, magnetics, isolation, clocks, and termination networks, but the external network interface must be selected independently because the verified data does not identify one specific companion-device BOM. The primary design consideration is availability and lifecycle validation. This is a mature Ethernet controller, so procurement should confirm current supply, manufacturer status, and traceability before a new design is released. Existing products should preserve the original schematic, timing, and firmware assumptions unless a replacement has been independently qualified. This page consolidates the verified package, supply, interface, and Ethernet data while separating unavailable specifications from established facts. It also records the lack of a verified drop-in replacement rather than presenting a functionally similar controller as a safe PCB substitute.

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DP83902AV/NOPB - 10BASE-T Ethernet Controller
DP83902AV/NOPB

DP83902AV/NOPB - 10BASE-T Ethernet Controller

Texas Instruments DP83902AV/NOPB is an IEEE 802.3 serial network interface controller for 10BASE-T twisted-pair Ethernet, with a 4.75 V to 5.25 V supply range, 140 mA supply current, and an 84-pin PLCC package measuring 29.31 mm by 29.31 mm. It integrates the network-controller and twisted-pair transceiver functions required by legacy 10 Mb/s Ethernet systems. An Ethernet controller is an interface IC that connects a host or embedded system to a physical-layer network. The DP83902AV/NOPB belongs to the ST-NIC family and is intended for IEEE 802.3 10BASE-T networking. Unlike a switching Ethernet transceiver designed for modern 100 Mb/s or multi-gigabit links, this device targets legacy 10BASE-T equipment where established system architecture and installed cabling remain important. The device operates from a conventional 5 V supply, accepting voltages from 4.75 V through 5.25 V. Its specified supply current is 140 mA. The package is an 84-pin J-lead PLCC with a 29.31 mm by 29.31 mm body, and the documented shipping format is a tube. The suffix NOPB identifies a lead-free ordering configuration associated with this manufacturer’s RoHS-compliant product documentation. DP83902AV/NOPB combines the logical Ethernet controller and 10BASE-T physical interface in one integrated circuit. This integration reduces the number of network-interface components required in a conventional 10BASE-T design. The serial interface is consistent with the ST-NIC architecture used in IEEE 802.3 systems, allowing the controller to serve as the principal interface between host-side logic and the twisted-pair physical layer. Typical uses include legacy network interface cards, embedded industrial Ethernet equipment, test systems, and industrial-control products whose original architecture was designed around the IEEE 802.3 10BASE-T standard. The device may also appear in equipment maintenance and obsolescence programs where preserving the original 84-pin PLCC footprint is preferable to redesigning the network interface. A replacement decision should prioritize the complete pinout, electrical characteristics, clocking arrangement, media-access behavior, and software-driver expectations. Do not assume that another Ethernet controller is interchangeable solely because it also supports 10BASE-T. A qualified replacement must preserve the 84-pin PLCC land pattern and the original system-level timing and register requirements. This product page combines the controller identity, operating limits, package information, verified drop-in information, comparison parameters, and engineering selection guidance. That practical context helps engineers distinguish a genuine footprint-compatible replacement from a merely similar Ethernet interface before committing to a redesign.

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DP83902AVLJ - 5V Serial Network Controller | Texas Instruments
DP83902AVLJ

DP83902AVLJ - 5V Serial Network Controller | Texas Instruments

The Texas Instruments DP83902AVLJ is a serial network interface controller for twisted-pair networks, supplied in a 100-lead rectangular QFP package and operating from a 4.75 V to 5.25 V supply. Its listed characteristics include a serial interface, approximately 140 mA supply current, commercial temperature grade, and tray packaging. The device is described by Texas Instruments as an ST-NIC serial network interface controller and is categorized as an obsolete interface controller. A serial network interface controller is an integrated circuit that manages the communication path between a computer or embedded system and a network medium. In the product hierarchy, this controller belongs to interface ICs and ultimately to the broader semiconductor category. The DP83902AVLJ was designed around twisted-pair network connectivity, where a physical-layer transceiver is commonly paired with a controller. The controller handles network framing and data exchange, while the external transceiver performs signal encoding, reception, and electrical isolation from the copper medium. The DP83902AVLJ uses a 4.75 V minimum and 5.25 V maximum supply voltage, giving system designers a nominal 5 V operating rail. The verified distributor listing reports a supply current of 140 mA. Its 100-pin QFP package provides a substantial number of external connections, which is typical for legacy Ethernet controllers that require parallel host data paths, address and control signals, clocking, interrupt signaling, and twisted-pair transceiver interfaces. Package dimensions, pin names, operating-temperature limits, Ethernet data rate, transceiver interface details, and electrical timing limits are not included in the supplied verification data. The DP83902AVLJ is most relevant to legacy networking equipment, industrial control systems, embedded controllers, and industrial Ethernet designs that already use this controller and its associated application circuitry. It should not be assumed interchangeable with a modern Ethernet controller merely because both perform networking functions. The verified cross-reference material specifically states that the STMicroelectronics SERC816/TR is not a direct drop-in replacement because its pinout, internal biasing, and MII timing characteristics differ. A PCB replacement therefore requires a detailed electrical, timing, and pin-level review rather than a simple component substitution. This page consolidates the verified distributor specifications, lifecycle information, sourcing details, and replacement constraints for DP83902AVLJ. Pricing is presented as unavailable because the verified sources provide quote or request-for-quotation terms rather than numeric unit prices. The pin table records all 100 package terminals but marks individual terminal names as unavailable rather than guessing pin functions. Engineers should obtain the manufacturer datasheet and original design reference before layout changes, firmware updates, or obsolescence redesigns.

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DP83905AVQB - 10BASE-T Ethernet Controller | Texas Instruments
DP83905AVQB

DP83905AVQB - 10BASE-T Ethernet Controller | Texas Instruments

The Texas Instruments DP83905AVQB is an AT/LANTIC AT local-area-network twisted-pair interface controller with an integrated IEEE 802.3 10BASE-T PHY, an ISA interface, and a 160-pin QFP package measuring 28 mm by 28 mm. It operates from a single 4.75 V to 5.25 V supply and is specified for 0 °C to 70 °C commercial-grade operation. An Ethernet controller integrates the digital protocol, media-access, and physical-layer functions needed to connect a legacy personal computer or embedded ISA bus to a 10BASE-T twisted-pair network. The DP83905 supports the AT/LANTIC protocol family, IEEE 802.3 operation, and 10BASE-T signaling. Because the physical layer is integrated, a compliant design can use the controller with the appropriate line-driver, filter, isolation, and magnetics interface rather than implementing the complete PHY separately. Verified device attributes include a 4.75 V to 5.25 V supply range, nominal 100 mA supply current, IEEE 802.3 network support, 10BASE-T PHY operation, ISA host interfacing, a commercial temperature grade of 0 °C to 70 °C, and a 160-BFQFP package. The device is identified as obsolete in the supplied manufacturer-related documentation, so it is most appropriate for maintenance of legacy AT-compatible networking equipment rather than new mass-production designs. The DP83905AVQB belongs to the former National Semiconductor controller portfolio now served by Texas Instruments. Its large 160-pin gull-wing QFP construction is characteristic of late-1980s and early-1990s PC interface controllers, when integrating the AT bus logic, network controller, and 10BASE-T PHY into one device reduced component count and simplified legacy adapter-card design. Typical uses include industrial legacy controllers, AT-compatible Ethernet adapters, embedded data-acquisition systems, and repair or obsolescence-management programs for installed networking equipment. The ISA interface and 10BASE-T speed make the device most suitable for systems that already rely on the AT/LANTIC environment; it is not a modern 100BASE-TX or gigabit Ethernet controller. When replacing this component, engineers should verify the complete 160-pin footprint, exposed pad requirements, power rails, oscillator components, magnetics isolation, and legacy bus termination before substituting. Because this part is obsolete and few verified pin-compatible replacements are documented, board-level redesign to a current Ethernet controller may be safer than assuming equivalent availability.

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DP83907VF - 10Base-T Ethernet NIC Controller ISA Interface | TI
DP83907VF

DP83907VF - 10Base-T Ethernet NIC Controller ISA Interface | TI

The Texas Instruments DP83907VF (AT/LANTIC II) is a single-chip CMOS VLSI 10Base-T Ethernet Network Interface Controller (NIC) with integrated ISA bus interface, delivered in a 132-pin BQFP (PQFP) package. It supports a single 10 Mb/s twisted-pair or coaxial channel, operates from a single 5V supply (4.75 V to 5.25 V) drawing approximately 150 mA, and is qualified to the commercial temperature range. What is an Ethernet NIC controller? A NIC controller is an integrated circuit that bridges a host processor's parallel bus (such as ISA, PCI, or PCIe) to a Media Access Control layer that implements the CSMA/CD protocol used by IEEE 802.3 Ethernet. The DP83907 sits in the hierarchy: 10Base-T PHY → Ethernet MAC → NIC controller → host bus controller → PC motherboard. By integrating the entire PC-AT ISA bus interface along with the MAC and 10 Mb/s physical front-end, the DP83907 reduces discrete component count and lets designers add a 10 Mb/s LAN port with minimal glue logic. Key features of the DP83907VF include on-chip Manchester encoder/decoder for 10Base-T, integrated 10Base-T transceiver (twisted-pair), built-in attachment unit interface (AUI) for external MAU support, full ISA (Industry Standard Architecture) 8/16-bit bus mastering DMA engine, and configurable I/O and memory mapped modes. The device offers a 2-channel CSMA/CD link, supporting 1.25 MBps raw throughput on the serial side. CMOS process technology keeps power dissipation under 1W typical. Architecturally, the DP83907VF partitions cleanly into a bus interface unit, a CSMA/CD MAC engine, a Manchester ENDEC, and a 10Base-T analog front end. The MAC performs framing, CRC-32 generation/checking, collision detection, and back-off timing, while the analog front-end provides transmit waveshaping and receive equalization for 100-meter Category-3 cable runs. The combination targets PC-AT/PC/XT motherboards, ISA add-in cards, embedded LAN adapters, and industrial 10 Mb/s backbones. Typical applications include ISA-bus Ethernet NIC add-in cards, factory-floor 10Base-T bridges, industrial automation controllers with embedded LAN ports, legacy PC motherboard LAN-on-board designs, and 10 Mb/s repeaters/hubs requiring a host-managed controller. Because the part integrates the AUI option, it can also drive an external 10Base2 (BNC) transceiver for coax-based legacy LANs. When designing with the DP83907VF, plan ISA bus arbitration because bus-master DMA requires care to coexist with other bus masters. Add 4.7 kΩ pull-ups on configured strap inputs (IRQ, I/O base address) and keep the analog ground (AGND) and digital ground (DGND) separated under the package, joining them only at the PCB main ground plane to preserve 10Base-T jitter margins. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.

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DP8390DV - 10 Mbps 5 V Ethernet NIC | Texas Instruments
DP8390DV

DP8390DV - 10 Mbps 5 V Ethernet NIC | Texas Instruments

The Texas Instruments DP8390DV is a 10 Mbps, 5 V Ethernet network interface controller supplied in a 68-pin PLCC package measuring 25.13 mm by 25.13 mm. It is designed to interface host systems with CSMA/CD local-area networks, including Ethernet Thin implementations, while presenting a dedicated network-controller function rather than requiring the host processor to manage the physical network medium directly. The verified distributor listing identifies the device as an Ethernet controller interface and describes its 68-PLCC construction. What is an Ethernet network interface controller? An Ethernet NIC is an interface IC positioned between a computer or embedded controller and an Ethernet physical layer. It handles network-oriented communication tasks and reduces the electrical and protocol burden placed on the host system. In the broader semiconductor hierarchy, the DP8390DV is a communication interface controller, an interface IC, and ultimately a semiconductor used in Ethernet networking equipment and embedded data-processing systems. The DP8390DV’s primary verified characteristics include a 10 Mbps data rate, a 5 V supply, and approximately 40 mA supply current. Those values place it in the established 10BASE-T-era Ethernet hardware category. Its PLCC package provides a surface-mount PCB footprint with J-leads, while the listed 25.13 mm by 25.13 mm body size supports compact but not especially miniature industrial and legacy-compatible designs. DP8390D-family devices were designed to ease host interfacing with CSMA/CD local-area networks, including Ethernet Thin networks. The controller therefore belongs in systems where a host bus must communicate through an Ethernet-compatible network interface. Compared with a general-purpose interface IC, its defining value is Ethernet-specific integration: the network function is consolidated into a dedicated controller rather than being implemented entirely with host firmware and discrete logic. Typical uses include embedded Ethernet controllers, industrial data-acquisition systems, legacy terminal equipment, print servers, network-interface modules, and host adapters designed around the DP8390 family. In these applications, the DP8390DV can serve as the network-facing IC while an external transceiver, magnetic interface, connector, and system controller provide the surrounding physical-layer and host-side implementation. The principal design consideration is that this is a mature 10 Mbps controller rather than a current multi-gigabit Ethernet PHY or modern system-on-chip interface. Board design must follow the manufacturer pinout and required external components exactly. Signal routing, supply decoupling, thermal exposure, and network magnetics or transceiver selection should be validated against the official DP8390 documentation before layout release. This page consolidates verified distributor specifications, sourcing information, interface context, and application guidance. It does not invent unprovided pin assignments, timing values, temperature limits, or replacement parts, so unavailable engineering data remains explicitly marked rather than being inferred.

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DP83910AN - CMOS Serial Network Interface 24-DIP | National Semiconductor
DP83910AN

DP83910AN - CMOS Serial Network Interface 24-DIP | National Semiconductor

The National Semiconductor (Texas Instruments) DP83910AN is a CMOS Serial Network Interface (SNI) IC that provides Manchester data encoding and decoding for IEEE 802.3 Ethernet networks, supplied in a 24-pin DIP through-hole package (0.300 inch, 7.62 mm body width) and operating from a single 4.75 V to 5.25 V supply. The device is a direct-pin functional replacement for the legacy bipolar DP8391 SNI, integrating the physical-layer attachment functions required to interface an Ethernet transceiver (such as the DP8392 or DP839CT) to a controller or terminal-end Manchester encoder/decoder across 10 Mb/s Thin Ethernet (10BASE2/10BASE5) topologies. A Serial Network Interface (SNI) is a category of interface IC that sits between the Ethernet coaxial transceiver and the system controller, performing Manchester encoding, clock recovery, jabber monitoring, and link-integrity signalling per the IEEE 802.3 physical-layer specification. Within the broader hierarchy, the DP83910AN belongs to the network interface IC family, which falls under interface ICs, then integrated circuits, then semiconductors, providing OSI layer-1 connectivity and isolating the host CPU from line-coding analogue details. Key features include 10 Mb/s Manchester encoding/decoding, integrated jabber detection and Link Test generation, CMOS low-power operation versus the original bipolar DP8391, and a wide supply tolerance of 4.75 V to 5.25 V. The 24-DIP through-hole package supports easy insertion into legacy Ethernet adapter boards and industrial retrofit designs, while the CMOS process reduces typical operating current compared to its bipolar predecessor. The device also provides collision-detection and carrier-sense signalling flags that flow into the upper-layer MAC controller. Architecturally, the DP83910AN combines a phase-locked loop (PLL) for receive clock recovery, a 10 MHz oscillator interface, transmit clock-generation logic, and differential Manchester encode/decode blocks. Because the silicon is a drop-in CMOS replacement for the DP8391, existing schematic layouts can accept the DP83910AN without board rework, a critical advantage for legacy industrial networks and instrumentation that depend on the older part. Typical applications include 10BASE2 / 10BASE5 Ethernet adapter cards, industrial SCADA controllers, legacy factory-floor networking interfaces, and embedded instrumentation that must communicate over IEEE 802.3 media. The DP83910AN is also commonly used by restoration projects for early-1990s networking hardware and by test equipment vendors supporting IEEE 802.3 physical-layer compliance. When designing with this device, note that the DP83910AN is now in obsolete/EOL lifecycle, so long-term sourcing requires attention to authorized distributor stock and the qualified cross-references listed in the alternatives section. Decoupling with 0.1 uF ceramic capacitors close to VCC/GND pins is essential for the integrated PLL to maintain stable clock recovery under varying line loading. This page synthesizes distributor pricing from DigiKey and Win Source, drops-in cross-reference data, lifecycle risk analysis, and Pin Configuration design notes that go beyond what the original manufacturer datasheet provides as of October 22, 2026.

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