EP910DC-15
EP910DC-15 - Classic EPLD 900 Gates 15ns DIP-24 | Altera
The Altera EP910DC-15 is a member of the Classic EPLD (Erasable Programmable Logic Device) family, providing high-speed, low-power CMOS logic integration in a 24-pin ceramic DIP (DC) package. The device is speed grade 15, indicating a 15 ns maximum pin-to-pin propagation delay, and is specified for the commercial operating temperature range. Built on advanced CMOS EPROM technology, the EP910 delivers approximately 900 usable gates of combinatorial and registered logic for glue-logic, bus decoding, state-machine, and address- decoding applications that previously required multiple discrete TTL or CMOS SSI/MSI parts.
An EPLD (Erasable Programmable Logic Device) is a one-time- or UV-erasable non-volatile programmable logic IC from the late-1980s/early-1990s era, sitting in the device hierarchy between simple PAL/GAL SPLDs and modern SRAM-based FPGAs. EPLDs integrate multiple AND/OR arrays, programmable macrocells, and a fixed interconnect into a single package, giving designers higher density and predictable timing compared to discrete 22V10-style PALs while remaining simpler and cheaper than contemporary FPGAs. Altera's Classic family extended this concept by sharing a uniform macrocell architecture across EP310, EP320, EP610, EP910, EP1800 and EP1810 densities, allowing seamless design migration through the same toolchain.
Key features of the EP910DC-15 include 24 macrocells, 12 dedicated inputs, 12 bidirectional I/O pins, 10 flip-flops, 24 product terms per macrocell, and a 15 ns tPD. The device is erasable via a quartz window (ceramic DIP package only), enabling prototype iteration and field re-programming on the same silicon. I/O structures are TTL-compatible and the part supports either 5V-only or, on later die revisions, 5V/3.3V mixed-voltage operation, making it suitable for bridging legacy and modern logic rails in brownfield designs. A logic-lock feed-through path and pin-keeper circuits reduce external glue requirements.
Architecturally, the EP910 implements a sum-of-products PLA structure feeding a flexible output macrocell. Each macrocell contains a programmable flip-flop, output enable, and feedback path that can be reconfigured post-fit to implement D/T/JK flip-flops, latches, or pure combinatorial output with selectable polarity. This uniform architecture yields predictable, deterministic timing - a key reason Classic EPLDs were preferred over early SRAM-based FPGAs for control logic where tCO and tSU needed to be fixed at compile time. Power consumption is approximately 200-400 mW active at 25 MHz, depending on utilization and toggle rate, and drops to a low CMOS standby in idle.
Typical applications include address decoding and chip-select generation in 8086/68k/MIPS-based microprocessor systems, bus arbitration, DRAM/VRAM control logic, channelized interface glue between legacy peripherals, firmware state machines for disk controllers, and industrial PLC ladder-logic replacement. The 24-pin DIP form factor is also convenient for through-hole prototype boards, educational labs, and legacy equipment repair where surface-mount adapters would be impractical.
When designing with the EP910DC-15, treat the 15 ns tPD as a hard budget: derive fMAX from the registered tCO + logic + tSU path and de-rate by 20% for setup margin. Decouple VCC with a 0.1 uF ceramic plus 10 uF tantalum placed within 5 mm of the pins, and reserve the unused macrocells as outputs driving a known state to avoid bus contention during ISP. For new designs, prefer Altera MAX II or Lattice ispMACH 4000 families; the EP910DC-15 is recommended only when matching an existing pinout or repairing installed equipment.
This page synthesizes distributor pricing snapshots, same-brand and cross-brand drop-in alternatives, and practical design notes not assembled on any single manufacturer or distributor datasheet.
询价
联系我们
