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DP83223V-1 - 100 Mbps Ethernet Transceiver | Texas Instruments
The National Semiconductor DP83223V-1 is a single-port Ethernet TX/RX integrated circuit operating from a 5 V supply at 10 Mbps or 100 Mbps in a 28-pin PLCC package measuring 11.51 mm by 11.51 mm. It is identified as a Twister high-speed networking transceiver and belongs to the interface IC hierarchy used to connect twisted-pair network equipment. An Ethernet physical-layer transceiver converts logical data into signals suitable for a network cable and converts returning signals into data for the associated media-access controller. The DP83223V family supports 10 Mbps and 100 Mbps operation, according to the verified distributor specifications. Its single-port architecture serves legacy Fast Ethernet equipment rather than gigabit networks, so PHY function, cable topology, and controller support must be checked before modern system integration. The verified listings identify the device as an Ethernet transceiver with one port, a 5 V supply, and a 100 Mbps maximum listed data rate. The target ordering code DP83223V-1 is listed by DigiKey through Rochester Electronics. The base DP83223V is also listed by DigiKey in a 28-pin PLCC package, providing a useful package reference for design review. Detailed electrical limits, termination requirements, transmit-drive strength, receiver thresholds, temperature range, and exact pin names were not included in the supplied source data and therefore are not inferred here. DP83223V can be evaluated in legacy 10/100-Mbps endpoint, network-interface-card, hub-interface, switch-interface, and industrial-retrofit designs when the surrounding controller and magnetics are compatible with the original Twister architecture. Designers should not substitute it for a gigabit PHY because the verified maximum data rate is 100 Mbps. Likewise, an SOHO or industrial controller must support the same line coding, signaling, isolation, and termination arrangement before the transceiver is selected. The principal design consideration is that a transceiver is only one element of an Ethernet physical layer. The line interface also depends on transformer or magnetics, termination network, connector, controlled-impedance printed circuit board, grounding, and electromagnetic-compatibility design. Follow the manufacturer datasheet for pin connections and application circuitry. Because the exact schematic and pin table were not supplied, validate the complete interface against the current manufacturer documentation rather than relying on distributor summaries. This page consolidates verified distributor identification, sourcing links, package information, and engineering-selection guidance. It does not invent missing timing, electrical, compliance, lifecycle, or pricing values; those fields remain explicitly unresolved where the supplied evidence is insufficient. That distinction is especially important for an older networking transceiver, where exact revision behavior and sourcing status can determine whether a legacy design remains electrically and commercially reproducible.
DP83223VB - High-Speed Twisted-Pair Transceiver | National Semiconductor
The National Semiconductor DP83223VB is a high-speed twisted-pair networking transceiver built for three-level MLT-3 encoded data-stream transmission and reception, supplied in a 28-pin PLCC package. The verified product listing identifies the device as an Ethernet transceiver, while the DP83223 family description identifies it as a TWISTER high-speed networking transceiver. Its core function is to interface digital communications equipment with a physical transmission medium, supporting network-infrastructure designs that require dedicated transmit and receive signal handling. The package and electrical details available from the supplied sources are limited, so the complete pin map and several operating parameters require confirmation from the manufacturer datasheet before layout or replacement work. What is a twisted-pair transceiver? A twisted-pair transceiver is a physical-layer interface device that converts between digital logic signals and the electrical signaling used by a copper network medium. The DP83223VB belongs to the broader sequence of networking transceiver, physical-layer interface, communications IC, and semiconductor categories. Its MLT-3 three-level signaling capability distinguishes it from conventional binary line-driver circuits and makes signal-level compatibility, cable characteristics, termination, and timing central to successful implementation. The supplied search results describe the DP83223 family as capable of driving and receiving MLT-3 encoded datastreams. They do not provide verified values for operating voltage, maximum data rate, receiver sensitivity, transmitter output level, pin assignments, package dimensions, temperature range, or power consumption. Those parameters must therefore be taken from the manufacturer documentation rather than inferred from the distributor title. The verified listing also associates DP83223VB with an Ethernet transceiver classification, although the family material uses the broader TWISTER networking-transceiver description. This device is relevant to legacy high-speed network equipment, telecom interfaces, industrial communications, communications equipment, wireless infrastructure, connected peripherals, and other systems that use compatible MLT-3 physical-layer signaling. Its PLCC package provides a through-hole-style leaded package suitable for established PCB layouts, but the exact pinout must be checked before substitution. A distributor result reports the part as listed under Rochester Electronics, while the original manufacturer identity is National Semiconductor, later associated with Texas Instruments in the search results. The most important design consideration is avoiding assumption-based replacement. Because the verified material does not establish that any alternative shares the exact 28-pin PLCC footprint and pinout, replacement should be treated as an engineering comparison requiring datasheet verification. Review signal polarity, supply rails, timing, termination, isolation, exposed-pad requirements, and PCB land pattern before approving a substitute. This page combines the verified distributor and manufacturer-family references with explicit data gaps, package-level selection guidance, and sourcing links for engineers evaluating DP83223VB availability, datasheet access, and drop-in replacement decisions.
DP83223VX - 5V Twister Transceiver | Texas Instruments
The Texas Instruments DP83223VX is a 5 V TWISTER high-speed networking transceiver with one transceiver channel in a 28-pin PLCC package measuring 11.51 mm by 11.51 mm. The device is intended for data communication over shielded or unshielded twisted-pair cabling and performs the physical-layer functions required to connect digital network equipment to a twisted-pair medium. Its verified supply range is 4.75 V to 5.25 V. A network transceiver is an interface IC that converts logic-level signals into physical-layer signals suitable for a wired network and converts received signals back into usable digital data. In the hierarchy, the DP83223VX is a network interface transceiver, a communications interface IC, and a semiconductor. TWISTER describes the physical-layer signal-processing approach used for differential twisted-pair networking rather than a modern two-wire interface standard. The verified information identifies a transceiver configuration, a 4.75 V to 5.25 V operating supply, and a 28-PLCC J-lead package. Distributor listings classify the part as a driver, receiver, and transceiver, while a technical listing describes it as a high-speed physical-layer device for shielded or unshielded twisted-pair cabling. Detailed data rates, driver and receiver counts, cable reach, termination requirements, and electrical timing limits were not supplied in the verified data and must be confirmed from the manufacturer datasheet before design release. The PLCC package provides a through-hole-style surface-mount form factor with J-shaped leads and a compact 11.51 mm by 11.51 mm body. Its legacy package and interface function make careful footprint verification important when comparing it with modern Ethernet devices. Board layout must preserve the manufacturer's recommended network-line separation, component spacing, grounding, and termination arrangement; the available search excerpts do not provide enough detail to specify those values safely. Potential uses include legacy high-speed network interface equipment, industrial data links, embedded communications controllers, and telecommunications equipment using compatible twisted-pair signaling. The device should be selected only after confirming the protocol, signaling rate, cable type, connector, isolation requirements, and exact pinout against the authoritative datasheet. A modern PHY or Ethernet transceiver may offer different compliance, topology, and supply characteristics and therefore is not automatically interchangeable. For a new layout, do not infer pin assignments from the distributor package title. Obtain the DP83223 datasheet, compare every power, ground, driver, receiver, enable, and network-line connection, and validate the assembled channel with the intended cable and system load. This page synthesizes the supplied manufacturer-linked search results, distributor availability references, package information, and sourcing guidance; missing electrical values are deliberately not guessed.
DP83257VF - FDDI Physical Layer Controller | Texas Instruments
The Texas Instruments DP83257VF is a PLAYERa+ FDDI physical-layer controller with a 160-pin QFP package. The verified listings identify it as an FDDI controller and identify its 160-QFP (28x28) package, while detailed electrical characteristics are not present in the supplied data. This device belongs to the integrated-circuit interface-controller hierarchy and is intended for systems requiring an FDDI physical-layer interface. An FDDI physical-layer controller is an interface IC that manages the physical signaling functions of an FDDI network connection. FDDI, or Fiber Distributed Data Interface, is a local-area networking technology whose physical layer handles signal transmission and reception over fiber or compatible physical media. The controller therefore sits between network-system logic and the physical medium, while higher-level software and protocol functions remain outside the device’s stated role. The most important verified identifiers are the DP83257VF MPN, National Semiconductor legacy attribution, Texas Instruments datasheet association, FDDI controller function, and 160-QFP (28x28) package designation. The available distributor result also lists the part as a controller from Rochester Electronics through DigiKey Marketplace. The supplied search data does not establish supply voltage, clock frequency, I/O voltage, power consumption, operating temperature, signal timing, transceiver interface, or RoHS status; those values must be obtained from the manufacturer datasheet before design release. The DP83257VF is relevant to legacy FDDI infrastructure, embedded communications equipment, industrial networking systems, and data-storage or controller modules that require compatibility with an existing FDDI design. Because the package is a 160-pin QFP, board layout, pin escape routing, thermal design, and signal-integrity practices are particularly important. Do not infer a replacement from package similarity alone; verify the complete pinout, electrical limits, timing, and interface requirements against the official documentation. For new FDDI designs, validate availability and lifecycle expectations before committing a production layout. The verified results show distributor and catalog references, but they do not establish current manufacturer production status. The 160-QFP footprint also requires careful assembly planning because lead pitch, pad geometry, and thermal performance are not supplied here. Confirm those details from the official package drawing. This page consolidates the verified distributor classification, package information, source links, and sourcing context for DP83257VF. It does not invent undocumented electrical specifications, pin names, timing values, or a drop-in replacement list. Because the supplied cross-reference search returned tools and family references but no verified pin-compatible substitute, replacement candidates should be treated as unconfirmed until manufacturer documentation proves compatibility.
DP8340N - Encoder Transmitter 24-DIP | Texas Instruments
The Texas Instruments DP8340N is a bipolar microprocessor circuit packaged as a 24-pin dual in-line encoder transmitter, with an operating supply value of [DATA_NEEDED: supply voltage] and encoder-interface parameters of [DATA_NEEDED: electrical characteristics]. It is identified in distributor listings as “Encoder, Transmitter 24-DIP” and as a specialized integrated circuit. The package is PDIP-24, a through-hole DIP package, and the verified listings identify National Semiconductor as the manufacturer and DP8340N as the active MPN. What is an encoder transmitter? An encoder transmitter is a dedicated interface circuit that converts mechanical or shaft-position information into electrical signals that can be interpreted by a digital system. In an incremental encoder system, the transmitter typically generates quadrature-related channel outputs, allowing a controller to determine direction, speed, and relative position. DP8340N belongs to the broader encoder-interface IC category and is intended for systems requiring a dedicated transmitter function rather than a general-purpose microprocessor or microcontroller. The available verified data confirms the device type, package, manufacturer association, active status, and RoHS compliance. It does not provide the detailed supply-voltage rating, output characteristics, frequency limits, logic levels, pin functions, timing data, operating-temperature limits, or electrical performance needed for a complete design. Those values are therefore not inferred. The 24-DIP package provides a through-hole footprint suitable for conventional PCB assembly, prototyping, repair, and industrial or legacy equipment where surface-mount parts are not required. Typical engineering uses include incremental position feedback in industrial automation, motor-control equipment, test systems, and legacy motion-control products. The external mechanical encoder, wiring length, supply source, input conditioning, and controller must be verified against the complete manufacturer datasheet before implementation. Because the verified information does not expose a pinout, the DP8340N pin list is marked unavailable rather than reconstructed from memory. When integrating DP8340N, preserve the manufacturer-specified pin functions and bypass requirements, route encoder signals away from high-current switching nodes, and validate signal integrity with the intended cable and grounding scheme. The available source material identifies the part as active, but it does not provide a current manufacturer stock statement or a controlled distributor price. Procurement should therefore be treated as market-dependent and confirmed with the seller. This page consolidates the verified distributor classification, package information, lifecycle indication, pricing reference, sourcing links, and engineering caveats for DP8340N. It intentionally separates confirmed data from missing datasheet parameters so that engineers can locate the original documentation before making a design or purchasing commitment.
DP83800AVF Ethernet Interface Controller | National Semiconductor
The National Semiconductor DP83800AVF is an Ethernet interface controller associated by distributor listings with drivers, receivers, transceivers, and 10/100-class network-adapter functions. The verified sources identify the original manufacturer as National Semiconductor, now associated with Texas Instruments, but they do not provide a complete manufacturer datasheet, electrical tables, timing values, package dimensions, or an official product-page description. The DP83800AVF package is identified publicly as QFP, while the exact pin count, pin names, and exposed-pad configuration remain unverified in the supplied data. An Ethernet interface controller is an interface IC that connects an embedded system or network adapter to a physical Ethernet network. In the broader hierarchy, it belongs to integrated circuits, interface ICs, network controllers, and communications semiconductors. Such devices typically coordinate physical-layer signaling, media access, data framing, and host-facing transfers, but the exact division of functions implemented by DP83800AVF cannot be confirmed from the supplied search snippets. The available distributor listing describes DP83800AVF as an ISA network adapter with an IC designation and catalog number 10/100. Another distributor result categorizes it among drivers, receivers, and transceivers. These labels indicate legacy networking and interface applications, but they are insufficient to establish supply voltage, clock, transceiver thresholds, media support, package dimensions, operating temperature, or host-bus timing. Those parameters require the original manufacturer datasheet. Potential legacy applications include ISA-based industrial control equipment, embedded controllers, network adapters, and industrial Ethernet systems designed around older host buses. These applications are contextual rather than verified design recommendations; host-bus compatibility, transceiver requirements, reference circuitry, magnetic-component integration, and signal-integrity constraints must be confirmed before schematic reuse. The primary design concern is source fidelity. DP83800AVF appears as an older or specialized catalog part, and distributor category labels differ across the retrieved pages. Engineers should obtain the original datasheet, verify the exact package suffix and lead count, compare every pin and supply rail, and reproduce the reference network before beginning a layout. A modern Ethernet controller may be electrically more capable while still being unsuitable as a drop-in replacement because legacy ISA signaling, voltage levels, timing, and package geometry can differ. This page distinguishes verified catalog facts from missing technical data, preserves uncertainty instead of guessing, and provides sourcing and validation guidance where the supplied evidence does not support numerical specifications. It also records that the available search results do not establish a manufacturer-authorized drop-in replacement for this legacy device.
DP83826AI - Low-Latency 10/100 Ethernet PHY | TI
The Texas Instruments DP83826AI is a low-latency, deterministic 10/100 Mbps industrial Ethernet PHY optimized for EtherCAT and real-time industrial fieldbus systems. Housed in a compact 32-pin VQFN (RHB) 5x5 mm package, the DP83826AI integrates an IEEE 802.3 10BASE-Te and 100BASE-TX PHY with MII and RMII MAC interfaces, targeting designs where deterministic sub-microsecond latency is critical for closed-loop control. The part supports industrial temperature operation (-40C to +85C) and offers enhanced EMC/ESD performance rated for IEC 61000-4-2 Class A 8 kV contact discharge, making it suitable for harsh factory environments where DP83826I (the non-improved variant) does not meet Class A margins. The DP83826AI also adds a strap option on RX_CLK to prevent link drop in EMI-prone industrial settings. An industrial Ethernet PHY (Physical Layer transceiver) is a specialized transceiver IC that connects an MCU or SoC's MAC (Media Access Controller) to the copper twisted-pair medium via an isolation transformer, performing 10BASE-Te/100BASE-TX line coding, echo cancellation, and clock/data recovery. In the broader system hierarchy, the PHY sits below the MAC layer (Layer 2) of the OSI reference model and above the transformer and RJ-45 magnetics, forming the physical interface that turns serialized MAC data into MLT-3 (100BASE-TX) or differential Manchester-coded (10BASE-Te) signals on the MDI lines. For deterministic real-time protocols such as EtherCAT, Profinet IRT, and SERCOS III, the PHY's transmit and receive pipeline latency must be tightly bounded; the DP83826AI is designed to meet those bounds. Key differentiating features of the DP83826AI include sub-microsecond deterministic loop latency in 100 Mbps full-duplex mode, low power consumption suitable for distributed sensor nodes, integrated PHY diagnostics including cable diagnostics and link-quality monitoring, support for both MII and RMII bus widths, and an industrial-grade operating range. The 32-VQFN (RHB) package with an exposed thermal pad enables compact board layouts typical of small PLC slices, distributed I/O stations, and motor-control daughterboards where PCB real estate is at a premium. In typical operation the DP83826AI is paired with an industrial MCU (such as TI's Sitara AM243x family) running an EtherCAT slave stack, with the PHY providing the physical edge to a 100BASE-TX link. The architecture focuses on minimizing store-and-forward buffers in the receive and transmit paths, which is what enables the bounded, jitter-free latency that EtherCAT's distributed clock synchronization demands. Hardware straps allow configuration of master/slave mode, MII vs. RMII selection, and 10/100 Mbps speed without external software intervention in strap-only systems. Typical applications include EtherCAT slave modules, Profinet IRT devices, industrial servo drives, distributed I/O over industrial Ethernet, and small-form-factor PLCs. Real-world deployments span factory-floor closed-loop motion control, substation automation with IEC 61850, and deterministic sensor networks where IEEE 1588 timing is carried over the same Ethernet link. When designing with the DP83826AI, pay close attention to magnetics selection (the part requires a 1:1 transformer ratio with a center-tapped primary for 100BASE-TX), PCB layout for the MDI traces (100-ohm differential with controlled impedance), and isolation barrier placement to meet IEC 61800-3 industrial emissions requirements. Use of dedicated magnetics with integrated common-mode chokes is recommended to take full advantage of the device's improved EMC margin relative to DP83826I.
DP83848IVV - 10/100 Ethernet PHY Transceiver | Texas Instruments
The Texas Instruments DP83848IVV is a single-port 10/100 Mb/s Ethernet physical layer transceiver (PHYTER) in a 48-pin LQFP (7x7 mm) package designed for reliable operation across industrial temperature ranges. The device supports IEEE 802.3u Fast Ethernet, integrating MII and RMII MAC interfaces, auto-negotiation, and on-chip echo cancellation to simplify PCB layout. An Ethernet PHY (Physical Layer Device) is a transceiver IC that sits between a MAC controller and the copper media (twisted pair), handling analog line driving/receiving, clock recovery, link monitoring, and 10BASE-T/100BASE-TX encoding/decoding. PHYTERs are a category of Ethernet PHYs that emphasize robust industrial-grade operation, sitting within the broader Ethernet controller hierarchy: PHY -> transceiver -> network interface device -> communication IC -> semiconductor. Key features of the DP83848IVV include integrated 100BASE-TX/FX physical coding sublayer (PCS) and physical media attachment (PMA), 3.3V single-rail operation with 2.5V internal LDO, Auto-MDIX crossover detection, Energy Detect Plus power-down modes, and 4 kV ESD tolerance on the MDI pins. The device also features low-latency (sub-100ns) MII throughput, hardware pause-frame support for flow control, and an IEEE 1149.1 JTAG boundary-scan port for board test. The 48-LQFP package provides a thermally efficient surface-mount footprint with 31.4 C/W typical junction-to-ambient resistance. Architecture-wise, the DP83848IVV combines a DSP-based receive path with adaptive equalization to recover signals over >150m of CAT-5 cable, a 125 MHz PLL for 100BASE-TX clocking, and a 25 MHz crystal interface or external clock input. Internal voltage regulation simplifies power tree implementation by accepting a single 3.3V supply. The DP83848IVV is designed for industrial Ethernet nodes, factory automation controllers, motor drives with EtherCAT/PROFINET bridges, building-automation gateways, IP-based surveillance cameras, and any embedded MCU/MPU with MII/RMII needing 10/100 connectivity. Its -40C to +85C industrial temperature grade supports deployment in harsh environments. When designing with the DP83848IVV, follow TI's reference layout for the magnetics and 49.9 ohm 1% termination resistors as specified in the datasheet application section. Use a 25 MHz crystal or feed a clean external CMOS clock; keep the MDI traces length-matched within 50 mils and 100-ohm differential-impedance controlled for best EMI margin.
DP83848IVVX/NOPB - Industrial 10/100 Ethernet PHY | TI LQFP-48
The Texas Instruments DP83848IVVX/NOPB is a robust 10/100-Mbps Ethernet PHY transceiver (PHYTER) housed in a 48-pin LQFP (PT) package, designed for industrial temperature operation from -40C to +85C. It integrates MII/RMII/SNI MAC interfaces, supports both 100BASE-TX and 10BASE-T standards per IEEE 802.3u, and operates from a single 3.3 V supply. The device includes Auto-MDIX, hardware-driven cable diagnostics, and JTAG boundary-scan access, providing engineers with production-grade link visibility. An Ethernet PHY (physical layer transceiver) is the analog front-end that connects an MAC controller to the copper twisted-pair medium, performing encoding/decoding (MLT-3 for 100BASE-TX, Manchester for 10BASE-T), clock recovery, and adaptive equalization. PHYs sit at the bottom of the OSI physical layer and provide the digital baseband interface (MII/RMII/GMII) that links to the MAC. They are a sub-category of network interface ICs within the broader interface IC family, sitting between digital logic and the magnetics/connector of an Ethernet port. Key features include 3.3 V single-supply operation, integrated 100BASE-TX DSP with adaptive equalization and baseline-wander correction, programmable LED status outputs, IEEE 802.3u auto-negotiation, and a hardware Energy Detect power-down mode. The DP83848IVVX/NOPB ships with the SNI (Serial Network Interface) and JTAG test access port enabled, which simplifies board-level test and field diagnostics in factory-automation equipment. Architecturally, the part uses an DSP-based receive path with a 4B/5B/MLT-3 encoder-decoder and a PLL that recovers clock from inbound data. The integrated 1:1 turns-ratio magnetics interface and on-chip termination reduce external BOM count compared to legacy PHYs that required external termination networks, while the PT (LQFP-48) package gives a robust 0.5 mm pitch footprint suitable for industrial PCB assembly. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), factory-automation nodes, motion-control drives, and embedded gateways requiring -40C to +85C operation. The wide temperature range and JTAG access make the part particularly attractive in Industry-4.0 retrofits where deterministic connectivity and field serviceability are required. When designing with this device, place the 50 ohm transmission-line impedance traces between PHY and magnetics to within 25 mm, and use the recommended 2 kV HBM-rated magnetics module to meet industrial ESD/Surge targets. Always verify the reference clock source stability, because MII jitter margins shrink as cable length approaches 100 m. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical layout notes not always aggregated in the manufacturer datasheet, so procurement and engineering teams can shortlist a known-good BOM faster.
DP83858VF - 8-Port 100 Mb/s Ethernet Repeater | Texas Instruments
The Texas Instruments DP83858VF is a 100 Mb/s TX/T4 Repeater Interface Controller, also identified as 100RIC8, supporting up to eight 100 Mb/s Ethernet ports in a 132-PQFP package. The supplied data specifies a 4.75 V to 5.25 V supply range, 295 mA supply current, and IEEE 802.3 compatibility. An Ethernet repeater controller is an interface IC within the Ethernet networking hierarchy. It coordinates multiple 100 Mb/s network segments, regenerates and retimes received signals, and provides the control logic needed by low-port-count managed or unmanaged repeater systems. The DP83858 targets equipment that must extend Fast Ethernet connectivity across several ports without using eight separate external repeater controllers. The controller's defining features include support for as many as eight 100 Mb/s ports, 100 Mb/s TX/T4 operation, 5 V single-supply operation, and compatibility with the IEEE 802.3 repeater requirements identified in the manufacturer documentation. The 295 mA supply-current figure provides a basis for power budgeting, while the 132-PQFP mechanical format supports a substantial pin count for port-facing signals and control functions. The DP83858 belongs to the interface-controller category rather than a general-purpose transceiver. Its TX/T4 repeater architecture is intended for high-speed Ethernet systems and legacy Fast Ethernet infrastructure. Compared with a single-port PHY, the device concentrates repeater management and media-interface control for an eight-port system, reducing board-level component count while retaining a standardized networking architecture. Typical applications include managed Fast Ethernet switches, unmanaged low-port-count switches, Ethernet repeaters, industrial network concentrators, and legacy 100BASE-TX equipment. Installation requires careful PCB routing for high-speed differential pairs, solid supply decoupling, controlled return paths, and compliance with the manufacturer's recommended layout and termination practices. The main design trade-off is specialization: DP83858VF addresses multiport Fast Ethernet repeater control rather than modern multi-gigabit or single-port integrated PHYs. Legacy-system maintenance, industrial connectivity, and equipment replication are stronger reasons to select it than new high-bandwidth designs. This page consolidates the supplied manufacturer-related data, distributor listing, package information, and Ethernet application context. It also distinguishes verified specifications from parameters that require confirmation from the complete datasheet before schematic or PCB release.
DP83865BVH - 8/8 Gigabit Ethernet PHY | Texas Instruments
The Texas Instruments DP83865BVH is an 8/8 Gigabit Ethernet physical-layer transceiver with integrated support for 10BASE-T, 100BASE-TX, and 1000BASE-T operation, supplied in a surface-mount 128-pin PQFP package measuring 14 x 20 mm. Its verified operating supply information includes 1.8 V and 2.5/3.3 V rails, while its transceiver architecture connects an Ethernet MAC through a digital parallel interface to copper cabling. An Ethernet physical-layer transceiver, commonly called an Ethernet PHY, is the semiconductor layer that converts logical data transmitted by a network controller into electrical or optical signals suitable for a communications medium. Within the Ethernet hierarchy, a PHY sits below the MAC and above the physical medium. For copper Ethernet, the PHY handles encoding, signaling, clock recovery, link negotiation, and reception of data transmitted over twisted-pair cabling. The DP83865BVH is identified as an 8/8 transceiver, providing eight transmit and eight receive channels for parallel network-interface implementations. Verified source data identifies 10BASE-T and 100BASE-TX support and notes integrated PMD sublayers associated with 1000BASE-T operation. This makes the device relevant to multiport Ethernet switches, routers, network interface controllers, and industrial communication equipment requiring several copper ports. The 128-PQFP package is physically substantial compared with compact QFN Ethernet PHYs because it exposes a broad high-speed parallel interface, multiple PHY channels, supply rails, reference clocks, and copper-network connections. Its surface-mount construction supports automated assembly, but careful power-plane distribution, controlled clock routing, and high-speed signal-integrity management remain necessary in multi-channel Ethernet designs. Typical applications include 8-port Gigabit Ethernet switches, network interface cards, routers, industrial Ethernet equipment, and embedded communication systems. The 8/8 organization can reduce the number of discrete PHY devices required when several copper ports share one board, although system partitioning, thermal distribution, and magnetics selection must still be evaluated. For a new design, engineers should use the official Texas Instruments datasheet and pinout rather than assigning connections solely from generic Ethernet conventions. Verify every supply rail, transceiver channel, clock input, resistor network, magnetic-interface component, and exposed thermal or supply connection against that document before layout release. This page consolidates verified distributor specifications, package data, sourcing links, application context, and compatibility cautions. Its key information gain is the distinction between a true pin-to-pin replacement and a merely similar 8/8 Ethernet PHY, which prevents an electrically or mechanically invalid substitution.
DP83865DVH - 1G Ethernet PHY, 128-PQFP | Texas Instruments
The Texas Instruments DP83865DVH is a single-port Gigabit Ethernet physical-layer transceiver supporting 10BASE-T, 100BASE-TX, and 1000BASE-T in a 128-PQFP package measuring 14 x 20 mm. It operates from a 1.71 V to 1.89 V core supply and supports data rates through 1 Gbit/s. The commercial-temperature device is specified for 0 C to +70 C and has eight media-interface transmit or receive channels. An Ethernet PHY is the physical-layer component that converts digital Ethernet data supplied by a MAC into electrical signaling for a copper network, and receives analog signals from the cable. Within the Ethernet hierarchy, the PHY connects the digital MAC interface and the 10/100/1000BASE-T medium. This distinction matters because protocol handling remains above the PHY while the DP83865DVH performs line signaling, clock and data recovery, and physical-layer encoding functions. Verified source data identifies a 1 Gbit/s data rate, eight transceiver channels, a 1.71 V to 1.89 V supply range, approximately 430 mA supply current, and a 128-pin PQFP package. The device integrates physical medium-dependent sublayers required for 10BASE-T, 100BASE-TX, and 1000BASE-T Ethernet. Exact media-interface modes, clock tolerances, transceiver electrical limits, and pin-level functions are not present in the supplied search extracts and therefore require confirmation from the manufacturer datasheet before layout release. Typical implementation is a copper Gigabit Ethernet port in industrial controllers, embedded computers, test equipment, network interface cards, and communications hardware. The 128-PQFP footprint favors multilayer PCB routing and external magnetics rather than compact modules, while the 1.89 V maximum stated core supply requires a regulator with suitable headroom and power integrity. A network magnetics or integrated coupling arrangement is also required at the cable side, subject to the complete reference design. Engineers should preserve the exact interface voltage, termination, crystal or clock source, reset, and power-tree requirements given in the full DP83865 datasheet. Because no verified pricing schedule was supplied, unit prices remain marked as data needed rather than being inferred from generic distributor listings. The search data also indicates that no pin-to-pin DP83865 replacement is offered by TI, so substitution requires interface and PCB validation rather than an assumed footprint match. This page consolidates the verified distributor specifications, procurement sources, replacement evidence, and engineering cautions. It distinguishes confirmed electrical facts from unavailable details and avoids treating functionally similar PHYs as verified drop-in devices. That distinction is critical because Ethernet PHYs may use the same 128-pin package while differing in interface modes, strap behavior, clocking, register maps, and analog performance.
DP83867CSRGZR - Gigabit Ethernet PHY RGMII/SGMII | Texas Instruments
Texas Instruments DP83867CSRGZR is a robust, low-power, fully featured Gigabit Ethernet Physical Layer transceiver (PHY) supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols with RGMII and SGMII MAC interface options, packaged in a 48-pin VQFN (RGZ) 7x7 mm footprint. The device integrates the PMD sublayer and exceeds 8 kV IEC 61000-4-2 ESD (direct contact) immunity, targeting factory automation, motor drives, and other electrically harsh industrial environments. SGMII support enables seamless connection to MACs that lack parallel MII/GMII/RGMII pins, simplifying board routing on space-constrained designs. An Ethernet PHY (Physical Layer transceiver) is the analog front-end of an Ethernet link: it sits between the RJ45/magnetics on the line side and the MAC controller on the host side, performing PCS/PMA encoding, clock/data recovery, echo/ crosstalk cancellation, and link training. As a sub-class of network interface IC, the PHY falls under the broader hierarchy of networking ICs > interface ICs > integrated circuits. The DP83867CS series specifically targets the industrial Gigabit PHY niche where high ESD immunity, wide temperature support, and small form factor matter. Key features include configurable I/O voltage (3.3 V, 2.5 V, 1.8 V) for direct connection to FPGAs, SoCs, and ASICs of any logic family; ultra-low RGMII latency (TX < 90 ns, RX < 290 ns) which is essential for Time Sensitive Network (TSN) compliant systems; integrated cable diagnostics; and JTAG boundary scan support. The device ships in a 48-pin VQFN (RGZ) package with exposed thermal pad, and supports an extended industrial operating temperature range. The CS variant offers a low-power 457 mW typical operating power profile. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), human-machine interfaces (HMIs), motor and motion control, factory automation backbones, and embedded networking on single-board computers. The wide operating temperature range and ESD robustness also make it well suited to outdoor PoE end-points and ruggedized IoT gateways where commercial-grade PHYs would be unreliable. Designers should refer to the manufacturer datasheet for the recommended magnetics, RJ45 integration, and reference clock selection, and should follow the IBIS model for SI-validated board layout.
DP83867CSRGZT - Robust GbE PHY, RGMII/SGMII, VQFN-48 | TI
The Texas Instruments DP83867CSRGZT is a low-power, robust, fully-featured Gigabit Ethernet Physical Layer transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols, offered in a 48-pin VQFN (RGZ) 7x7 mm package. Key headlines: 10/100/1000 Mbps operation, RGMII and SGMII MAC interface options, configurable I/O voltage (3.3 V, 2.5 V, 1.8 V), and an industrial-grade 0 C to 70 C operating range with TI's high-immunity PHY core. An Ethernet PHY (Physical Layer transceiver) is the analog/digital mixed-signal device sitting between a Media Access Controller (MAC) and the magnetics/RJ45 connector on a copper Ethernet link. The PHY handles line encoding/decoding (PAM-5 for 1000BASE-T, MLT-3 for 100BASE-TX), link training, echo cancellation, and cross-talk mitigation across four twisted pairs, while presenting a parallel or serial digital interface to the MAC. As a Physical Layer transceiver within the seven-layer OSI model, the PHY is part of the wired networking interface layer, and a critical power-management and signal-integrity IC in any embedded Ethernet design. Key features include cable diagnostics, low RGMII latency (TX < 90 ns, RX < 290 ns), Time-Sensitive Network (TSN) compliance, fast link drop mode, JTAG 1149.1 boundary scan support, and integrated PMD sublayers. The DP83867CS provides high ESD/EMC immunity and an ultra-low RGMII latency profile. Compared to integration assemblers using lower-immunity PHYs, the CS variant offers enhanced robustness for noisy industrial environments. Architecturally, the device uses TI's proprietary DSP-based echo canceller and baseline wander corrector across all four pairs, with auto-negotiation and Auto-MDIX, allowing direct connection to either a straight-through or crossover cable. The SGMII option reduces MAC-to-PHY pin count to four differential signals, freeing board area in space-constrained designs. Typical applications include industrial Ethernet switches, factory automation controllers, motor drives with EtherCAT/PROFINET support, building automation, and any embedded system requiring a small-footprint, low-power gigabit copper interface. The wide temperature range and immunity rating make the part especially suitable for industrial Ethernet switches and PLCs. When designing with this device, pay careful attention to MDI trace routing (100-ohm differential, length-matched within the pair), magnetics selection, and decoupling on each supply pin. Reference the TI DP83867 design checklist for layout guidance, especially the four-pair MDI routing and chassis-ground separation.
DP83867E - Gigabit Ethernet PHY, RGMII/SGMII, 48-VQFN | TI
The Texas Instruments DP83867E is a robust, low-power, fully-featured 10/100/1000 Mbps Ethernet Physical Layer transceiver with integrated PMD sublayers, supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols, housed in a 48-pin VQFN (7x7 mm) package. The device delivers extra-low latency (TX < 90 ns, RX < 290 ns) and is offered in an industrial extended-temperature grade with SGMII and RGMII MAC interfaces. An Ethernet PHY (Physical Layer transceiver) is a mixed-signal IC that connects a MAC controller to the copper medium (twisted-pair cable), handling line encoding/decoding, link training, echo/next-crosstalk cancellation, and clock/data recovery across the MDI. The DP83867E sits at the bottom of the OSI physical layer, translating digital MAC frames into analog baseband signals on the cable. In the taxonomy: Ethernet PHY -> transceiver -> network interface IC -> communication semiconductor. The part exceeds 8 kV IEC 61000-4-2 ESD on the cable pins, making it a robust choice for industrial and automotive-grade Ethernet links. Key features include support for both RGMII and SGMII MAC interfaces, integrated 1.25 GHz SerDes for SGMII, low-power 1000BASE-T operation, programmable LED outputs, and a flexible MDIO/MDC management interface. The extended-temperature grade (-40C to +105C ambient with proper thermal design) targets industrial control, factory automation, and outdoor equipment where commercial-grade PHYs derate. Architecturally, the DP83867E uses a DSP-based echo and crosstalk canceller, an integrated 1000BASE-T PMA/PMD with on-chip termination, and a low-jitter PLL to recover the 125 MHz reference. The SGMII variant routes the recovered data over a 1.25 Gbps differential serial link, eliminating the 12-bit parallel RGMII bus and reducing board-layer routing complexity in space-constrained SoMs. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), factory-floor IO modules, motor drives, telecom base-station routers, and automotive Ethernet PHYs for in-vehicle networking. The SGMII interface in particular suits SoCs that place the PHY on a remote daughter card or that prefer serial MAC connectivity. Design consideration: the MDI traces require 100-ohm controlled differential impedance and an integrated magnetics RJ-45 with center-tap; the 1.0 V analog and 2.5/3.3 V digital rails must be cleanly decoupled to meet the IEEE 802.3 return-loss mask. Use the TI reference design checklist for BOM and stack-up. This page synthesizes distributor pricing, package-accurate cross-references, and practical PCB design notes that go beyond the manufacturer datasheet to accelerate your Ethernet hardware bring-up.
DP83867IRPAPT - Industrial GbE PHY, RGMII/GMII, 64-HTQFP | TI
The Texas Instruments DP83867IRPAPT is a robust, low-power, fully-featured gigabit Ethernet Physical Layer (PHY) transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T protocols, housed in a 64-pin HTQFP (PAP) 10x10 mm package. It delivers GMII, MII, and RGMII MAC interface support, an industrial temperature range of -40C to +85C, and ESD protection exceeding 8 kV IEC 61000-4-2 (direct contact). Full operating power is approximately 490 mW (PAP variant) and it includes cable diagnostics, IEEE 1588 Start of Frame Detection, and JTAG 1149.1 boundary scan. An Ethernet PHY (physical layer transceiver) is the lowest layer of the OSI model that converts digital MAC data into analog signaling for transmission over copper twisted-pair cable and recovers the analog signal at the receiving end. PHYs handle line coding (PAM-3 for 10BASE-Te, MLT-3 for 100BASE-TX, PAM-5 for 1000BASE-T), echo/next cancellation, equalization, and clock/data recovery. In the broader taxonomy, an Ethernet PHY is a type of network interface IC -> wired communication IC -> interface IC -> semiconductor. PHY choice (industrial temp, low latency, IEEE 1588 SOF) drives MAC selection, magnetics, and PCB stack-up decisions. The DP83867IRPAPT combines an integrated PHY with hardware timestamping (IEEE 1588 SOF), enabling sub-microsecond synchronization accuracy required by industrial Ethernet protocols such as EtherCAT, PROFINET, and TSN. The device supports both RGMII and GMII for flexible MAC attachment, including low-power mode down to approximately 230 mW (estimated from PAP data) when link is established. Cable diagnostics (TDR-based) detect open/short distance and polarity on each twisted pair, simplifying field installation. Typical applications include industrial Ethernet switches, programmable logic controllers (PLCs), industrial sensors and drives, factory automation gateways, and any embedded system requiring reliable GbE connectivity in harsh EMI/noisy environments. The industrial temperature rating and high ESD immunity make it well suited to factory floor equipment, motor drives, and outdoor installations where commercial-grade PHYs would fail. When designing in this part, allocate sufficient PCB area for the 64-HTQFP thermal pad and follow TI's reference layout for the magnetic interface. Use a 25 MHz reference clock or rely on the integrated 25 MHz crystal oscillator, and add proper decoupling (0.1 uF + 10 uF) near each supply pin to meet EMI/ESD margins. This page synthesizes distributor pricing, drop-in alternatives (same-brand first, then cross-brand), and practical PCB/thermal design notes not collected in any single distributor listing or in the manufacturer datasheet alone.
DP83867IRRGZ - Industrial GbE PHY, RGMII/SGMII, VQFN-48 | Texas Instruments
The Texas Instruments DP83867IRRGZ is a robust, low-power, fully featured Gigabit Ethernet physical layer (PHY) transceiver with integrated PMD sublayers supporting 10BASE-Te, 100BASE-TX, and 1000BASE-T over twisted-pair copper, housed in a 48-pin VQFN (RGZ) 7x7 mm package with exposed thermal pad. It features MAC interfaces of RGMII and SGMII, an industrial temperature range of -40C to +85C, and ESD protection that exceeds 8 kV IEC 61000-4-2 on the cable-side pins. The device targets harsh industrial Ethernet applications where EMI immunity, extended temperature, and long cable reach are required. An Ethernet PHY (Physical Layer transceiver) sits at layer 1 of the OSI model and converts digital MAC-side data into the analog differential signaling required by 10/100/1000BASE-T, while handling line coding, link training, echo/ crosstalk cancellation, and clock/data recovery. PHYs connect directly to an Ethernet MAC inside a switch controller, FPGA, SoC, or MCU, making them the physical bridge between the digital host and the RJ45/Magnetics front end. The DP83867 family belongs to the industrial-grade GbE PHY category, sitting above commercial-temperature PHY ICs and below automotive-qualified variants such as the DP83867IRRGZ-Q1. Key features include sub-1.5 W typical power consumption at gigabit speeds, integrated termination resistors, programmable LED drivers, IEEE 1588/SOF timestamping support, cable diagnostics (TDR), and a 25 MHz reference clock input. The RGMII/SGMII MAC interface gives the designer flexibility to bridge to either an FPGA/SoC with parallel RGMII pins or a serdes-based MAC with differential SGMII signaling. The wide 1.1 V / 2.5 V / 3.3 V supply rails simplify integration with mixed-voltage hosts, while the 8 kV ESD rating eliminates the need for external TVS arrays on the MDI pins in many designs. The internal architecture combines a DSP-based echo canceller and crosstalk canceller with an analog front-end optimized for 1000BASE-T PAM-5 signaling over 100 m of Cat5e/Cat6 cable. Auto-negotiation and Auto-MDIX streamline bring-up, while Energy-Efficient Ethernet (EEE) reduces idle power. Hardware diagnostics including cable length estimation and open/short detection assist field commissioning and predictive maintenance. Typical applications include industrial Ethernet switches, PLC communication modules, motor-control and servo-drive feedback links, factory-floor sensor backbones, ruggedized PoE PD/PoE+ powered devices, and embedded gateways that need deterministic GbE connectivity. The industrial temperature rating makes the part a standard choice for IEC 61131-2 / IEC 61850 environments. When designing with this PHY, place the 25 MHz crystal/oscillator within 50 mm of the XI/XO pins and keep the MDI differential pairs length-matched within 2 mm and referenced to a continuous ground plane. Add a 1 nF HV decoupling cap on each MDI center-tap and follow the reference schematic in the DP83867 datasheet for the RJ45 magnetics to pass IEEE conformance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, accelerating PHY selection and PCB bring-up.
DP83869HMRGZR - High-Immunity Gigabit Ethernet PHY | TI
The Texas Instruments DP83869HMRGZR is an extended-temperature, high-immunity gigabit Ethernet PHY transceiver with integrated PMD sublayers, supplied in a 48-pin VQFN (RGZ) 7x7 mm package. It supports 10BASE-Te, 100BASE-TX, and 1000BASE-T copper protocols along with 1000BASE-X and 100BASE-FX fiber interfaces, operating from a 1.8V/2.5V/3.3V supply rail. An Ethernet PHY (Physical Layer transceiver) is the interface IC that connects a MAC (Media Access Controller) to the physical copper or fiber cable, handling line coding, link training, echo/return-loss compensation, and clock/data serialization. As part of the Physical Layer transceiver -> Ethernet transceiver -> Network Interface IC -> Power Management/Connectivity IC hierarchy, gigabit PHYs sit one layer below the MAC and one layer above the magnetics/RJ-45 (or SFP fiber cage), translating MII/GMII/RGMII parallel data into differential serial signals compliant with IEEE 802.3 10/100/1000BASE-T. Key features of the DP83869HMRGZR include: IEEE 802.3 10/100/1000 Mbps operation, integrated PMD sublayers for copper and fiber, RGMII/MII/GMII MAC interfaces, media-conversion between copper and fiber ports, AEC-Q100-qualified extended-temperature grade (-40C to +125C), low-latency cut-through mode, and 8 kV IEC 61000-4-2 ESD protection (direct contact). The 48-pin VQFN (RGZ) package exposes a thermal pad for heat dissipation and supports reflow soldering on standard industrial PCB processes. Architecturally, the DP83869HMRGZR integrates the entire physical coding sublayer (PCS), physical medium attachment (PMA), and physical medium dependent (PMD) blocks on-chip, eliminating the need for external PHY magnetics tuning circuits. The device supports both SGMI and RGMII host interfaces with selectable timing modes, and includes integrated termination resistors that simplify the BOM. Cable diagnostics, loopback modes, and jumbo-frame support extend its utility in industrial Ethernet switches. Typical applications include industrial Ethernet switches, factory automation controllers, motor-drive communication boards, 5G small-cell fronthaul, automotive Ethernet gateways, and fiber-to-copper media converters. The wide temperature and high immunity make it well suited for IEC 61000-4 industrial EMC environments where standard PHYs would fail conformance. When designing with this part, ensure the MDI traces are 100-ohm differential with controlled 50-ohm single-ended impedance, place the 1.8V/2.5V/3.3V decoupling capacitors within 2 mm of each supply pin, and use a 4-layer PCB with a continuous ground plane below the PHY to meet IEEE 802.3 return-loss masks. This page synthesizes distributor pricing, drop-in TI same-family alternatives, design notes, and an honest comparison against cross-brand gigabit PHYs - content not aggregated on any single manufacturer or distributor page.
DP83901AV - 5V Serial Network Controller | Texas Instruments
The Texas Instruments DP83901AV is a 5 V serial network interface controller, or SNIC, with 110 mA typical supply current in a 68-pin PLCC J-lead package measuring 25.13 mm by 25.13 mm. Designed for CSMA/CD local-area networks, the device supports Ethernet 10BASE5, Thin Ethernet 10BASE2, and twisted-pair Ethernet 10BASE-T implementations. A serial network interface controller is a semiconductor that coordinates data exchange between a host computer and an Ethernet physical layer. Within the network-interface hierarchy, it sits between host hardware or software drivers and a network-medium transceiver. The DP83901AV consolidates functions required to manage Ethernet packet transfer, addressing, access, and station communication while operating from a single 5 V supply. The verified source material identifies the DP83901AV as a microCMOS VLSI controller with a serial interface, 7 pF typical input capacitance, and 7 pF typical output capacitance under the stated test conditions. Its nominal 110 mA supply current makes board-level power planning important in systems that operate continuously. Commercial temperature grade and tray packaging are also identified in the verified component listings. Because the part targets legacy Ethernet standards, its strongest design roles are 10BASE5, 10BASE2, and 10BASE-T network-interface designs rather than modern switched Gigabit Ethernet equipment. A host processor must provide the required bus, interrupt, memory, and network-driver environment. Designers should also preserve the exact timing, signal-conditioning, and pin functions documented for this legacy controller. Typical implementation choices include industrial data acquisition, embedded test systems, service equipment, and legacy Ethernet adapters that require 10BASE-T connectivity. The controller can be paired with suitable transceivers, magnetics, isolation, clocks, and termination networks, but the external network interface must be selected independently because the verified data does not identify one specific companion-device BOM. The primary design consideration is availability and lifecycle validation. This is a mature Ethernet controller, so procurement should confirm current supply, manufacturer status, and traceability before a new design is released. Existing products should preserve the original schematic, timing, and firmware assumptions unless a replacement has been independently qualified. This page consolidates the verified package, supply, interface, and Ethernet data while separating unavailable specifications from established facts. It also records the lack of a verified drop-in replacement rather than presenting a functionally similar controller as a safe PCB substitute.
DP83907VF - 10Base-T Ethernet NIC Controller ISA Interface | TI
The Texas Instruments DP83907VF (AT/LANTIC II) is a single-chip CMOS VLSI 10Base-T Ethernet Network Interface Controller (NIC) with integrated ISA bus interface, delivered in a 132-pin BQFP (PQFP) package. It supports a single 10 Mb/s twisted-pair or coaxial channel, operates from a single 5V supply (4.75 V to 5.25 V) drawing approximately 150 mA, and is qualified to the commercial temperature range. What is an Ethernet NIC controller? A NIC controller is an integrated circuit that bridges a host processor's parallel bus (such as ISA, PCI, or PCIe) to a Media Access Control layer that implements the CSMA/CD protocol used by IEEE 802.3 Ethernet. The DP83907 sits in the hierarchy: 10Base-T PHY → Ethernet MAC → NIC controller → host bus controller → PC motherboard. By integrating the entire PC-AT ISA bus interface along with the MAC and 10 Mb/s physical front-end, the DP83907 reduces discrete component count and lets designers add a 10 Mb/s LAN port with minimal glue logic. Key features of the DP83907VF include on-chip Manchester encoder/decoder for 10Base-T, integrated 10Base-T transceiver (twisted-pair), built-in attachment unit interface (AUI) for external MAU support, full ISA (Industry Standard Architecture) 8/16-bit bus mastering DMA engine, and configurable I/O and memory mapped modes. The device offers a 2-channel CSMA/CD link, supporting 1.25 MBps raw throughput on the serial side. CMOS process technology keeps power dissipation under 1W typical. Architecturally, the DP83907VF partitions cleanly into a bus interface unit, a CSMA/CD MAC engine, a Manchester ENDEC, and a 10Base-T analog front end. The MAC performs framing, CRC-32 generation/checking, collision detection, and back-off timing, while the analog front-end provides transmit waveshaping and receive equalization for 100-meter Category-3 cable runs. The combination targets PC-AT/PC/XT motherboards, ISA add-in cards, embedded LAN adapters, and industrial 10 Mb/s backbones. Typical applications include ISA-bus Ethernet NIC add-in cards, factory-floor 10Base-T bridges, industrial automation controllers with embedded LAN ports, legacy PC motherboard LAN-on-board designs, and 10 Mb/s repeaters/hubs requiring a host-managed controller. Because the part integrates the AUI option, it can also drive an external 10Base2 (BNC) transceiver for coax-based legacy LANs. When designing with the DP83907VF, plan ISA bus arbitration because bus-master DMA requires care to coexist with other bus masters. Add 4.7 kΩ pull-ups on configured strap inputs (IRQ, I/O base address) and keep the analog ground (AGND) and digital ground (DGND) separated under the package, joining them only at the PCB main ground plane to preserve 10Base-T jitter margins. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.
DP8390DV - 10 Mbps 5 V Ethernet NIC | Texas Instruments
The Texas Instruments DP8390DV is a 10 Mbps, 5 V Ethernet network interface controller supplied in a 68-pin PLCC package measuring 25.13 mm by 25.13 mm. It is designed to interface host systems with CSMA/CD local-area networks, including Ethernet Thin implementations, while presenting a dedicated network-controller function rather than requiring the host processor to manage the physical network medium directly. The verified distributor listing identifies the device as an Ethernet controller interface and describes its 68-PLCC construction. What is an Ethernet network interface controller? An Ethernet NIC is an interface IC positioned between a computer or embedded controller and an Ethernet physical layer. It handles network-oriented communication tasks and reduces the electrical and protocol burden placed on the host system. In the broader semiconductor hierarchy, the DP8390DV is a communication interface controller, an interface IC, and ultimately a semiconductor used in Ethernet networking equipment and embedded data-processing systems. The DP8390DV’s primary verified characteristics include a 10 Mbps data rate, a 5 V supply, and approximately 40 mA supply current. Those values place it in the established 10BASE-T-era Ethernet hardware category. Its PLCC package provides a surface-mount PCB footprint with J-leads, while the listed 25.13 mm by 25.13 mm body size supports compact but not especially miniature industrial and legacy-compatible designs. DP8390D-family devices were designed to ease host interfacing with CSMA/CD local-area networks, including Ethernet Thin networks. The controller therefore belongs in systems where a host bus must communicate through an Ethernet-compatible network interface. Compared with a general-purpose interface IC, its defining value is Ethernet-specific integration: the network function is consolidated into a dedicated controller rather than being implemented entirely with host firmware and discrete logic. Typical uses include embedded Ethernet controllers, industrial data-acquisition systems, legacy terminal equipment, print servers, network-interface modules, and host adapters designed around the DP8390 family. In these applications, the DP8390DV can serve as the network-facing IC while an external transceiver, magnetic interface, connector, and system controller provide the surrounding physical-layer and host-side implementation. The principal design consideration is that this is a mature 10 Mbps controller rather than a current multi-gigabit Ethernet PHY or modern system-on-chip interface. Board design must follow the manufacturer pinout and required external components exactly. Signal routing, supply decoupling, thermal exposure, and network magnetics or transceiver selection should be validated against the official DP8390 documentation before layout release. This page consolidates verified distributor specifications, sourcing information, interface context, and application guidance. It does not invent unprovided pin assignments, timing values, temperature limits, or replacement parts, so unavailable engineering data remains explicitly marked rather than being inferred.
DP83910AN - CMOS Serial Network Interface 24-DIP | National Semiconductor
The National Semiconductor (Texas Instruments) DP83910AN is a CMOS Serial Network Interface (SNI) IC that provides Manchester data encoding and decoding for IEEE 802.3 Ethernet networks, supplied in a 24-pin DIP through-hole package (0.300 inch, 7.62 mm body width) and operating from a single 4.75 V to 5.25 V supply. The device is a direct-pin functional replacement for the legacy bipolar DP8391 SNI, integrating the physical-layer attachment functions required to interface an Ethernet transceiver (such as the DP8392 or DP839CT) to a controller or terminal-end Manchester encoder/decoder across 10 Mb/s Thin Ethernet (10BASE2/10BASE5) topologies. A Serial Network Interface (SNI) is a category of interface IC that sits between the Ethernet coaxial transceiver and the system controller, performing Manchester encoding, clock recovery, jabber monitoring, and link-integrity signalling per the IEEE 802.3 physical-layer specification. Within the broader hierarchy, the DP83910AN belongs to the network interface IC family, which falls under interface ICs, then integrated circuits, then semiconductors, providing OSI layer-1 connectivity and isolating the host CPU from line-coding analogue details. Key features include 10 Mb/s Manchester encoding/decoding, integrated jabber detection and Link Test generation, CMOS low-power operation versus the original bipolar DP8391, and a wide supply tolerance of 4.75 V to 5.25 V. The 24-DIP through-hole package supports easy insertion into legacy Ethernet adapter boards and industrial retrofit designs, while the CMOS process reduces typical operating current compared to its bipolar predecessor. The device also provides collision-detection and carrier-sense signalling flags that flow into the upper-layer MAC controller. Architecturally, the DP83910AN combines a phase-locked loop (PLL) for receive clock recovery, a 10 MHz oscillator interface, transmit clock-generation logic, and differential Manchester encode/decode blocks. Because the silicon is a drop-in CMOS replacement for the DP8391, existing schematic layouts can accept the DP83910AN without board rework, a critical advantage for legacy industrial networks and instrumentation that depend on the older part. Typical applications include 10BASE2 / 10BASE5 Ethernet adapter cards, industrial SCADA controllers, legacy factory-floor networking interfaces, and embedded instrumentation that must communicate over IEEE 802.3 media. The DP83910AN is also commonly used by restoration projects for early-1990s networking hardware and by test equipment vendors supporting IEEE 802.3 physical-layer compliance. When designing with this device, note that the DP83910AN is now in obsolete/EOL lifecycle, so long-term sourcing requires attention to authorized distributor stock and the qualified cross-references listed in the alternatives section. Decoupling with 0.1 uF ceramic capacitors close to VCC/GND pins is essential for the integrated PLL to maintain stable clock recovery under varying line loading. This page synthesizes distributor pricing from DigiKey and Win Source, drops-in cross-reference data, lifecycle risk analysis, and Pin Configuration design notes that go beyond what the original manufacturer datasheet provides as of October 22, 2026.
DP83910AV - CMOS SNI Ethernet Interface | Texas Instruments
The Texas Instruments DP83910AV is a CMOS Serial Network Interface (SNI) integrated circuit with a 28-PLCC J-lead package. The supplied distributor data identifies it as an Ethernet network interface operating from a 4.75 V to 5.25 V supply and supporting a commercial temperature grade of 0 C to 70 C. The DP83910A family provides Manchester data encoding and decoding functions for IEEE 802.3 Ethernet Thin Ethernet local-area networks and is described as a direct-pin equivalent of the bipolar DP8391 SNI. A Serial Network Interface is an interface integrated circuit that converts between a host-side digital data stream and the physical signaling required by a legacy Ethernet network. In the product hierarchy, SNI belongs to network interfaces, then interface ICs, then integrated circuits. Manchester encoding represents each data bit through a transition pattern, allowing the receiver to recover both the bit value and clock information from the serial waveform. This device is therefore intended for systems requiring legacy Ethernet-compatible Manchester encoding and decoding rather than a modern integrated PHY/MAC solution. The DP83910AV is specified as a 28-pin PLCC device, with the AV suffix identifying the supplied package/orderable configuration. Its 4.75 V to 5.25 V operating range is characteristic of a 5 V legacy interface implementation. Distributor listings classify the device as an Ethernet Network Interface IC, while the manufacturer-related datasheet description identifies it as a CMOS SNI Serial Network Interface. The available source data does not provide verified values for clock rate, current consumption, output timing, logic levels, or internal transceiver details. Typical engineering uses include legacy Thin Ethernet network nodes, industrial data-collection equipment, embedded test systems, and retrofits requiring compatibility with existing Manchester-encoded Ethernet hardware. In such systems, the DP83910AV can perform the Manchester encoding or decoding stage at the boundary between digital logic and the network interface. The 28-PLCC package is a legacy surface-mount format requiring a matching footprint, adequate routing clearance, and careful examination of pin orientation and thermal performance. For new designs, verify that the required legacy network architecture, voltage, timing, connector, and isolation requirements match the device. Obsolete or NRND legacy Ethernet components should be sourced only after confirming documentation, traceability, and long-term availability. The available distributor result reports 6,224 pieces in stock and a unit price of $9.5471, but price and availability should be reconfirmed at the time of purchase. This page combines verified distributor descriptions, lifecycle information, package data, and engineering-use guidance. It does not infer unprovided electrical limits or claim a substitute part where pin-level and parametric equivalence has not been established.
DP8392CN-1 - IEEE 802.3 Coaxial Transceiver | Texas Instruments
The Texas Instruments DP8392CN-1 is an IEEE 802.3 coaxial transceiver interface with 16 through-hole DIP terminals, a nominal -9 V supply, and a commercial operating-temperature grade of 0°C to 70°C. It is designed to connect a coaxial Ethernet physical-layer cable to data-terminal equipment through transmit and receive signal paths. The verified listing identifies the device as a CTI, or Coaxial Transceiver Interface, and classifies it as an Ethernet transceiver rather than a general-purpose transceiver. Its legacy application is Thin Ethernet, or 10BASE-2, where the transceiver connects a station or network node to a coaxial bus. A coaxial transceiver interface is an interface IC that integrates the electrical functions needed to communicate over a shielded coaxial cable. In the broader networking hierarchy, it belongs to the network-interface and communications-semiconductor categories, where a physical-layer transceiver works alongside a network controller or system data bus. The DP8392CN-1 is therefore most useful when maintaining, repairing, or reproducing a legacy 10BASE-2 Ethernet design rather than designing a new modern Ethernet system. Its 16-DIP package favors through-hole construction and serviceable legacy equipment. Key verified attributes include the 16-terminal rectangular DIP package, through-hole terminal form, nominal -9 V negative supply, commercial temperature grade, and a listed 19.305 mm length. The device is identified as suitable for Ethernet transceiver applications and supports the coaxial cable line-driver and receiver function. The verified data does not provide output impedance, propagation delay, receiver sensitivity, isolation voltage, or detailed timing values, so those parameters should not be inferred from the product family without an applicable manufacturer document. Typical applications include legacy Thin Ethernet terminal adapters, coaxial network-interface cards, industrial or communications equipment retaining a 10BASE-2 port, and repair or restoration of older Ethernet hardware. The -9 V supply requirement must be checked against the surrounding circuit; it is not a modern 3.3 V or 5 V plug-in-compatible rail. The 16-pin through-hole footprint also requires mechanical and pin-level verification before replacement. The most important design consideration is that a coaxial transceiver is not interchangeable with every Ethernet transceiver having the same network function. Confirm the exact pinout, supply polarity, cable termination, connector type, and signal-level requirements in the applicable datasheet before layout or schematic changes. For new designs, verify that the legacy 10BASE-2 requirement is intentional; modern 10/100/1000 Ethernet generally uses different physical-layer devices. This page combines the verified distributor and manufacturer-source identification with package, application, and sourcing context. It distinguishes confirmed DP8392CN-1 facts from parameters that remain unavailable, rather than filling gaps with assumptions or unsupported substitutions.