ADC1213S080HN-C18 - 12-Bit 80MSPS Single-Channel ADC | Renesas
MPN: ADC1213S080HN-C18 ✓ نشطADC1213S080HN-C18 نظرة عامة
An ADC (Analog-to-Digital Converter) is a mixed-signal data-converter IC that samples a continuous-time analog waveform and produces a discrete-time binary code. It belongs to the SAR/pipeline family of Nyquist-rate converters, sits under the broader hierarchy of data converters -> mixed-signal ICs -> integrated circuits -> semiconductors, and is governed by interface standards such as JESD204A for high-speed serial transport to an FPGA or ASIC. Compared with lower-speed ADCs (10-40 MSPS), 80 MSPS parts are commonly used to digitise wideband IF signals in software-defined radio and LTE/4G base-station receivers.
Key specifications include 12-bit native resolution, 80 MSPS maximum sampling rate, JESD204A serial output, 1.8V analog and digital supplies, differential analog input with on-chip buffer option, 1 GHz analog input bandwidth, 70 dB SNR (typical, near-Nyquist), and SFDR around 78 dBc. A power-down mode and SPI control port further ease system integration. The HVQFN-32 package with exposed thermal pad keeps PCB footprint small and provides a low thermal resistance path for the 130 mW typical dissipation.
Architecture is a multi-stage pipeline with proprietary front-end sample-and-hold, on-chip reference, and digital error-correction logic that produces a clean 12-bit output. Built-in JESD204A link-layer hardware transmits one lane of 8b/10b-encoded samples at the JESD204A line rate, eliminating external FPGA LVDS deskew circuitry and simplifying board layout. The C18 ordering code designates the tape-and-reel 1k reel option for the 80 MSPS speed grade.
Typical applications include LTE/4G base-station receivers, software-defined radio (SDR) front-ends, medical ultrasound beamformers, radar and LIDAR digitiser channels, and industrial test & measurement. The wide analog input bandwidth and low jitter sample clock make it a strong fit for any 5 MHz-40 MHz IF strip that must be brought into a DSP / FPGA for further processing.
When designing with this part, place a clean 1.8V LDO (e.g. a low-noise TPS7A family member) close to the AVDD pin, decouple every supply pin with 100 nF X7R + 1 uF X5R pairs, route the analog input as a 100 ohm differential pair, keep the SYSREF and CLKP/CLKN lines length-matched, and verify the JESD204A link using the Renesas reference GUI before locking the FPGA fabric. The C18 reel suffix is purely logistic and has no effect on the silicon or performance. This page synthesises distributor pricing, drop-in pin-compatible alternatives, and practical layout notes not collected in a single place on the Renesas product page.
بدائل مباشرة لـ ADC1213S080HN-C18 — نفس الحزمة، متوافق دبوس بدبوس. تُستثنى القطع ذات الحزم المختلفة التي تتطلب تعديل PCB.
الطرازات في هذه السلسلة
طرازات من نفس السلسلة متوافقة تمامًا مع ADC1213S080HN-C18 (نفس عامل الشكل والبصمة) — يختلف في Package, Resolution, Operating Temperature, Input Type, Configuration Interface.
ADC1213S080HN/C1:5
✅ بديل مباشر📋 بديل مرجعي (غير موجود في الكتالوج)
ADC1213D080HN/C1:5
✅ بديل مباشر📋 بديل مرجعي (غير موجود في الكتالوج)
ADC1010S080HN/C1:5
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←ADC1210S065HN/C1
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←ADC1012D080HN/C1:5
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←ADC1213S080HN-C18 الحدود القصوى والخصائص الكهربائية
| الدقة | 12 bits |
| Number of Channels | 1 |
| Maximum Sample Rate | 80 MSPS |
| Output Interface | Serial JESD204A (1 lane) |
| Analog Supply Voltage (AVDD) | 1.8 V |
| Digital / IO Supply (OVDD) | 1.8 V to 3.3 V |
| Analog Input Type | Differential, on-chip buffer |
| Analog Input Bandwidth | 1 GHz |
| SNR (typical, fIN near Nyquist) | 70 dBFS |
| SFDR (typical) | 78 dBc |
| Power Dissipation (typical, 80 MSPS) | 130 mW |
| Power-Down Mode | Yes (SPI-controlled) |
| Configuration Interface | SPI / serial control |
| العلبة | HVQFN-32 (5x5 mm) with exposed thermal pad |
| نوع التركيب | Surface Mount |
| درجة حرارة التشغيل | -40 C to +85 C |
| مستوى MSL | 3 |
| حالة RoHS | Compliant |
تكوين أطراف ADC1213S080HN-C18
| دبوس 1 | AVDD — 1.8V analog supply |
| دبوس 2 | AVDD — 1.8V analog supply |
| دبوس 3 | VCM — Common-mode voltage output |
| دبوس 4 | VINP — Differential analog input (positive) |
| دبوس 5 | VINN — Differential analog input (negative) |
| دبوس 6 | CLKP — Differential sample clock (positive) |
| دبوس 7 | CLKN — Differential sample clock (negative) |
| دبوس 8 | GND — Ground |
| دبوس 9 | OVDD — 1.8V-3.3V digital IO supply |
| دبوس 10 | SCLK — SPI clock for configuration |
| دبوس 11 | CSB — SPI chip select (active low) |
| دبوس 12 | SDIO — SPI serial data I/O |
| دبوس 13 | RESETB — Hardware reset (active low) |
| دبوس 14 | PDN — Power-down input |
| دبوس 15 | GND — Ground |
| دبوس 16 | DRVDD — 1.8V supply for digital output drivers |
| دبوس 17 | GND — Ground |
| دبوس 18 | NC — Not connected (per datasheet) |
| دبوس 19 | NC — Not connected (per datasheet) |
| دبوس 20 | GND — Ground |
| دبوس 21 | AVDD — 1.8V analog supply |
| دبوس 22 | AVDD — 1.8V analog supply |
| دبوس 23 | GND — Ground |
| دبوس 24 | VREF — External reference bypass |
| دبوس 25 | FSADJ — Full-scale adjustment pin |
| دبوس 26 | GND — Ground |
| دبوس 27 | NC — Not connected (per datasheet) |
| دبوس 28 | SYNCB — JESD204A synchronization request |
| دبوس 29 | DA0P — JESD204A serial data lane 0 (positive) |
| دبوس 30 | DA0N — JESD204A serial data lane 0 (negative) |
| دبوس 31 | DRVDD — 1.8V supply for digital output drivers |
| دبوس 32 | EP — Exposed thermal pad - tie to analog ground plane |
التطبيقات النموذجية
ADC1213S080HN-C18 مناسب لـ 6 التطبيقs: LTE / 4G Base-Station Receiver IF Digitiser, Software-Defined Radio (SDR) Front-End, Medical Ultrasound Beamformer Receive Path, Industrial Test & Measurement (Oscilloscope / DAQ), Radar / LIDAR Pulse Digitiser, Communications Baseband Signal Processing.
LTE / 4G Base-Station Receiver IF Digitiser
The ADC1213S080HN-C18's 80 MSPS sample rate and 1 GHz analog input bandwidth make it a strong fit for LTE/4G base-station receiver IF strips digitising 5-40 MHz intermediate frequencies. Its 70 dBFS SNR plus SFDR around 78 dBc preserves EVM on the recovered QAM constellation, which is critical for meeting 3GPP spectral mask and ACLR limits. The JESD204A output streams directly into a baseband FPGA such as a Xilinx 7-Series, eliminating parallel LVDS routing. Place a low-jitter clock on CLKP/CLKN and route the analog input as a 100 ohm differential pair with length matching within 5 mil.
موصى به
Software-Defined Radio (SDR) Front-End
In software-defined radio platforms the ADC sits between the analog tuner and the FPGA DSP fabric, and the ADC1213S080HN-C18 handles this with 12-bit / 80 MSPS performance plus a 1 GHz analog input bandwidth that subsumes most HF/VHF/UHF IF chains. The 78 dBc SFDR prevents strong-signal spurs from masking weak adjacent channels, and the SPI-controlled power-down mode lets portable SDR dongles enter a sub-5 mW sleep state between bursts. Pair the ADC1213S080HN-C18 with a Xilinx Zynq-7020 SoC that has a native JESD204A IP core, and feed the analog input from a wideband LNA + anti-alias filter.
موصى به
Medical Ultrasound Beamformer Receive Path
Portable ultrasound carts and point-of-care probes digitise 64-256 receive channels at IF frequencies of 5-15 MHz, and the ADC1213S080HN-C18's 80 MSPS / 12-bit combination is well matched to this requirement, especially when per-channel power must stay under 200 mW. The 130 mW typical dissipation of this part (at 80 MSPS, 1.8V supplies) leaves thermal headroom in dense probe-head assemblies. Its 1 GHz analog input bandwidth preserves harmonics of Doppler-shifted returns, and the JESD204A output minimises the cable pin count between the probe head and the cart FPGA.
موصى به
Industrial Test & Measurement (Oscilloscope / DAQ)
Wide-bandwidth bench oscilloscopes, dynamic signal analysers and high-speed DAQ cards rely on 12-bit ADCs to maintain 70+ dB dynamic range while still capturing fast transients. The ADC1213S080HN-C18, with 1 GHz analog input bandwidth and SFDR around 78 dBc, fits mid-tier digitiser cards sampling at 80 MSPS across 4-8 channels. Its small HVQFN-32 package and SPI configuration port let designers place the ADC close to the analog front-end with a minimal 100 ohm differential backplane, which is critical at 100 MHz+ analog frequencies. The exposed thermal pad also provides a low theta-JA path on a 4-layer FR-4 board.
موصى به
Radar / LIDAR Pulse Digitiser
Automotive and industrial radar front-ends, plus short-range LIDAR receivers, sample baseband or IF return pulses with 12-bit resolution to detect target range and velocity. The ADC1213S080HN-C18's 1 GHz analog input bandwidth lets it directly digitise baseband returns without an extra anti-alias LPF, and its 80 MSPS rate captures chirp profiles up to 40 MHz instantaneous bandwidth. The on-chip differential input buffer and on-chip reference simplify the bill of materials, and the JESD204A output feeds a Spartan-6 / 7-Series FPGA for FFT-based detection. The 130 mW typical power keeps thermal load in outdoor IP-rated enclosures manageable.
موصى به
Communications Baseband Signal Processing
Beyond IF sampling, the ADC1213S080HN-C18 is used in cable-modem termination systems (CMTS) and software-modem cards that digitise upstream and downstream QAM carriers. Its 78 dBc SFDR prevents adjacent-channel leakage from degrading MER, while the 1.8V analog supply lets the card share a common power tree with adjacent SerDes and DSP. The SPI configuration port allows software to re-program gain, sample phase and JESD204A lane assignments at runtime, which is essential in adaptive line-card designs where the host controller tunes the receiver per-port. The HVQFN-32 footprint is also drop-in compatible with the lower-power ADC1210S065HN/C1 when a re-spin is needed for power reduction.
موصى به
ملخص المنتجات الموصى بها
بيانات مرجعية هندسية لـ ADC1213S080HN-C18 — المقارنة وإرشادات التصميم ومعلومات الامتثال.
دليل الاختيار
المقارنة مع البدائل
| المعامل | هذا المنتج | ADC1213S080HN/C1:5 | ADC1213D080HN/C1:5 | ADC1010S080HN/C1:5 | ADC1210S065HN/C1 | ADC1012D080HN/C1:5 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | HVQFN-32 (5x5 mm) | HVQFN-32 (5x5 mm) - same | HVQFN-48 - different | HVQFN-32 (5x5 mm) - same | HVQFN-32 (5x5 mm) - same | HVQFN-48 - different |
| Resolution | 12 bits | 12 bits | 12 bits | 10 bits | 12 bits | 10 bits |
| Sample Rate | 80 MSPS | 80 MSPS | 80 MSPS | 80 MSPS | 65 MSPS | 80 MSPS |
| Number of Channels | 1 | 1 | 2 | 1 | 1 | 2 |
| Output Interface | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A |
| Analog Supply | 1.8V | 1.8V | 1.8V | 1.8V | 1.8V | 1.8V |
| Power Dissipation | 130 mW (typ @ 80 MSPS) | 130 mW | 240 mW (dual) | 110 mW | 90 mW | 200 mW (dual) |
| Pin-Compatible (same footprint) | HVQFN-32 baseline | Yes (identical silicon, different reel code) | No (HVQFN-48, dual channel) | Yes (same HVQFN-32 footprint) | Yes (same HVQFN-32 footprint) | No (HVQFN-48, dual channel) |
أبرز الفروقات
- 12-bit resolution with JESD204A serializer at 80 MSPS in a compact HVQFN-32 (مقابلADC1010S080HN/C1:5)
- Single JESD204A lane with on-chip 1 GHz analog input buffer (مقابلADC1213D080HN/C1:5 (dual-channel HVQFN-48))
- C18 reel code is the default 1k-piece tape-and-reel (مقابلADC1213S080HN/C1:5 (100-piece 7-inch reel))
- 80 MSPS speed grade with documented wideband AC linearity (مقابلADC1210S065HN/C1 (65 MSPS, lower power))
ملاحظات التصميم
Power the ADC1213S080HN-C18 from a low-noise 1.8V LDO such as a TPS7A4700 on AVDD, and a separate 1.8V-3.3V rail on OVDD. Decouple every supply pin (AVDD, DRVDD, OVDD) with a 100 nF X7R ceramic within 2 mm of the pin plus a 1 uF X5R bulk capacitor. Keep the analog and digital ground planes separated under the ADC and stitch them together only at the exposed thermal pad (EP). Estimated: at 80 MSPS, total current draw is around 72 mA from AVDD; the LDO must source at least 100 mA with < 10 uVrms noise to preserve SNR.
Route VINP/VINN as a 100 ohm differential pair from the analog front-end to the ADC input pins, with length matching within 5 mil and no vias. Keep the CLKP/CLKN clock lines length matched within 2 mil, route them on an inner layer with continuous reference ground, and source the clock from a low-jitter oscillator (< 200 fs RMS jitter). Keep the JESD204A DA0P/DA0N output lane length matched to the FPGA receiver, with characteristic 100 ohm impedance and no stubs.
Place a 2nd-order anti-alias low-pass filter between the analog front-end and the ADC1213S080HN-C18 with cut-off around 40 MHz (1/2 of the sample rate plus guard band). Use an impedance-matched differential active filter with 100 ohm termination, or a passive LC if the source can drive 50 ohm single-ended loads. Verify SFDR with a -1 dBFS two-tone test before locking the PCB layout, because the SFDR around 78 dBc is sensitive to the analog input common-mode voltage on VCM.
Do not use the same LDO to power the ADC and any high-current switching converter; the 130 mW of ADC power plus switching noise will couple through the LDO and degrade SNR by 5-10 dB. Always drive CLKP/CLKN from a low-jitter source; phase noise above 1 MHz offset directly translates to ADC aperture jitter and reduces SNR. Ensure SPI configuration sequences match the Renesas reference GUI defaults, especially the JESD204A K-character and lane-0 assignment, before the FPGA link is brought up.
معلومات الامتثال
RoHS and REACH compliance per Renesas product page. Not AEC-Q100 qualified - this part is intended for industrial / commercial / communications use; for automotive radar designs choose an AEC-Q100 qualified ADC such as the ADC12QJ2000 family.
