74LVC1G123DC: Nexperia Single Retriggerable Monostable Multivibrator — Specs, Design Guide, Alternatives and Sourcing (2026)

74LVC1G123DC Quick Answers: What It Is, Key Specs, and Availability

The 74LVC1G123DC is a Nexperia single retriggerable monostable multivibrator — a one-shot — in an 8-pin VSSOP (DC) package. It operates from 1.65 V to 5.5 V VCC, delivers a 5.3 ns typical propagation delay at 5 V, and sets output pulse width with an external REXT resistor and CEXT capacitor. Schmitt-trigger inputs on A and B, a totem-pole CMOS output, and Ioff partial-power-down backflow protection make it a direct fit for noisy industrial edges and mixed-voltage buses. XAIPART records 99,999 units in stock at MOQ 1, priced from $0.62 at qty 1 to $0.28 at qty 1000 (as of 2026-10-06), with lifecycle status active. Volume pricing and the full pin table live on the 74LVC1G123DC product page.

A monostable multivibrator holds one stable state and one temporary state: a valid trigger drives it into the temporary state for a programmed interval, after which it returns to stable. The 74LVC1G123DC belongs to the 74LVC (Low-Voltage CMOS) logic family and occupies the specialty-logic sub-category alongside multivibrators, Schmitt triggers, and buffers.

Three separate mechanisms control the output pulse. The first is external REXT/CEXT programming. The second is retriggering through the gated active-LOW A input or the active-HIGH B input, which extends a pulse already in progress. The third is a direct active-LOW CLEAR reset. Because VCC spans 1.8 V, 2.5 V, 3.3 V, and 5 V rails, the device bridges logic domains without external level shifters.

Every value above comes from the XAIPART verified product record; nothing is estimated. Two parameters carry the most design weight: the 1.65 V minimum VCC, which decides whether the part survives a low-voltage rail migration, and the 5.3 ns typical propagation delay at 5 V, which sets how fast a trigger or fault reaches downstream logic.

Takeaway: if your design needs a resettable, retriggerable one-shot that runs from a 1.65 V to 5.5 V rail and settles in single-digit nanoseconds, the 74LVC1G123DC covers it in an 8-pin surface-mount footprint available at MOQ 1.

How Do You Select and Design In the 74LVC1G123DC?

Selection reduces to four checks: supply rail, pulse-width range, trigger polarity and noise immunity, and power sequencing in multi-rail systems. Each maps to a verified parameter.

1. Match the supply rail first

VCC spans 1.65 V to 5.5 V, which covers 1.8 V, 2.5 V, 3.3 V, and 5 V logic. A 3.3 V microcontroller triggers the device directly, and the totem-pole CMOS output drives downstream CMOS without a translator. The XAIPART record also notes 5 V tolerance on the outputs when VCC is 3.3 V, which is what makes the part usable for legacy 5 V peripherals. Stay above the 1.65 V floor.

2. Program the pulse width with REXT and CEXT

Pulse width is externally programmed, not internally trimmed. Per Nexperia, the basic relation is t_w = R_EXT x C_EXT, with the timing network connected to pin 3 (1REXT/CEXT) and pin 5 (1CEXT). Because accuracy depends on the external components, choose a tight-tolerance resistor and a stable capacitor dielectric, then evaluate the timing window across the full -40 C to +125 C operating range. Retriggering on A or B extends a pulse in progress — the behavior that enables missing-pulse detection and watchdog windows.

3. Choose trigger polarity and reset behavior

Pin 2 (1A) responds to an active-LOW edge; pin 1 (1B) is the active-HIGH trigger input; pin 7 (CLEAR) is an active-LOW reset that terminates the pulse immediately. Hold CLEAR high for retriggerable operation. Pull CLEAR low to return the one-shot to its stable state on command — the standard method for aborting a watchdog window or forcing a known state at power-up. When the one-shot feeds an MCU reset line, the fixed-width pulse replaces a discrete RC reset network with a defined duration; a comparable pattern appears in the PIC16F628A-I/SO design guide for 8-bit controller systems.

4. Use Ioff protection on mixed-voltage buses

The Ioff circuitry disables the outputs during power-down, preventing damaging current backflow. On a board where the 74LVC1G123DC sits on a 3.3 V rail that shuts down while a 5 V bus stays live, that protection stops the live bus from driving current into the unpowered device. This parameter is what makes partial-power-down sequencing safe instead of risky.

5. Let the Schmitt inputs handle slow and noisy edges

Both trigger inputs are Schmitt-trigger type, with hysteresis of several hundred millivolts per Nexperia. Slow rise times from RC-filtered sensors, aged switch contacts, and cable ringing all resolve into one clean trigger event. In industrial panels where a switch can sit meters from the logic board, this removes external hysteresis components from the BOM.

6. Layout, assembly, and speed

Place CEXT as close to the device pins as possible — Nexperia notes that parasitic effects at the timing pins degrade pulse-width accuracy. The 8-VSSOP (DC) package is surface mount with MSL 1 classification, so no dry-pack baking cycle is required before reflow, and the part is RoHS compliant. At 5.3 ns typical propagation delay at 5 V, the one-shot itself will not be the slow element in a control loop.

Takeaway: lock the supply rail, compute REXT and CEXT from t_w = R_EXT x C_EXT before you lay out the board, route the timing capacitor tight to pins 3 and 5, and hold CLEAR high unless you need a hard reset — those four decisions cover the majority of 74LVC1G123DC designs.

What Are the Drop-In Alternatives to the 74LVC1G123DC?

Four alternate orderables are recorded in the XAIPART database. Two are Nexperia variants built on the same die and package; two are Texas Instruments cross-references with identical pinout. None of them requires a PCB change.

The one number that changes a timing budget

The Nexperia part specifies 5.3 ns typical propagation delay at 5 V. The recorded TI SN74LVC1G123DCUT value is 18.5 ns — a 249% increase. Logic behavior, pinout, and 1.65 V to 5.5 V operation stay identical, so the swap is electrically safe at the board level; the risk sits in the timing budget. A design that gates a window at nanosecond resolution must be re-derived after substitution. A design whose pulse window runs in microseconds or milliseconds will not notice the difference.

Takeaway: dual-source with the TI cross-reference for supply security, but treat the 5.3 ns to 18.5 ns propagation-delay gap as a design change, not a documentation change — re-run the timing simulation before you release the alternate.

Is the 74LVC1G123DC in a Healthy Supply Position?

Yes. The XAIPART database lists the 74LVC1G123DC with lifecycle status active and 99,999 units in stock at an MOQ of 1. Prototype quantities and production volumes pull from the same listing, and the tiered price falls as quantity rises:

The pricing snapshot carries a 2026-10-06 timestamp; the distributor listing data in the same XAIPART record carries a 2026-10-05 timestamp. Treat the two as one same-week snapshot, not as a price trend.

The step structure matters for planning. Moving from qty 1 ($0.62) to qty 100 ($0.42) cuts unit cost by 32%. Moving from qty 1 to qty 1000 ($0.28) cuts it by 55%. The largest single break sits at the 100-piece level, where the unit price falls from $0.55 to $0.42 — a 24% step.

Second-source depth is the other supply signal. The TI SN74LVC1G123DCUT and SN74LVC1G123DCUR share pinout and 1.65 V to 5.5 V operation with the Nexperia part, so a dual-source strategy needs no second layout. The 74LVC1G123DC,125 orderable covers tape-and-reel assembly on the same die and package, and the 74LVC1G123DC-Q100H adds AEC-Q100 automotive qualification on that same die and package.

Takeaway: a 99,999-unit position at MOQ 1 with an active lifecycle and two pin-compatible cross-references removes schedule risk for this part — the sourcing decision left to make is which qualification tier (standard, tape-and-reel, or AEC-Q100) your program requires.

What Should Buyers Watch Through 2026 and Beyond?

Rail voltages keep falling — check the minimum VCC first

Designs migrating to 1.8 V and 2.5 V rails stay inside the verified 1.65 V to 5.5 V window of the 74LVC1G123DC. A one-shot specified only for 3.3 V to 5.5 V drops out of those designs. Minimum VCC is the first parameter to check on any cross-reference, before price and before package.

Cross-reference substitutions carry a 249% timing delta

The gap between the Nexperia 5.3 ns typical propagation delay at 5 V and the recorded 18.5 ns for the TI SN74LVC1G123DCUT is the single most misread number in this product family. Because pinout and supply range match, engineers assume the parts are interchangeable in every respect. They are interchangeable electrically, not temporally.

Partial power-down is becoming a requirement, not a feature

Ioff support determines whether a device can sit on a rail that powers down while another rail stays live. As boards add voltage domains, the number of parts that must tolerate partial power-down grows with them. Confirm Ioff before releasing any alternate into a multi-rail design.

Pulse-width accuracy will be decided by the external network

Because t_w = R_EXT x C_EXT, field accuracy tracks resistor tolerance and capacitor stability rather than the IC. Keep CEXT close to pins 3 and 5, and evaluate the pulse window across -40 C to +125 C. Bench data taken at room temperature alone will not predict shift across an industrial temperature swing.

Temperature and qualification tiers drive sourcing decisions

The standard part is specified across -40 C to +125 C, which covers most industrial control, motor-feedback, and instrumentation designs. Automotive programs need the AEC-Q100 qualified 74LVC1G123DC-Q100H, which uses the same die and package as the standard part — the design does not change, only the orderable. Sourcing plans should carry both part numbers from the start; the XAIPART Blog tracks cross-tier availability shifts like this, and the component catalog shows live stock across the logic family.

Takeaway: qualify alternates on minimum VCC, propagation delay, Ioff, and temperature grade — in that order — and you will avoid the two failure modes that actually bite: a part that cannot run on a 1.8 V rail, and a substitute that silently adds 249% to your timing path.