EPM7128SQC100-15: Complete Guide to Altera MAX 7000 128-Macrocell CPLD — Specs, Pinout, Alternatives & Buying Guide

The EPM7128SQC100-15 is an Altera (now Intel) MAX 7000 family Complex Programmable Logic Device (CPLD) that delivers 128 macrocells, 84 user I/Os, and a 15 ns pin-to-pin logic delay (tPD) in a 100-pin PQFP package. It runs from a single 5 V supply with 5% tolerance (4.75 V to 5.25 V), stores its configuration in on-chip EEPROM for instant power-up, and supports in-system programming and boundary-scan test through an IEEE Std. 1149.1 (JTAG) interface. Typical usable density is about 2,500 gates, organized into 4 Logic Array Blocks (LABs) of 16 macrocells each. The part is in last-time-buy (LTB) / legacy status, but XAIPART currently lists 99999 units in stock with pricing from $14.50 at qty 1 down to $8.20 at qty 1,000 as of 2026-09-14, MOQ 1. Note that the standard part is NOT RoHS compliant (SnPb lead finish); the EPM7128SQC100-15N offers the same die and footprint with a lead-free finish.

Quick Answers: What Should Every Buyer Know About the EPM7128SQC100-15?

Before you commit this part to a bill of materials, here are the direct, data-backed answers to the questions engineers and buyers ask most often. The EPM7128SQC100-15 belongs to Altera's MAX 7000 EEPROM-based CPLD family, positioned in the programmable logic hierarchy between simple PLDs and FPGAs: PLD → CPLD → FPGA → SoC FPGA. Because configuration lives in on-chip EEPROM, it boots instantly at power-up without an external configuration PROM — a decisive advantage in deterministic-startup systems such as telecom line cards, industrial safety interlocks, and medical device control boards.

Each macrocell provides 6 to 10 product terms plus a programmable flip-flop, and the MAX (Multiple Array matriX) interconnect routes all LABs through a Programmable Interconnect Array (PIA). The key architectural benefit: propagation delays are fast and predictable regardless of routing density — exactly why MAX 7000 parts remain embedded in long-life programs where deterministic timing matters more than raw density.

Technical Guide: How Do You Select, Design In, and Program the EPM7128SQC100-15?

Power Supply Design

The device uses a single 5 V rail (VCCINT), with all I/O banks deriving from the same VCC — there is no separate VCCIO. Plan an external 5 V regulator with at least 200 mA headroom. Because the rail tolerates only 4.75 V to 5.25 V, regulate accurately and decouple each VCC pin (pins 65 and 100 per the verified pinout) with local 0.1 µF ceramics close to the package. GND pins on the verified pinout appear at pins 11, 21, 31, 41, 51, 61, 72, 82, and 91 — connect all of them solidly to the ground plane.

Interfacing to modern logic requires care: this is a 5 V-only core. When connecting to 3.3 V or 1.8 V logic, add level shifters. Conversely, the 5 V tolerance makes it a drop-in choice for legacy TTL/CMOS buses with no conditioning beyond, in noisy industrial environments, simple resistor dividers on 24 V-conditioned signals.

JTAG Programming and Layout

In-system programming and boundary-scan test run through the IEEE Std. 1149.1 JTAG port. Per the verified pinout: TDI is pin 62, TMS is pin 63, TCK is pin 64, and TDO is pin 95. Supported programming hardware includes Altera's ByteBlasterMV parallel-port cable, ByteBlaster II USB cable, and MasterBlaster serial/USB cable. Software support comes from MAX+PLUS II (fully supported by version 10.23 baseline and earlier); the newer Quartus II programmer also supports the device in JTAG mode.

Follow Altera's JTAG chain layout guidelines to avoid programming failures: pull TCK down, and pull TMS and TDI up. Keep the JTAG traces short and route them away from switching noise sources such as motor-drive traces or backplane clocks.

Global Control Resources

Three dedicated global inputs — GCLK (pin 92), OE (pin 93), and GCLRn (pin 94) — drive synchronous clocking, tri-state output control, and global clear respectively. Use GCLK for all registered timing-critical clocks; the global low-skew network is part of what makes MAX 7000 delays deterministic.

Package, Soldering, and Handling

The 100-pin PQFP has a 0.65 mm pitch with gull-wing leads and a tin-lead (SnPb) finish. Pin 1 is identified by a dot marker on the package top surface. With MSL 3 (168 hours) classification, bake or reseal floor-life-exposed trays before reflow, and use a reflow profile compatible with leaded solder paste. If your build requires RoHS compliance, the SnPb finish is disqualifying — move to the EPM7128SQC100-15N (lead-free NiPdAu finish) instead.

Design Workflow

Entry routes: schematic capture or HDL in MAX+PLUS II 10.23, then fit to the 128-macrocell array, verify timing with the 15 ns tPD figure, and program via JTAG. Because MAX 7000 delays are routing-independent, static timing closes predictably — a single 15 ns worst-case pin-to-pin figure supports roughly 66 MHz operation, suitable for address decoding, chip-select generation, and small state machines.

Alternatives & Comparison: What Are the Drop-In Replacements for the EPM7128SQC100-15?

Three verified alternatives from the MAX 7000 family share the same PQFP-100 footprint. Because they are pin-compatible, they allow speed-grade or finish upgrades with no PCB changes.

Selection guidance: choose the -15N if you need an identical, RoHS-compliant drop-in; choose the -15FN if you additionally need an extended temperature option; choose the EPM7128EQC100-15 if your design benefits from the MAX 7000E family's enhanced expander terms and additional global clocks — it keeps the same pinout and 5 V operation. Speed-grade substitutions are also valid: the EPM7128SQC100-10/-10N (10 ns tPD) drop in for a 5 ns timing improvement, while the -15 can replace a -10 socket if your margins permit the slower propagation. Note: Xilinx XC95144 comparisons and migrations to MAX II EPM240T100C5N or MAX V 5M240ZT100C5N are NOT pin-compatible and require PCB redesign — treat those as new designs, not drop-ins.

Industry Insight: What Is the Market Position and Supply Situation for the EPM7128SQC100-15?

The EPM7128SQC100-15 sits in last-time-buy (LTB) / legacy status. Per Intel/Altera product change notifications cited in the verified database, MAX 7000 PQFP variants have been scheduled for end-of-life, with remaining inventory available through authorized distributors. Lead times from authorized channels run typically 8 to 16 weeks as remaining factory stock is consumed, and broker channels (Heisener reported 13,716 pieces at time of writing) are not replenished.

For buyers, the practical implications are clear. First, XAIPART currently shows 99999 units in stock with tiered pricing as of 2026-09-14: $14.50 (qty ≥ 1), $12.85 (qty ≥ 10), $10.95 (qty ≥ 100), $9.40 (qty ≥ 500), and $8.20 (qty ≥ 1,000). Second, LTB status raises counterfeit risk in the secondary market — always verify parts come from authorized sources. Third, if your program horizon exceeds available inventory, qualify the MAX II EPM240T100C5N or MAX V 5M240ZT100C5N now; both require PCB rework due to different TQFP-100 pinouts, so start that qualification early rather than at the end of your buffer stock. [VERIFY_NEEDED: exact date of final factory orders / last shipments for this specific MPN]

Trends & Outlook: What Should Buyers Watch Going Forward?

Anchor your planning to the verified facts. The 5 V-only, SnPb-finished PQFP architecture of this part has no forward path in new RoHS-compliant, low-voltage designs — modern replacements (MAX II/MAX V in TQFP-100) use 3.3 V-class I/O and different pinouts. The migration trend is therefore one-directional: legacy 5 V maintenance designs stay on MAX 7000 for as long as stock lasts, while everything new goes to MAX II or MAX V. [VERIFY_NEEDED: long-term roadmap commitments for MAX II / MAX V families]

Practical watch items for procurement teams: (1) order design-life quantities now while XAIPART holds 99999 units and MOQ 1 — prices as of 2026-09-14 favor volume breaks sharply ($8.20 at 1,000 pcs vs $14.50 single-unit, a 43% reduction); (2) prefer the EPM7128SQC100-15N for any build that must pass RoHS inspection even in maintenance spares; (3) document a firmware/programming-toolchain plan, since support lives in legacy MAX+PLUS II 10.23 and Quartus II JTAG programming modes; (4) for safety-relevant deployments in medical or industrial contexts, complete risk documentation (e.g., ISO 14971 risk assessment for medical devices, MIL-HDBK-1547 derating for aerospace ground systems) and verify obsolescence status before long-term programs. Buyers who combine these steps with JTAG boundary-scan fixture test will keep legacy 5 V systems serviceable well past the LTB window.