EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
MPN: EPM7128SQC100-15 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.85 | $128.50 |
| 100 | $10.95 | $1,095.00 |
| 500 | $9.4 | $4,700.00 |
| 1,000 | $8.2 | $8,200.00 |
Drop-in alternatives for EPM7128SQC100-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128SQC100-10
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7128SQC100-10N
β Drop-Inβ In Stock
$14.95 / Unit
View Datasheet βEPM7128SQC100-15N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SQC100-15FN
β Drop-Inπ Reference alternative (not in catalog)
EPM7128EQC100-10
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7128EQC100-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7128BTC100-10
β Drop-Inβ In Stock
$11.2 / Unit
View Datasheet βEPM7128SQC100-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Logic Array Blocks (LABs) | 4 (16 macrocells each) |
| User I/Os | 84 |
| Pin-to-Pin Delay (tPD) | 15 ns |
| Typical Gate Count | 2,500 gates |
| Supply Voltage (VCCINT) | 5 V (5% tolerance) |
| Programming Technology | EEPROM (in-system programmable via JTAG) |
| JTAG Interface | IEEE Std. 1149.1 compliant |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) |
| Operating Temperature | 0C to +70C (Commercial) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Non-compliant (SnPb lead finish - legacy PQFP) |
EPM7128SQC100-15 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell-driven bidirectional) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | GND β Ground |
| Pin 62 | TDI β JTAG Test Data In |
| Pin 63 | TMS β JTAG Test Mode Select |
| Pin 64 | TCK β JTAG Test Clock |
| Pin 65 | VCC β +5 V supply |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | GND β Ground |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | I/O β User I/O pin |
| Pin 87 | I/O β User I/O pin |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | GND β Ground |
| Pin 92 | INPUT/GCLK β Global Clock / dedicated input |
| Pin 93 | INPUT/OE β Global Output Enable / dedicated input |
| Pin 94 | INPUT/GCLRn β Global Clear / dedicated input |
| Pin 95 | TDO β JTAG Test Data Out |
| Pin 96 | I/O β User I/O pin |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | VCC β +5 V supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SQC100-15 is suitable for 6 applications: Bus Interface Glue Logic, Industrial Automation and Control, Telecom Backplane Signal Conditioning, Legacy Aerospace Ground Systems, Medical Device Control Logic, Test & Measurement Instrumentation.
Bus Interface Glue Logic
The EPM7128SQC100-15 is widely used as bus-interface glue logic between microprocessors, memories, and peripherals in legacy 5 V systems. Its 128 macrocells and 84 user I/Os provide ample capacity for address decoding, wait-state generation, and chip-select logic across 16/32-bit bus architectures. The 15 ns tPD introduces minimal address-to-CS latency, while the 5 V tolerance allows direct connection to TTL buses without level shifters. Compared to discrete 74-series glue, a single EPM7128SQC100-15 replaces 5 to 15 standard logic packages, simplifying PCB layout and improving reliability in industrial backplanes, VME/PCI bridges, and embedded computing platforms.
Recommended
Industrial Automation and Control
In industrial control systems, the EPM7128SQC100-15 handles deterministic state machines, sensor multiplexing, and motor-drive enable sequencing where predictable timing is paramount. The MAX 7000 architecture delivers fixed propagation delays that are independent of routing density - critical for safety interlocks and deterministic PLC scan cycles. Its 5 V I/O tolerates noisy 24 V-conditioned industrial signals via simple resistor dividers. The 128 macrocells support multiple parallel state machines for conveyor control, robotic arm sequencing, and packaging machinery, while JTAG boundary scan simplifies in-field board test during commissioning.
Recommended
Telecom Backplane Signal Conditioning
The EPM7128SQC100-15 serves telecom backplanes by providing clock distribution, frame synchronization, and line-interface signal conditioning at 5 V TTL levels. Its 84 user I/Os can fan out to multiple line cards while macrocell flip-flops re-time recovered clocks with sub-15 ns jitter. EEPROM-based configuration means the CPLD is ready at power-on without an external configuration PROM - essential for telecom systems that must boot deterministically after a power glitch. Long-life support and PQFP-100 footprint make it a stable choice for maintaining installed T1/E1, SDH, and legacy ATM switch line cards.
Recommended
Legacy Aerospace Ground Systems
Aerospace ground-test equipment and avionics maintenance rigs often retain 5 V TTL logic for backward compatibility with fielded avionics LRUs. The EPM7128SQC100-15 provides configurable stimulus generation, MIL-STD-1553 / ARINC 429 interface glue, and parallel-to-serial conversion in these long-life programs. Its PQFP-100 commercial-temperature package suits ground-bench environments, and the MAX 7000 architecture has decades of field reliability data. Designers should still apply derating per MIL-HDBK-1547 and verify up-to-date obsolescence status before long-term programs.
Recommended
Medical Device Control Logic
The EPM7128SQC100-15 is used in medical device control boards for deterministic sequencing of sensor acquisition, alarm logic, and front-panel I/O in 5 V systems. Its instant-on (EEPROM) configuration is critical for patient-safety devices that must boot reliably after power interruption without relying on external PROMs or firmware. The 15 ns tPD supports real-time control loops in infusion pumps, patient monitors, and diagnostic analyzers. Designers should perform ISO 14971 risk assessment, document firmware lifecycle plans, and verify supply continuity given the part's last-time-buy status.
Recommended
Test & Measurement Instrumentation
The EPM7128SQC100-15 functions as the timing-and-control brain in legacy test and measurement instruments such as logic analyzers, protocol testers, and bench-top data-acquisition systems. Its 84 user I/Os multiplex stimulus channels and capture trigger logic, while macrocell flip-flops synchronize high-speed comparators and ADC sequencers. Deterministic 15 ns timing supports repeatable test sequences required by compliance test rigs (USB, Ethernet, MIL-STD). JTAG boundary scan aids fixture-level board test, and the 5 V tolerance interfaces directly to legacy bench instrumentation signal levels.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SQC100-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQC100-10 | EPM7128SQC100-10N | EPM7128SQC100-15N | EPM7128SQC100-15FN | EPM7128EQC100-10 |
|---|---|---|---|---|---|---|
| Package | 100-pin PQFP (QC100) | 100-pin PQFP (QC100) - same | 100-pin PQFP (QC100) - same | 100-pin PQFP (QC100) - same | 100-pin PQFP (QC100) - same | 100-pin PQFP (QC100) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000E (enhanced) |
| Pin-to-Pin Delay (tPD) | 15 ns | 10 ns (33% faster) | 10 ns | 15 ns (identical) | 15 ns (identical) | 10 ns |
| Macrocells | 128 | 128 (identical) | 128 (identical) | 128 (identical) | 128 (identical) | 128 (identical) |
| User I/Os | 84 | 84 (identical) | 84 (identical) | 84 (identical) | 84 (identical) | 84 (identical) |
| Supply Voltage | 5 V | 5 V (identical) | 5 V (identical) | 5 V (identical) | 5 V (identical) | 5 V (identical) |
| RoHS / Lead-Free | Non-compliant (SnPb) | Non-compliant (SnPb) | Compliant (lead-free) | Compliant (lead-free) | Compliant (lead-free) | Non-compliant (SnPb) |
| Unit Price (qty 1, USD, as of 2026-09-13) | $14.50 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Same die across -15 / -10 / -10N / -15N speed grades (vs EPM7128SQC100-10)
- Lead-free RoHS variant available in same package (vs EPM7128SQC100-15N)
- Drop-in compatible with MAX 7000E family (vs EPM7128EQC100-10)
- 3.3 V core with 5 V-tolerant I/O option (vs EPM7128BTC100-10)
Design Notes
The EPM7128SQC100-15 draws Icc in the range of approximately 100 to 300 mA depending on switching activity and output loading (per MAX 7000 datasheet power-estimation methodology). Estimated: at 5 V Vcc and 200 mA average, the part dissipates roughly 1 W; the PQFP-100 package has theta_JA around 35 C/W, producing a 35C junction rise above ambient at full activity. Provide a 5 V regulator with at least 400 mA capacity and a 1 uF decoupling cap on each Vcc pin pair (pins 65 and 100) placed within 5 mm of the package. Distribute GND (pins 11, 21, 31, 41, 51, 61, 72, 82, 91) across the PCB with a ground plane stitched directly under the device for thermal spreading.
PQFP-100 has a 0.65 mm lead pitch which is hand-solderable but not production-friendly. Use a stencil and reflow profile consistent with J-STD-020 (peak 235 C for SnPb or 245 C for lead-free). Keep all 9 GND pins connected to a single ground plane with multiple vias for low-impedance return paths. Place the JTAG chain header (TCK, TMS, TDI, TDO at pins 62-65 and 95) within 50 mm of the CPLD for reliable programming. If the design also uses an Altera configuration device, daisy-chain the JTAG signals so all devices are in one chain.
With 84 user I/Os at 5 V TTL levels, fan-out is generous (24 mA sink/source per pin on most macrocells), but parallel-bus designs should still use 33 ohm series damping resistors at outputs driving long traces (> 50 mm) to limit ringing. The 15 ns tPD means setup-time margins at clock frequencies above 33 MHz require careful tCO/tSU analysis - prefer the EPM7128SQC100-10 (10 ns) for designs above 40 MHz. Place a global clock input (pin 92 GCLK) where it sees the cleanest clock source and keep its trace length-matched with adjacent I/O to minimize skew across LAB boundaries.
Last-time-buy (LTB) status means factory stock is depleted and authorized distributors may show 0 inventory. Do not start new designs with this part without a qualified second source or design-life inventory purchase. The MAX 7000S toolchain is legacy MAX+PLUS II - if migrating to MAX 7000E (EPM7128EQC100-15), recompile in MAX+PLUS II as the libraries differ slightly. Verify all VCCINT and GND pin pairs are connected; missing a GND pin can cause erratic JTAG programming failures even though the device appears to function. Always pull TCK low through a 1 kohm resistor and TMS/TDI high through 10 kohm resistors when the JTAG header is unconnected, to prevent spurious JTAG state transitions during board reset.
Compliance Information
Standard EPM7128SQC100-15 uses SnPb lead finish and is NOT RoHS compliant. Use the EPM7128SQC100-15N (lead-free) variant for RoHS-compliant builds. Commercial temperature grade (0C to +70C); industrial and military grades are not offered in this part number. Last-time-buy status means future supply is from remaining inventory only.
