EP20K600CF672 vs EP20K600CF672C9N তুলনা
. বিস্তৃত সাথে-সাথে তুলনা EP20K600CF672 নির্দিষ্ট Intel ও EP20K600CF672C9N নির্দিষ্ট Intel. প্রধান বিশেষত্ব, বৈদ্যুতিক প্রাকৃতিক, প্যাকেজিং, জীবনচক্র অবস্থা, মূল্যাঙ্কন, ও পরিসীমা কোন অপশনটির কেন্দ্রীয় নির্ধারণ করুন
Intel
EP20K600CF672 - 600K APEX 20KC FPGA, 672-BGA | Intel
EP20K600CF672 [data_needed: lifecycle status]
বিশিষ্টতা তুলনা
| পারামিটার | EP20K600CF672 | EP20K600CF672C9N |
|---|---|---|
| ব্র্যান্ড | Intel | Intel |
| ক্যাটাগরি | FPGA & CPLD | FPGA & CPLD |
| লাইফসাইকেল স্ট্যাটাস | [DATA NEEDED: Lifecycle Status] | Obsolete |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Product Family | APEX-20KC | — |
| Manufacturer | Altera / Intel | — |
| User I/O Lines | 508 I/O | — |
| Logic Elements | [DATA_NEEDED: logic element count] | 24,320 |
| Propagation Delay | 1.48 ns for supplied EP20K600CF672C9N/C8N references | 1.48 ns (per logic element) |
| Device Type Listed by Supplied References | SPLD | — |
| Process Technology | 0.15 um all-layer copper-metal process for supplied family references | 0.15 µm all-layer copper |
| Performance Claim | Up to 35% faster than APEX 20KE devices | — |
| Package Type | 672-ball BGA, FCBGA | FineLine BGA (FC-FBGA), 1.00 mm pitch, 45 x 45 mm |
| Package Dimensions | 45 mm x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| মাউন্টিং টাইপ | Surface Mount | Surface Mount |
| অপারেটিং তাপমাত্রা | 0 C to 85 C for supplied EP20K600CF672C9N/C8N references | 0 C to 85 C (commercial) |
| Configuration Device Type | Enhanced Configuration (EPC) device | — |
| Core Voltage | [DATA_NEEDED: core supply voltage] | — |
| I/O Voltage | [DATA_NEEDED: I/O supply voltage] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory type and capacity] | — |
| Embedded Memory | [DATA_NEEDED: embedded memory capacity] | MultiCore EABs supporting up to 311,000 RAM bits |
| RoHS স্ট্যাটাস | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| AEC-Q100 Status | unknown | — |
| Family | — | APEX 20KC |
| Device Type | — | Loadable PLD / SRAM FPGA |
| System Gates | — | 600,000 |
| Maximum Operating Frequency | — | 250 MHz |
| Core Supply Voltage | — | 1.71 V to 1.89 V (1.8 V nominal) |
| User I/Os | — | 488 |
| Total Terminals | — | 672 |
| Configuration Interface | — | JTAG (IEEE 1149.1), passive serial, active serial |