10AS066K2F35I2SG vs 10AS057K2F35I2SG Comparison
Detailed side-by-side comparison of 10AS066K2F35I2SG by Intel and 10AS057K2F35I2SG by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | 10AS066K2F35I2SG | 10AS057K2F35I2SG |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5,750.00 | $3,198.40 |
| Product Family | Arria 10 SX SoC FPGA | — |
| Logic Elements | 660,000 | 570K |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Core Clock | 1.5 GHz | — |
| Package | 1152-ball FCBGA (35x35 mm) | 1152-ball FC-FBGA (F35), 35x35 mm |
| Temperature Grade | Industrial (-40C to +100C) | — |
| Speed Grade | 2 (mid-tier) | -2 |
| Process Node | 20 nm TSMC | 20 nm TSMC |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | Compliant | Compliant (lead-free finish) |
| MSL Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | [DATA_NEEDED: DSP block count] |
| Embedded Memory (M20K) | [DATA_NEEDED: M20K count] | — |
| Transceivers | [DATA_NEEDED: transceiver count] | [DATA_NEEDED: transceiver count and max data rate] |
| GPIO | 396 user I/O | — |
| Device Variant | 10AS066K2F35 | — |
| Family | — | Arria 10 SX SoC FPGA |
| Processor Core | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Core Frequency | — | 1.5 GHz |
| Operating Temperature | — | -40C to +100C (Industrial) |
| User I/O Count | — | 396 (per Heisener parametric data) |
| Embedded Memory | — | [DATA_NEEDED: M20K / MLAB bit count] |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, SPI, I2C, NAND/NOR flash controllers, SD/MMC |
| Memory Interfaces | — | DDR3/DDR4/LPDDR3 hard controllers (Arria 10 HPS) |
| Configuration | — | FPGA + HPS independent / coordinated boot |