10AS057K2F35I2SG - Arria 10 SX SoC FPGA 570K LE | Intel
MPN: 10AS057K2F35I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3915.43 | $3,915.43 |
| 10 | $3765.2 | $37,652.00 |
| 100 | $3520.55 | $352,055.00 |
| 250 | $3345.18 | $836,295.00 |
| 500 | $3198.4 | $1,599,200.00 |
Drop-in alternatives for 10AS057K2F35I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS057K2F35I2LG
✅ Drop-In✓ In Stock
$1545 / Unit
View Datasheet →10AS057K2F35I1HG
✅ Drop-In✓ In Stock
$3820 / Unit
View Datasheet →10AS057K2F35E2SG
✅ Drop-In✓ In Stock
$2304.55 / Unit
View Datasheet →10AS057K2F35E2LG
✅ Drop-In✓ In Stock
$3450 / Unit
View Datasheet →10AS057K2F35E1HG
✅ Drop-In✓ In Stock
$1995 / Unit
View Datasheet →10AS057K2F35I2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 570K |
| Processor Core | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Core Frequency | 1.5 GHz |
| Speed Grade | -2 |
| Package | 1152-ball FC-FBGA (F35), 35x35 mm |
| Operating Temperature | -40C to +100C (Industrial) |
| User I/O Count | 396 (per Heisener parametric data) |
| Process Node | 20 nm TSMC |
| HPS Peripherals | EMAC, USB 2.0 OTG, SPI, I2C, NAND/NOR flash controllers, SD/MMC |
| Memory Interfaces | DDR3/DDR4/LPDDR3 hard controllers (Arria 10 HPS) |
| Configuration | FPGA + HPS independent / coordinated boot |
| RoHS Status | Compliant (lead-free finish) |
| Mounting Type | Surface Mount (BGA) |
10AS057K2F35I2SG 1152-ball fc-fbga (f35), 35x35 mm Pin Configuration Guide
Complete pinout information for 10AS057K2F35I2SG (1152-ball fc-fbga (f35), 35x35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS057K2F35I2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS057K2F35I2SG is suitable for 6 applications: Wireless Baseband and Radio Cards, Industrial Machine Vision and Video Processing, Test and Measurement Instrumentation, Military and Aerospace Signal Intelligence, Medical Imaging and Diagnostic Equipment, High-Throughput PCIe Acceleration Cards.
Wireless Baseband and Radio Cards
The 10AS057K2F35I2SG is purpose-built for 4G/5G wireless baseband processing where the dual ARM Cortex-A9 HPS executes MAC-layer scheduling and protocol stacks while the 570K-LE FPGA fabric accelerates FFT, FEC (turbo/LDPC), and beamforming weights. Its integrated transceivers support CPRI line rates up to 9.8 Gbps and JESD204B/C links to RF ADCs/DACs, eliminating external PHY silicon. The -2 speed grade provides the timing margin needed at CPRI 7.2A, while industrial temperature allows outdoor RRH and small-cell deployments. Quartus Prime DSP Builder accelerates algorithm IP integration, and the HPS runs a real-time Linux or RTOS control plane.
Recommended
Industrial Machine Vision and Video Processing
The 10AS057K2F35I2SG's 570K logic elements plus DSP blocks make it well-suited for multi-channel machine vision pipelines where it ingests MIPI CSI-2 or GigE Vision streams, performs Bayer demosaic, lens correction, and CNN inference pre-processing in fabric, while the HPS Linux stack runs OpenCV and inference orchestration. The Arria 10 20nm process delivers roughly 1.5x the DSP performance of the prior Arria V generation, enabling 4K60 processing within power budgets typical of industrial PCs. Industrial temperature qualification supports factory-floor deployments without additional thermal conditioning.
Recommended
Test and Measurement Instrumentation
The 10AS057K2F35I2SG fits high-end oscilloscope, protocol analyzer, and signal-generator platforms where the FPGA fabric implements real-time acquisition, triggering, and DSP while the Cortex-A9 HPS handles display rendering, network connectivity (LXI/SCPI), and user interface. Its multi-gigabit transceivers accept ADC outputs at up to 12.5 Gbps, and the hard PCIe Gen2 x4 endpoint accelerates host-side data upload. The SoC integration reduces BOM and PCB complexity compared to discrete processor+FPGA designs, critical for compact benchtop instruments.
Recommended
Military and Aerospace Signal Intelligence
The 10AS057K2F35I2SG supports SWaP-constrained defense platforms requiring wideband signal capture, demodulation, and direction-finding in a single device. Its industrial temperature range, RoHS-compliant lead-free finish, and long-life-cycle Arria 10 family pedigree make it attractive for upgrade programs where Intel has committed continued support. The dual ARM cores run VxWorks or Green Hills INTEGRITY RTOS for secure deterministic boot, while the FPGA fabric implements channelization, DFT, and digital down-conversion. Hardware AES, secure boot, and tamper detection in the HPS subsystem support anti-tamper requirements.
Recommended
Medical Imaging and Diagnostic Equipment
The 10AS057K2F35I2SG powers high-end ultrasound, CT, and MRI back-end processing where the FPGA fabric executes beamforming, image reconstruction (e.g., back-projection), and Doppler processing at low latency, while the Cortex-A9 HPS runs the user interface and DICOM network stack. The hard PCIe Gen2 endpoint simplifies host integration into clinical workstations. Industrial temperature qualification suits mobile cart and bedside equipment. Long-term Arria 10 silicon availability supports the 10-15 year lifecycle typical of regulated medical device platforms.
Recommended
High-Throughput PCIe Acceleration Cards
The 10AS057K2F35I2SG is commonly used as a PCIe Gen2 x4 / x8 endpoint in FPGA accelerator cards for HPC, financial analytics, and database compression workloads. The hard PCIe IP in Arria 10 SX achieves low-latency DMA into host memory, while the FPGA fabric implements custom data-path accelerators (encryption, regex, compression). The Cortex-A9 HPS can run a lightweight management plane with board-health monitoring. Industrial temperature supports edge-server and telco-datacenter environments without active cooling.
Recommended
Recommended Products Summary
Engineering reference data for 10AS057K2F35I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS057K2F35I2LG | 10AS057K2F35I1HG | 10AS057K2F35E2SG | 10AS057K2F35E2LG | 10AS057K2F35E1HG |
|---|---|---|---|---|---|---|
| Package | 1152-ball FC-FBGA (F35), 35x35 mm | 1152-ball FC-FBGA (F35) - same | 1152-ball FC-FBGA (F35) - same | 1152-ball FC-FBGA (F35) - same | 1152-ball FC-FBGA (F35) - same | 1152-ball FC-FBGA (F35) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 570K | 570K | 570K | 570K | 570K | 570K |
| Speed Grade | -2 | -2 | -1 | -2 | -2 | -1 |
| Temperature Grade | Industrial (-40C to +100C) | Commercial / Extended (0C to +85C) | Industrial (-40C to +100C) | Extended (0C to +100C) | Commercial / Extended (0C to +85C) | Extended (0C to +100C) |
| HPS Core | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| Process Node | 20 nm TSMC | 20 nm TSMC | 20 nm TSMC | 20 nm TSMC | 20 nm TSMC | 20 nm TSMC |
| RoHS Compliant | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Highest speed grade (-2) in the F35 industrial temperature class (vs 10AS057K2F35I1HG)
- Industrial temperature (-40C to +100C) qualification (vs 10AS057K2F35I2LG)
- Heterogeneous SoC FPGA architecture (vs 10AS048K2F35I2SG (Arria 10 SX 480K LE))
Design Notes
The 1152-ball FC-FBGA F35 package requires a high-density PCB stack-up, typically 10 or more layers with sequential lamination for via-in-pad structures. Use microvia (laser-drilled) stack-ups to escape the 1.0 mm ball pitch; follow Intel's recommended land pad and solder mask defined (SMD) or non-solder mask defined (NSMD) pad geometry. Power distribution requires multiple dedicated inner planes with low-inductance decoupling: place 0402/0201 ceramic capacitors within 100 mils of every power pin, and use the Arria 10 SmartVID controller to minimize core-rail leakage.
Estimated: at full HPS (1.5 GHz, both cores active) plus ~80% FPGA fabric utilization, total on-die power can reach 35-45 W. The 35x35 mm F35 package has a typical theta_JA of approximately 8-10 C/W with a properly designed 12-layer PCB thermal via array under the heat-spreader footprint, so the junction can reach 90-100C in still air. A heat sink with thermal interface material (TIM) and 200-400 LFM airflow is recommended for production deployments; thermal simulation in ANSYS Icepak or Siemens FloTHERM is highly advised before committing to enclosure design.
Arria 10 SX transceivers support data rates up to 12.5 Gbps (GX) and 17.4 Gbps (GXT) depending on channel grade; achieving the highest rates requires strict PCB control of channel loss, return loss, and crosstalk. Use HyperLynx or ANSYS SIwave for pre-layout channel simulation, and follow Intel's transceiver channel guidance document for trace width, dielectric selection, and AC-coupling capacitor placement. For HPS DDR3/DDR4 interfaces, run the External Memory Interface Toolkit (EMIF) calibration and validate write/read margins across temperature and voltage corners before tape-out.
Common pitfalls include: (1) mis-assigning the configuration mode pins (MSEL) for the desired AS/PS/FAST configuration scheme, (2) failing to assert the HPS cold-reset sequence properly after POR, leading to HPS boot failure that Quartus Prime software cannot flag, and (3) ignoring SmartVID controller initialization in the board power-up sequence, which can leave the core rail at the wrong voltage and cause intermittent failures. Always validate the pinout in Quartus Prime's Pin Planner and run the TimeQuest timing analyzer across all corners before generating the .sof / .jic files for production.
Compliance Information
RoHS and lead-free per the Intel Altera product page suffix 'G' (Pb-free). Not AEC-Q100 qualified (industrial-grade FPGAs typically are not). REACH compliance assumed based on Intel policy.
