5CSEBA6U19I7LN vs 5CSEBA5U19I7N Comparison
Detailed side-by-side comparison of 5CSEBA6U19I7LN by Intel and 5CSEBA5U19I7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
5CSEBA5U19I7N - Cyclone V SE SoC FPGA 85K LE Dual ARM Cortex-A9 | Intel
5CSEBA5U19I7N ✓ ActiveSpecification Comparison
| Parameter | 5CSEBA6U19I7LN | 5CSEBA5U19I7N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $288.90 | $119.85 |
| Device Family | Cyclone V SE | — |
| Product Type | System-on-Chip (SoC) FPGA | SoC FPGA (System-on-Chip FPGA) |
| Logic Elements | 110K | 85,000 |
| Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Hard Processor Core Count | 2 | — |
| Maximum HPS Clock Frequency | 925 MHz | — |
| Package | 484-UBGA (Ultra FineLine BGA), 19x19 mm | 484-pin UBG (UFBGA) 19x19 mm |
| Pin/Ball Count | 484 | — |
| Process Technology | TSMC 28 nm low-power | 28 nm TSMC low-power |
| Embedded Memory | M10K + MLAB blocks | Approximately 4,450 Kbits |
| DSP Blocks | 18x18 multipliers, fabric-implemented | 87 variable-precision (18x18 multipliers) |
| Hard Memory Controller | DDR3, DDR3L, LPDDR2 with ECC | — |
| Operating Temperature | -40C to +100C (Industrial) | -40C to +100C (Industrial grade, suffix I) |
| Speed Grade | 7 | — |
| RoHS Status | Compliant | Compliant (per Heisener listing and product family) |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| Series | — | Cyclone V SE |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Core Frequency | — | 800 MHz (typical), up to 925 MHz |
| Supply Voltage | — | 1.1 V core |
| FPGA User I/O | — | 66 (per datasheet front-page snippet) |
| Transceivers | — | Up to 5 Gbps (Cyclone V SE feature) |
| HPS Peripherals | — | USB 2.0 OTG, EMAC, CAN, SPI, I2C, UART, SD/MMC, NAND |
| MSL Level | — | [DATA_NEEDED: MSL level] |